JPS58164319U - high frequency circuit - Google Patents
high frequency circuitInfo
- Publication number
- JPS58164319U JPS58164319U JP6143482U JP6143482U JPS58164319U JP S58164319 U JPS58164319 U JP S58164319U JP 6143482 U JP6143482 U JP 6143482U JP 6143482 U JP6143482 U JP 6143482U JP S58164319 U JPS58164319 U JP S58164319U
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- fet
- high frequency
- frequency circuit
- ground conductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Microwave Amplifiers (AREA)
- Waveguides (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図はソース接地用FETの構造の従来例を示す図、
第2図は従来のソース接地FETアンプのFET実装方
法の一例を示す図、第3図は他の例を示す図、第4図は
この考案に用いるソース接地用FETの構造の一例を示
す図、第5図はその実装方法の一例を示す図である。
1Fはソース接地用FET、lはそのパッケージ、2は
ゲートリード、3はドレインリード、4及び5はソース
リード、10は配線基板、11はアース導体、12及び
13はストリップラインである。FIG. 1 is a diagram showing a conventional example of the structure of a source-grounded FET.
FIG. 2 is a diagram showing an example of a FET mounting method for a conventional source-grounded FET amplifier, FIG. 3 is a diagram showing another example, and FIG. 4 is a diagram showing an example of the structure of a source-grounded FET used in this invention. , FIG. 5 is a diagram showing an example of the implementation method. 1F is a source grounding FET, 1 is its package, 2 is a gate lead, 3 is a drain lead, 4 and 5 are source leads, 10 is a wiring board, 11 is a ground conductor, and 12 and 13 are strip lines.
Claims (1)
トリップラインを構成する導体が所定のパターン形状に
被着され、上記配線基板にくり抜き部が設けられ、この
くり抜き部に高周波用FETのパッケージ部分が収納さ
れ、上記FETのゲート電極のリードとドレイン電極の
リードとは互いに対向する一方向に上記パッケージ部分
から設けられて、それぞれ上記配線基板の他面側のスト
リップラインを構成する導体に接続され、上記FETの
ソース電極のリードは上記一方向と同方向に上記パッケ
ージ部分から設けられて上記配線基板の一面側のアース
導体に接続されるようになされた高周波回路。A wiring board has a ground conductor attached to one side, and a conductor constituting a strip line is attached to the other side in a predetermined pattern shape, and a hollow part is provided in the wiring board. A package portion of the FET is housed, and a gate electrode lead and a drain electrode lead of the FET are provided from the package portion in one direction facing each other, and conductors forming strip lines on the other side of the wiring board, respectively. and a lead of a source electrode of the FET is provided from the package part in the same direction as the one direction and connected to a ground conductor on one side of the wiring board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6143482U JPS58164319U (en) | 1982-04-27 | 1982-04-27 | high frequency circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6143482U JPS58164319U (en) | 1982-04-27 | 1982-04-27 | high frequency circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58164319U true JPS58164319U (en) | 1983-11-01 |
JPS622819Y2 JPS622819Y2 (en) | 1987-01-22 |
Family
ID=30071633
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6143482U Granted JPS58164319U (en) | 1982-04-27 | 1982-04-27 | high frequency circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58164319U (en) |
-
1982
- 1982-04-27 JP JP6143482U patent/JPS58164319U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS622819Y2 (en) | 1987-01-22 |
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