JPS61163418U - - Google Patents
Info
- Publication number
- JPS61163418U JPS61163418U JP4606885U JP4606885U JPS61163418U JP S61163418 U JPS61163418 U JP S61163418U JP 4606885 U JP4606885 U JP 4606885U JP 4606885 U JP4606885 U JP 4606885U JP S61163418 U JPS61163418 U JP S61163418U
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- fet
- ground
- mounting pattern
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 230000000087 stabilizing effect Effects 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
Landscapes
- Amplifiers (AREA)
Description
第１図はこの考案の一実施例による増幅器安定
化回路のＦＥＴ部分を示す図であり、第２図は従
来の増幅器安定化回路のＦＥＴ部分を示す図であ
る。
１はＦＥＴチツプ、２はＦＥＴ取付けパターン
、３は信号ラインであるストリツプ線路、４は付
加インダクタ成分用金ワイヤ、５はアースパター
ン、６は付加インダクタ成分用ストヌリツプ線路
、７は調整用金リボンである。なお、図中同一あ
るいは相当部分には同一符号を付してある。
FIG. 1 is a diagram showing the FET part of an amplifier stabilizing circuit according to an embodiment of the invention, and FIG. 2 is a diagram showing the FET part of a conventional amplifier stabilizing circuit. 1 is a FET chip, 2 is a FET mounting pattern, 3 is a strip line that is a signal line, 4 is a gold wire for an additional inductor component, 5 is a ground pattern, 6 is a strip line for an additional inductor component, and 7 is a gold ribbon for adjustment. be. In addition, the same reference numerals are given to the same or corresponding parts in the figures.
Claims (1)
ンと隣り合う２つのアースパターンとを誘電体基
板上に備え、前記取付けパターンとアースパター
ンとを接続し、かつ、その使用本数によつて前記
ＦＥＴのソースとアースの間のインダクタンス値
を任意に設定することができる金ワイヤとを備え
たことを特徴とする増幅器安定化回路。 A FET mounting pattern and two ground patterns adjacent to the mounting pattern are provided on a dielectric substrate, and the mounting pattern and the ground pattern are connected, and depending on the number of FETs used, the source of the FET and the ground pattern are connected. An amplifier stabilizing circuit comprising: a gold wire capable of arbitrarily setting an inductance value between the two wires.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4606885U JPS61163418U (en) | 1985-03-29 | 1985-03-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4606885U JPS61163418U (en) | 1985-03-29 | 1985-03-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61163418U true JPS61163418U (en) | 1986-10-09 |
Family
ID=30560126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4606885U Pending JPS61163418U (en) | 1985-03-29 | 1985-03-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61163418U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017046297A (en) * | 2015-08-28 | 2017-03-02 | 株式会社東芝 | High frequency low-noise amplifier |
-
1985
- 1985-03-29 JP JP4606885U patent/JPS61163418U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2017046297A (en) * | 2015-08-28 | 2017-03-02 | 株式会社東芝 | High frequency low-noise amplifier |
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