JPH0453313U - - Google Patents
Info
- Publication number
- JPH0453313U JPH0453313U JP9569290U JP9569290U JPH0453313U JP H0453313 U JPH0453313 U JP H0453313U JP 9569290 U JP9569290 U JP 9569290U JP 9569290 U JP9569290 U JP 9569290U JP H0453313 U JPH0453313 U JP H0453313U
- Authority
- JP
- Japan
- Prior art keywords
- fet
- microstrip circuit
- microstrip
- terminal
- circuit connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Landscapes
- Amplifiers (AREA)
- Microwave Amplifiers (AREA)
Description
第１図はこの考案の一実施例による高周波低雑
音増幅器を示す構成図、第２図は従来の高周波低
雑音増幅器を示す構成図である。
図中、１はＦＥＴ、２はゲート端子、３はドレ
イン端子、４はソース端子、５はマイクロストリ
ツプ回路、６はグランドパターン、７はセラミツ
ク基板、８はキヤリア、９は金ワイヤ、１０はマ
イクロストリツプ線路である。なお、図中、同一
符号は同一、または相当部分を示す。
FIG. 1 is a block diagram showing a high frequency low noise amplifier according to an embodiment of this invention, and FIG. 2 is a block diagram showing a conventional high frequency low noise amplifier. In the figure, 1 is a FET, 2 is a gate terminal, 3 is a drain terminal, 4 is a source terminal, 5 is a microstrip circuit, 6 is a ground pattern, 7 is a ceramic substrate, 8 is a carrier, 9 is a gold wire, 10 is a microstrip line. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
Ｔのゲート端子に接続される第１のマイクロスト
リツプ回路と、前記ＦＥＴのドレイン端子に接続
される第２のマイクロストリツプ回路と、前記第
１のマイクロストリツプ回路と前記第２のマイク
ロストリツプ回路が取付けられるキヤリアとで構
成される高周波増幅器において、前記ＦＥＴのソ
ース端子とグランドとの間をマイクロストリツプ
線路によつて接続したことを特徴とする高周波低
雑音増幅器。 A field effect transistor (FET) and the FE
a first microstrip circuit connected to the gate terminal of the FET; a second microstrip circuit connected to the drain terminal of the FET; and a carrier to which a microstrip circuit is attached, characterized in that the source terminal of the FET and the ground are connected by a microstrip line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9569290U JPH0453313U (en) | 1990-09-12 | 1990-09-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9569290U JPH0453313U (en) | 1990-09-12 | 1990-09-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0453313U true JPH0453313U (en) | 1992-05-07 |
Family
ID=31834627
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9569290U Pending JPH0453313U (en) | 1990-09-12 | 1990-09-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0453313U (en) |
-
1990
- 1990-09-12 JP JP9569290U patent/JPH0453313U/ja active Pending
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