JPS5952701U

JPS5952701U - Single throw double pole semiconductor switch

Info

Publication number: JPS5952701U
Application number: JP14780582U
Authority: JP
Inventors: 輝雄古屋; 晋啓折目
Original assignee: 三菱電機株式会社
Priority date: 1982-09-29
Filing date: 1982-09-29
Publication date: 1984-04-06
Also published as: JPS635282Y2

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Brief explanation of drawings]

第１図は従来の単投双極形半導体スイッチの構成を示す
斜視図、第２図は一般的なＦＥＴの説明に用いるＦＥＴ
の静特性を示す図、第３図ａ、　　ｂは一般的なマイク
ロストリップ線路から成る９０度コーナの説明に用いる
図で同図ａは不整合なコーナを示す図、同図すは整合さ
れたコーナを示す　　　−図、第４図はこの考案の一実
施例による単投双極形半導体スイッチの構成を示す平面
図である。図中、１は半導体基板、２は地導体、３は主線路、４ａ
、　４ｂは第１及び第２の副線路、５はＦＥＴ１６はド
レイン電極、７ａ、　　７ｂは第１及び第２のソニス電
極、８ａ、　８ｂは第１及び第２のゲート電極、９ａ、
９ｂはバイアス回路、１０は特性曲線、１１は特性曲線
、１２ａ、　　１２ｂハ９０度コーナの内部導体パター
ン、１３はカット面である。なお、薗中同−あるいは相
当部分には同一符号を付して示しである。 −一汗・　　− １＼−＼ −（傳〔コFigure 1 is a perspective view showing the configuration of a conventional single-throw bipolar semiconductor switch, and Figure 2 is an FET used to explain a general FET.
Figures 3a and 3b are diagrams used to explain a 90-degree corner made of a general microstrip line. FIG. 4 is a plan view showing the structure of a single-throw bipolar semiconductor switch according to an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is a ground conductor, 3 is a main line, and 4a
, 4b are the first and second sub-lines, 5 is the drain electrode of the FET 16, 7a and 7b are the first and second sonis electrodes, 8a and 8b are the first and second gate electrodes, 9a,
9b is a bias circuit, 10 is a characteristic curve, 11 is a characteristic curve, 12a and 12b are internal conductor patterns at 90-degree corners, and 13 is a cut surface. It should be noted that identical or equivalent parts are indicated by the same reference numerals. -One sweat・ - 1\-\ -(傳〔こ

Claims

[Scope of utility model registration request]

In a single-throw bipolar semiconductor switch formed by connecting an FET formed on a semiconductor substrate and a microstrip line formed on the semiconductor substrate, a main line, a first sub-line, and a second sub-line formed of the microstrip line are provided. The tip of the line is formed into an isosceles taper, and the tapered part of the main line and the one-side tapered part of the first and second sub-lines are formed so that the main line and the first and second sub-lines are connected to each other. are arranged adjacent to each other so as to be orthogonal to each other, and the adjacent portions of the main line and the first and second sub-lines have an interdigital configuration;
The main line of the interdigital section is used as the drain electrode of the FET, and the first line of the interdigital section is also used as the drain electrode of the FET.
and a second sub-line to the first and second lines of the FET, respectively.
A first gate electrode is formed in a bent structure between the drain electrode and the first source electrode of the FET, and a second gate electrode is formed between the drain electrode and the second source electrode of the FET. 1. A single-throw bipolar semiconductor switch, characterized in that the gate electrode is formed in a bent structure, and means is provided for applying a bias voltage to each of the first and second gate electrodes of the FET.