JPS5856457U - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5856457U JPS5856457U JP14877781U JP14877781U JPS5856457U JP S5856457 U JPS5856457 U JP S5856457U JP 14877781 U JP14877781 U JP 14877781U JP 14877781 U JP14877781 U JP 14877781U JP S5856457 U JPS5856457 U JP S5856457U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- semiconductor equipment
- mos
- transistors
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
- Bipolar Transistors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案による装置の回路図、第2図は第1図に
示す回路の入力−出力特性を示す図、第3図は第1図に
示す回路をモノリシックLSIに適したデバイス構造に
より実現するに最も適した各−デバイス構造の断面図で
ある。
1・・・・・・入力端子、2・・・・・・出力端子、3
・・・・・・pnp゛トランジスタ、4・・・・・・p
、−MOS トランジスタ、5・・・・・・n−MOS
トランジスタ、6・・・・・・npn )ランジスタ、
21・・・・・・p型シリコン基板、22・・・・・・
n型坤込み層、23・・・・・・エピタキシャル層、2
4・・・・・・フィールド5in2膜、25・・・・・
・コレクタ引出し用n型拡散層、26・・・・・・np
n )ランジスタのベース領域、27・・・・・・エミ
ッタ領域、2B、 29. 30・・・・・!それぞ
れエミッタ、ベース、コレクタ電極、3空・・・・−・
ラテラル・トランジスタのコレクタ拡散領域、36・・
・・・・ベース拡散領域、37・・・・・・エミッタ拡
散領域、41. 42. 43・・・・・・それぞれベ
ース、エミッタ、コレクタ電極、51・・・・・・p型
拡散〜領域、52・・・・・・h型ソース領域、53・
・・・;・絶縁膜、 −54・・・・・・多結晶S
iゲート、55・・・・・・ゲート絶縁膜、56・・・
・・・ドレイン領域、61・・・・・・ソース領域、6
2・・・・・・絶縁膜、63・・・・・・ゲート酸化膜
、64・・・・・・多結晶Siゲート、65・・・・・
・ドレイン領域。Figure 1 is a circuit diagram of the device according to the present invention, Figure 2 is a diagram showing the input-output characteristics of the circuit shown in Figure 1, and Figure 3 is a diagram of the circuit shown in Figure 1 with a device structure suitable for monolithic LSI. FIG. 3 is a cross-sectional view of each device structure most suitable for implementation. 1...Input terminal, 2...Output terminal, 3
・・・・・・pnp゛transistor, 4・・・・・・p
, -MOS transistor, 5...n-MOS
transistor, 6...npn) transistor,
21...p-type silicon substrate, 22...
n-type embedded layer, 23... epitaxial layer, 2
4...Field 5in2 membrane, 25...
・N-type diffusion layer for collector drawer, 26...np
n) Base region of transistor, 27...Emitter region, 2B, 29. 30...! Emitter, base, collector electrode, 3 spaces...
Lateral transistor collector diffusion region, 36...
. . . Base diffusion region, 37 . . . Emitter diffusion region, 41. 42. 43...Base, emitter, collector electrode, 51...P-type diffusion region, 52...H-type source region, 53.
・・・;・Insulating film, -54・・・Polycrystalline S
i gate, 55... gate insulating film, 56...
... Drain region, 61 ... Source region, 6
2... Insulating film, 63... Gate oxide film, 64... Polycrystalline Si gate, 65...
- Drain area.
Claims (1)
ジスタのエミッタをそれぞれ正電源、負電源に接続し、
両コレクタを相互に!続して出力端子とし、上記二つの
バイポーラ拳トランジスタのベー −スはそれぞれp−
MOS、n−MOSトランジスタのソースに接続され、
かつ上記二つのMOS)ランジスタのドレインは相互に
接続されて入力端子とし、ゲート電極は出力端子に接続
されていることを特徴とする半導体装置。Connect the emitters of each bipolar transistor, pnp and npn, to the positive power supply and negative power supply, respectively.
Both collectors mutually! The bases of the above two bipolar fist transistors are p-
Connected to the sources of MOS and n-MOS transistors,
and the drains of the two MOS transistors are connected to each other to serve as input terminals, and the gate electrodes are connected to an output terminal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14877781U JPS5856457U (en) | 1981-10-08 | 1981-10-08 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14877781U JPS5856457U (en) | 1981-10-08 | 1981-10-08 | semiconductor equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5856457U true JPS5856457U (en) | 1983-04-16 |
Family
ID=29941578
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14877781U Pending JPS5856457U (en) | 1981-10-08 | 1981-10-08 | semiconductor equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5856457U (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60178670U (en) * | 1984-05-10 | 1985-11-27 | 日本ダイヤバルブ株式会社 | Valve with antistatic device |
JPS6120963U (en) * | 1985-01-04 | 1986-02-06 | 北村バルブ製造株式会社 | Valve with antistatic device |
JPS6184112A (en) * | 1984-10-02 | 1986-04-28 | Fujitsu Ltd | Logical gate circuit |
JPH02122277U (en) * | 1989-03-20 | 1990-10-05 |
-
1981
- 1981-10-08 JP JP14877781U patent/JPS5856457U/en active Pending
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60178670U (en) * | 1984-05-10 | 1985-11-27 | 日本ダイヤバルブ株式会社 | Valve with antistatic device |
JPS6184112A (en) * | 1984-10-02 | 1986-04-28 | Fujitsu Ltd | Logical gate circuit |
JPS6120963U (en) * | 1985-01-04 | 1986-02-06 | 北村バルブ製造株式会社 | Valve with antistatic device |
JPS6326612Y2 (en) * | 1985-01-04 | 1988-07-19 | ||
JPH02122277U (en) * | 1989-03-20 | 1990-10-05 |
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