JPS5815363U - CMOS integrated circuit - Google Patents
CMOS integrated circuitInfo
- Publication number
- JPS5815363U JPS5815363U JP10952481U JP10952481U JPS5815363U JP S5815363 U JPS5815363 U JP S5815363U JP 10952481 U JP10952481 U JP 10952481U JP 10952481 U JP10952481 U JP 10952481U JP S5815363 U JPS5815363 U JP S5815363U
- Authority
- JP
- Japan
- Prior art keywords
- type
- integrated circuit
- type layer
- layer
- cmos integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来構造のＮＰＮ ）ランジスタの断面図、第
２図はＣＭＯＳインバーターの一例の断面図、第３図は
本考案の実施例の断面図を示す。
１．１５．１Ｂ、２１．２５．３２・・・オーミックコ
ンタクトのための高濃度Ｎ型層、２，２０゜２７・・・
オーミックコンタクトのための高濃度Ｐ型層、４．７．
２３・・・Ｐウェル拡散層、５，６゜２２・・・Ｎ型シ
リコン基板、１・・・コレクタ、２・・・ベース、３・
・・エミッタ、９・・・Ｐチャンネルソース、１０・・
・Ｐチャンネルゲート、１２・・・Ｐチャンネルドレイ
ン、１３・・・Ｎチャンネルソース、１６・・・Ｎチャ
ンネルゲート、１９・・・Ｎチャンネルドレイン、２８
・・・コレクター、３１・・・ベース、３０・・・エミ
ッタ。FIG. 1 is a sectional view of a conventional NPN transistor, FIG. 2 is a sectional view of an example of a CMOS inverter, and FIG. 3 is a sectional view of an embodiment of the present invention. 1.15.1B, 21.25.32...High concentration N-type layer for ohmic contact, 2,20°27...
High concentration P-type layer for ohmic contact, 4.7.
23... P well diffusion layer, 5,6° 22... N type silicon substrate, 1... Collector, 2... Base, 3...
...Emitter, 9...P channel source, 10...
・P channel gate, 12...P channel drain, 13...N channel source, 16...N channel gate, 19...N channel drain, 28
...Collector, 31...Base, 30...Emitter.
Claims (1)
型層内のソース及びドレインとなる部分に低濃度Ｎ型層
を形成し、該Ｎ型層の電極接続部分に高濃度Ｎ型層を形
成して、Ｎチャンネルトランジスタを形成するＣＭＯ３
集積回路において前記低濃度Ｎ型層に高濃度Ｐ型層を作
り、ＰＮＰ ）ランジスタを形成することを特徴とする
ＣＭＯ３集積回路。A low concentration P-type diffusion layer is formed on an N-type silicon substrate, and the P-type diffusion layer is formed on an N-type silicon substrate.
CMO3 that forms an N-channel transistor by forming a lightly doped N-type layer in the portions of the type layer that will become the source and drain, and forming a highly doped N-type layer in the electrode connection portions of the N-type layer.
A CMO3 integrated circuit characterized in that a high concentration P type layer is formed in the low concentration N type layer to form a PNP transistor in the integrated circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10952481U JPS5815363U (en) | 1981-07-23 | 1981-07-23 | CMOS integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10952481U JPS5815363U (en) | 1981-07-23 | 1981-07-23 | CMOS integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5815363U true JPS5815363U (en) | 1983-01-31 |
Family
ID=29903904
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10952481U Pending JPS5815363U (en) | 1981-07-23 | 1981-07-23 | CMOS integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5815363U (en) |
-
1981
- 1981-07-23 JP JP10952481U patent/JPS5815363U/en active Pending
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