JPS6015977A - Manufacture of field effect transistor - Google Patents
Manufacture of field effect transistorInfo
- Publication number
- JPS6015977A JPS6015977A JP12283583A JP12283583A JPS6015977A JP S6015977 A JPS6015977 A JP S6015977A JP 12283583 A JP12283583 A JP 12283583A JP 12283583 A JP12283583 A JP 12283583A JP S6015977 A JPS6015977 A JP S6015977A
- Authority
- JP
- Japan
- Prior art keywords
- gaas
- gate metal
- junction
- type
- alloying reaction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 230000005669 field effect Effects 0.000 title claims description 5
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 17
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 238000005275 alloying Methods 0.000 claims abstract description 12
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 238000010438 heat treatment Methods 0.000 claims abstract 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 150000002500 ions Chemical class 0.000 abstract description 8
- 238000005245 sintering Methods 0.000 abstract description 7
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 238000000137 annealing Methods 0.000 abstract description 5
- 239000000758 substrate Substances 0.000 abstract description 4
- 230000001681 protective effect Effects 0.000 abstract description 3
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 238000002513 implantation Methods 0.000 abstract 1
- 229910052759 nickel Inorganic materials 0.000 abstract 1
- 229910052697 platinum Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 12
- 238000005468 ion implantation Methods 0.000 description 3
- UOACKFBJUYNSLK-XRKIENNPSA-N Estradiol Cypionate Chemical compound O([C@H]1CC[C@H]2[C@H]3[C@@H](C4=CC=C(O)C=C4CC3)CC[C@@]21C)C(=O)CCC1CCCC1 UOACKFBJUYNSLK-XRKIENNPSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- UKUVVAMSXXBMRX-UHFFFAOYSA-N 2,4,5-trithia-1,3-diarsabicyclo[1.1.1]pentane Chemical compound S1[As]2S[As]1S2 UKUVVAMSXXBMRX-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 210000002784 stomach Anatomy 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Electrodes Of Semiconductors (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、Ｇａ Ａ ｓを活性層に用いた電界効果１・
ランジスタの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to a field effect system using GaAs as an active layer.
The present invention relates to a method of manufacturing a transistor.
従来１タリの１１”１ｊ成とその問題点ＧａＡｓを用い
た電界効果トランジスタ（以上ＦＥＴと略す）には、Ｐ
ｎ接合型ＦＥＴとンヨノトキ接合型ＦＥＴの２つに大別
される。ノーマリ・オフ型ＦＥＴを用いた論理回路で比
較ずると、Ｐｎ接合型ＦＥＴは、ショノ１・主接合型Ｆ
ＥＴに比して論理振幅が大きく、集積回路には有利であ
る。Conventional 1Tari 11"1J structure and its problems Field effect transistors (hereinafter abbreviated as FET) using GaAs have P
They are roughly divided into two types: n-junction FETs and n-junction FETs. Comparing logic circuits using normally-off FETs, Pn junction FETs are
The logic amplitude is larger than that of ET, which is advantageous for integrated circuits.
一方製造方法を比較すると、Ｐｎ−１と金型ＦＥＴは、
Ｐｎ接合型ＦＥＴ（ｔＪ、、ンヨノ１・主接合型ＦＥＴ
に比して、製造工程が多く、特にノーマリ・オフ型ＦＥ
Ｔのように活性層か薄くなると、薄いＰ型層の形成か難
しく、現在、イオン注入法，拡ｉ欣法等か用いられてい
るか、その市１１ １ＡＩはｇ’Ｌ Ｌ．い。On the other hand, when comparing the manufacturing methods, Pn-1 and mold FET are
Pn junction type FET (tJ, Nyono 1/main junction type FET
There are many manufacturing processes compared to
When the active layer becomes thin like T, it is difficult to form a thin P-type layer, and currently methods such as ion implantation and expansion methods are used. stomach.
第１図（ａ）〜（ｑ）は従来のイオン住人法によるＰｎ
接合型屯昇動果１・ランンスタの製造方法を示したもの
である。まず、同図（ａ）にｉドずように、゛１′−絶
絆性ＧａＡｓ 基板１に、絶縁膜２、フ］トレンスト膜
３をマスクとしてＳｉイオンを高ドース゛で注入し、ソ
ースドレインオーミノクコンタク！・部となるｎ 型領
域４を形成する。次に、同図（ｂ）に示すように、同様
にＳｉイオンをｉ内当なドーズ注入して、活性層となる
ｎ型領域５を形成ずる。次に同図（Ｃ）にイくｔように
絶縁膜６を保護Ｊ摸として高ｉ’ＡａでアニールをイＪ
４：いｎ’、ｎ型イＪ１゛１域４，５を活性化さぜる。Figures 1(a) to (q) show Pn obtained by the conventional ion resident method.
This figure shows a method for manufacturing a joint-type turret lift device 1 and a runner. First, as shown in FIG. 2(a), Si ions are implanted at a high dose into a 1'-absolute GaAs substrate 1 using the insulating film 2 and the free-strength film 3 as masks. Nokkontaku!・An n-type region 4 is formed. Next, as shown in FIG. 4B, Si ions are similarly implanted at a suitable dose to form an n-type region 5 that will become an active layer. Next, annealing is performed at a high i'Aa using the insulating film 6 as a protective layer as shown in FIG.
4: In', activates n-type IJ1'1 regions 4 and 5.
次に同図（ｄ）に示すように、Ｚｎイオンを注入して、
Ｐ型領域７を形成する。次に同図（ｅ）に示すように、
同図（Ｃ）と同様に絶縁膜６を保護膜として高ｉ’Ｍで
アニールを行ないＰ型領域７を活性化させる。次に同図
（ｆ）に示すようにＡｕＧｅを蒸着してシンターを行な
いソース電極８、ドレイン電極９を形成する。次に同図
（ｑ）に示すように、ＡｕＺｎを蒸着してシンターを行
ないゲート電極１０を形成するものである。以上のよう
に、従来の方法では、Ｚｎ６１０人後のアニールか比較
的高温を要するため、Ｚｎの拡散が大きく、薄いＰ型層
を得ることは９！ＩｆＬいし、拡散法でも同様である。Next, as shown in the same figure (d), Zn ions are implanted,
A P-type region 7 is formed. Next, as shown in the same figure (e),
Similarly to FIG. 6C, annealing is performed at high i'M using the insulating film 6 as a protective film to activate the P-type region 7. Next, as shown in FIG. 2F, AuGe is deposited and sintered to form a source electrode 8 and a drain electrode 9. Next, as shown in FIG. 3(q), AuZn is deposited and sintered to form a gate electrode 10. As mentioned above, in the conventional method, Zn610 post-annealing or relatively high temperature is required, so Zn diffusion is large and it is difficult to obtain a thin P-type layer. The same applies to IfL and the diffusion method.
そのため！４Ｓ債回路には、製造工程の簡単なショット
キ型ＦＥＴが多く用いられている。Therefore! Schottky type FETs, which have a simple manufacturing process, are often used in 4S bond circuits.
発明の１三１的
本発明は、かかる問題に鑑み、従来のＰｎ接合型ＦＥＴ
の製造方法に比して、１程数か少なく、７υｉいＰ型層
が容易に得られるＰｎ接合型ＦＥＴの製造方法を提供す
るものである。SUMMARY OF THE INVENTION In view of such problems, the present invention
The purpose of the present invention is to provide a method for manufacturing a Pn junction FET, which can easily obtain a P-type layer with a thickness of about 1 or less and a thickness of 7υi compared to the manufacturing method of the present invention.
発明の構成
本発明は、ＧａＡｓを活性層とするＦＥＴにおいて、ゲ
ート金属としてＰ型不純物となる元素（たとえばＺｎ
、Ｂｅ等）を含み、ＧａＡｓと合金化反応をおこす金属
ｐｔ又はＮ１を用い、加熱を行なって合金化反応をおこ
ない、同１時にＰ型不純物の拡散を促進させ、容易にＰ
ｎ接合型ＦＥＴを得るものである。Structure of the Invention The present invention provides an FET having an active layer of GaAs, in which an element that becomes a P-type impurity (for example, Zn) is used as a gate metal.
, Be, etc.), which causes an alloying reaction with GaAs, is heated to cause an alloying reaction, and at the same time promotes the diffusion of P-type impurities, making it easy to form P-type impurities.
This is to obtain an n-junction FET.
実施例の説明
第２図（ａ）〜（ｆ）は、本発明の一実施例を示したも
のである。DESCRIPTION OF THE EMBODIMENT FIGS. 2(a) to 2(f) show an embodiment of the present invention.
まず同図（ａ）に示すように、半絶縁１生ＧａＡｓ基板
１上に、絶、１ｔｇ２、フォトレジスト膜３をマスクと
して、Ｓｉ イオンを高ドーズでｔＪＥ人し、ソース。First, as shown in FIG. 5A, Si ions are injected at a high dose onto a semi-insulating raw GaAs substrate 1 using the photoresist film 3 as a mask, and then a source is formed.
トレインオーミソクコ／タクト部となるｎＩ鎮域４を形
成する。次に同図（ｂ）に示すようＫｓｔ イオンを所
望のドーズ注入して、ｎ領域の活性層５を形成する。Form the nI area 4 which will become the Train Ohmisokuko/Tact section. Next, as shown in FIG. 4B, Kst ions are implanted at a desired dose to form an n-type active layer 5.
次に同図（ｃ＋）に示すように絶縁膜６を１呆護膜とし
テ、高ｔｆｕｉでアニールを行ないＳ１イオン注入領域
４．５を活性化させる。次に同図（ｄ）に示すように、
ＡｕＧｅを蒸着し、シンターを行ない、ソース電極８、
ドレイン電極９を形成する。次に同図（ｅ）に示すよう
に、第１のゲート金属としてＰ型不純物となるＺｎ１１
を蒸着し、さらにその上に第２のゲート金属としてＰｔ
、１２を蒸着する。次に同図（ｆ）に示すように、適当
な温度（３０ｏ℃〜４６０℃）でシンター行ないゲート
金属１１．１−２とＧａＡｓとを合金化反応を行なわせ
Ｐｎ接合を形成する。Next, as shown in (c+) of the same figure, the insulating film 6 is used as a protective film, and annealing is performed at a high tfui to activate the S1 ion implantation region 4.5. Next, as shown in the same figure (d),
AuGe is deposited and sintered to form a source electrode 8,
A drain electrode 9 is formed. Next, as shown in the same figure (e), Zn11 becomes the P-type impurity as the first gate metal.
Pt is further deposited on top of it as a second gate metal.
, 12 are deposited. Next, as shown in FIG. 6(f), sintering is performed at a suitable temperature (30° C. to 460° C.) to cause an alloying reaction between the gate metal 11.1-2 and GaAs to form a Pn junction.
図中の７はＰ型層を示す。7 in the figure indicates a P-type layer.
一般に、ゲート＜＋’；’、属としてＺｎだけの場合、
ＺｎとＧａＡｓが反Ｌ１−’＝ してＰｎ接合を形成す
るには約６００℃以上の高’１ｍ：でアニールすること
が必要であり、この’ｌ：ｕ’＋度域では、オーミック
電極８，９が劣化する。又、一般にｐｔは２５０℃〜５
００℃でＧａＡｓと合金化反応をおこし、その合金層と
ＧａＡｓがンヨノトキ接合を形成することか知られてい
る。本発明は、このことを応用したものであり、ｐ ｇ
ｌｌｊ不純、吻となるＺｎ上に、ｐｔ を形成して適当
な温度（３００℃〜４５０℃）でシンターすることによ
り、 ｐｔとＧａ Ａｓの合金化反応を行なわせ、同時
にｐｔ前に存在するＺｎかＧａＡｓ中に拡散することを
促進させＰｎ接合を形成するものである。この方法を用
いれは、従来の拡散法、イオン注入法よりも低温で容易
にＰｎ接合を形成すること力ｉｎｆ能で、しかも、Ｐ型
層厚の制御も、低？ＡＡのため正確に制御することが可
能である。In general, if the gate <+';', and Zn is the only genus,
In order to form a Pn junction between Zn and GaAs by anti-L1-'=, it is necessary to anneal at a high temperature of about 600°C or higher. , 9 deteriorate. Also, generally pt is 250℃~5
It is known that an alloying reaction occurs with GaAs at 00° C., and the alloy layer and GaAs form a junction. The present invention applies this fact, and p g
By forming PT on Zn, which becomes an impurity, and sintering it at an appropriate temperature (300°C to 450°C), an alloying reaction between PT and GaAs is carried out, and at the same time, the Zn existing in front of PT is It promotes diffusion into GaAs to form a Pn junction. Using this method, it is possible to easily form a Pn junction at a lower temperature than the conventional diffusion method or ion implantation method, and it is also possible to control the P-type layer thickness. Accurate control is possible due to AA.
ｇ＞図はゲート金属１１．１２のａｓ ｄｅｐｏ （ａ
）とシンター後（５）のＦＥＴのゲート、ソース間順方
向電流覗圧特注を比較したものである。ａｓ ｄｅｐ。g＞The figure shows gate metal 11.12 as depo (a
) and (5) after sintering, the FET's gate-to-source forward current peek pressure is compared. as dep.
では、ショットキ接合のため、順方向電流の立ち」ニリ
ｔｔｒ丁は０．８■ぐらいであるか、シンターすると、
Ｐｎ接合が形成されるため、１蹄壁か人きぐなり、立ち
上り電圧は１．２■ぐらいとなっていることがわかる。Now, because of the Schottky junction, the forward current is about 0.8 mm, or when sintered,
It can be seen that because a Pn junction is formed, the rise voltage is about 1.2 .mu.m.
なお、第１のゲート金属Ｚｎの厚さは、たいたい２００
〜５００八ぐらいが適当である。Note that the thickness of the first gate metal Zn is approximately 200 mm.
~5008 is appropriate.
以上の説明では、Ｐ型不純物となる第１のゲート金属と
してＺｎ 、 ＧａＡｓ と合金化反応をおこす第２の
ゲート金属としてｐｔの場合について述へたが、ｐｔ中
にＺｎが最初から含まれる場合も同様である。合合化反
応をおこす金属としてはＮｉも用いられることはもちろ
んである。In the above explanation, we have described the case where PT is used as the first gate metal that becomes a P-type impurity and the second gate metal that causes an alloying reaction with GaAs. However, in the case where PT contains Zn from the beginning, The same is true. Of course, Ni can also be used as the metal that causes the combination reaction.
発明の効果
以上のように、本発明は従来よりも工程数が少なく、し
かもＰ型層厚の制御が容易なＰｎ接合型ＦＥＴの製造方
法を提供するものであり、集積回路に適して分り歩沼り
の向上をはかるものである。Effects of the Invention As described above, the present invention provides a method for manufacturing a Pn junction FET that requires fewer steps than the conventional method and allows easy control of the P-type layer thickness, and is suitable for integrated circuits. This is intended to improve the quality of the swamp.
しかも、シコノトキ型ＦＥＴを用いたものより論理振幅
か大きくなる。Furthermore, the logic amplitude is larger than that using the Shikonotoki type FET.
第１図（８１〜（ｑｌは従来のＰｎ接合型Ｆ 、Ｅ Ｔ
の製造工程断］ｎ１図、第２図（，１〜（ｆ）は本発明
の一実施例のＰｎ接合型ＦＥＴの製造工程断面図、第３
図は本発明のＦＥＴのａｓ ｄｅｐｏ とシンター後の
ゲート。
ソース順方向′）Ｌ流電圧特性を示す図である。
１・・・・・半導体絶縁性ＧａＡｓ基板、５・・・・・
・ｎ型領域、７・・・・Ｐ型領域、１ｏ・・・・・・ゲ
ート電極（ＡｕＺｎ）、１１・・・・第１のゲート金属
Ｚｎ、１２・・・・・第２のゲート金属Ｐｔ、１３・・
・・・シンター後のゲート電極。
代理人の氏名 弁理士 中 尾 敏 男 ほか１名第１
図
第１図
第 ２ 図
ρ ７
第２図
汐 ！２ ノ／ｑ
（５’ ／３ ｑFigure 1 (81~(ql is the conventional Pn junction type F, ET
1 to 2 (f) are cross-sectional views of the manufacturing process of a Pn junction FET according to an embodiment of the present invention;
The figure shows the FET of the present invention as depo and the gate after sintering. FIG. 4 is a diagram showing the source forward direction')L current voltage characteristics. 1... Semiconductor insulating GaAs substrate, 5...
・N-type region, 7...P-type region, 1o...gate electrode (AuZn), 11...first gate metal Zn, 12...second gate metal Pt, 13...
...Gate electrode after sintering. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 1 Figure 2 Figure ρ 7 Figure 2 Shio! 2 ノ/q (5' /3 q
Claims (2)
不純物と４巽）ノし素を含みＧａ Ａｓと合金化反応を
する金属を用い、／Ｉｌｌ熱を行ない合金化反応を行な
わせてＰ ｎ １．ｉ；音ゲートを上記活性層上に形成
することを特徴とする綴≠郡電界効果トランジスタの製
造方法。(1) Using GaAs as the active layer and a P-type impurity as the gate electrode and a metal that contains nitrogen and undergoes an alloying reaction with GaAs, /Ill heating is performed to cause an alloying reaction and P n 1. i; A method for manufacturing a field effect transistor, characterized in that an acoustic gate is formed on the active layer.
又はＮｉを用いることを特徴とする特）ｉ’ｌ請求の範
囲射１項記戦の寮會阜ｒ比界効果トランンスタの製造方
法０(2) As a metal that undergoes an alloying reaction with GaAs, pt
or a method for manufacturing a field-effect transistor according to claim 1, characterized in that Ni is used.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12283583A JPS6015977A (en) | 1983-07-06 | 1983-07-06 | Manufacture of field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12283583A JPS6015977A (en) | 1983-07-06 | 1983-07-06 | Manufacture of field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6015977A true JPS6015977A (en) | 1985-01-26 |
Family
ID=14845809
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12283583A Pending JPS6015977A (en) | 1983-07-06 | 1983-07-06 | Manufacture of field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6015977A (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5646563A (en) * | 1979-09-26 | 1981-04-27 | Seiko Instr & Electronics Ltd | Static induction transistor |
| JPS5844771A (en) * | 1981-09-10 | 1983-03-15 | Mitsubishi Electric Corp | Junction type field effect transistor and manufacture thereof |
| JPS58143582A (en) * | 1982-02-22 | 1983-08-26 | Toshiba Corp | Manufacture of diffused junction gate fet |
-
1983
- 1983-07-06 JP JP12283583A patent/JPS6015977A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5646563A (en) * | 1979-09-26 | 1981-04-27 | Seiko Instr & Electronics Ltd | Static induction transistor |
| JPS5844771A (en) * | 1981-09-10 | 1983-03-15 | Mitsubishi Electric Corp | Junction type field effect transistor and manufacture thereof |
| JPS58143582A (en) * | 1982-02-22 | 1983-08-26 | Toshiba Corp | Manufacture of diffused junction gate fet |
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