JPS60150677A - Integrated circuit - Google Patents

Abstract

PURPOSE:To prepare an integrated circuit containing a differential amplifying section, threshold voltage thereof hardly disperses, easily by using a field-effect transistor, in which the ions of an N type impurity are implanted to a neutral impurity GaAs semi-insulating semiconductor substrate and activated through heat treatment at a high temperature to form an operating layer, as a constitutional element. CONSTITUTION:The ions of <28>Si as an N type impurity are implanted to a surface section 11 in a GaAs semi-insulating semiconductor substrate 10 containing In as a neutral impurity. A striped pattern 12 coating the position of a gate electrode is formed, and the ions of <28>Si are implanted to sections 13, 14 while using the pattern 12 as a mask. The resist mask 12 is removed, an silicon nitride film is deposited on a crystal surface, and an ion implanted layer is activated through heat treatment in an N2 atmosphere while employing the silicon nitride film as a protective film. The silicon nitride film is removed, and a source electrode 16, a drain electrode 17 and the gate electrode 18 are shaped. An integrated circuit using a differential amplifying section constituted by an FET prepared in this manner as an element as a fundamental circuit is manufactured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to improvements in the characteristics of integrated circuits whose constituent elements are field effect transistors using GaAs as a semiconductor crystal.

[Background technology]

Increasing the operating speed of integrated circuits is of great industrial importance. As a promising means for achieving this goal, research is being widely conducted using GaAs, which has an electron mobility 5 to 6 times higher than that of St, as a semiconductor crystal. As its constituent elements, either a junction field effect transistor or a Schottky gate field effect transistor is usually used.

The cross-sectional structure of a more commonly used Schottky gate field effect transistor is shown in FIGS. 1 and 2. Here, 1 is a GaAs semi-insulating substrate crystal, 2, 20, 21, and 22 are n-type active layers, 3 is a gate electrode, 4 is a source electrode, and 5 is a drain electrode.

Fig. 1 shows an example of groove formation in which the active layer 2 is flat, and Fig. 2 shows an example in which a part of the active layer 20, 22 is gated to reduce series resistance.
This is an example in which the thickness is thicker or the impurity concentration is higher than that of the active layer 21 directly below tA3.

One of the basic characteristic quantities of such a field effect transistor is the threshold voltage vth, which is given by the following first equation.

N vth = vb - -α2(1) 2ε Here, Vb is the built-in voltage, ε is the dielectric constant of the semiconductor crystal, q is the amount of charge, N and n are the thickness of the active layer directly below the gate electrode and its electrons, respectively. It is concentration. In an integrated circuit in which several orders of field effect transistors are formed on the same chip, it is necessary for all transistors on the chip to have a value of vth within a certain tolerance value in order to operate. This tolerance value depends on the circuit system,
Although they differ depending on the degree of integration, it is necessary that the characteristics match extremely well, especially between transistors forming a pair of differential amplifier circuits, and the difference in vth is required to be within several mV.

Conventionally, semi-insulating GaAs as shown in Fig. 1 or 2 was used.
Using chromium or oxygen to form a deep level as a crystal substrate, or a crystal to which both chromium and oxygen are added as impurities, or a crystal grown by the pulling method without adding impurities, this crystal is The active layer of 2.20.21.22 was formed by ion-implanting an n-type impurity, such as Si'', and then performing heat treatment at a high temperature of 800 to 850°C to form the active layer. In the case of Ga
It has been extremely difficult to create integrated circuits using As crystals. In particular, it has been difficult to create a differential amplifier that requires small variations in vth characteristics.

A major reason for the large variation in vth in the conventional method is that dislocations exist in the crystal at a high density of 10,000 #IA/c7n2 or more, which leads to microscopic impurity density distribution and microscopic nonuniform electron concentration. It is for the sake of
The two transistors forming a pair of differential amplifiers are several tens of μm thick.
Even if they are made close to each other, the difference in vth between paired transistors is not sufficiently small due to microscopic non-uniformity in electron concentration, and there is usually a difference of 50 mV or more. As a result, there were some off-cuts, and it was never put into practical use.

[Disclosure of the invention]

The present invention has been made to overcome the above-mentioned difficulties.

The present invention will be described below. As is clear from the first equation, the uniformity of the electron concentration N needs to be sufficiently good in order to reduce the variation in the threshold voltage vth.

The electron concentration N is expressed by the following second equation.

N = r) Nn + NDO-NA□ (2) Here, ND is the concentration of n-type impurity added by ion implantation, η
is the activation rate, and Nn□ is the sum of the n-type level existing in the crystal from the beginning and the n-type level due to defects generated during processes such as high-temperature heat treatment, and NA.

is the sum of the P-type level existing in the crystal from the beginning and the P-type level generated during the process. Therefore, in order to reduce the variation in N, and therefore the variation in threshold value vth, it is necessary to reduce the density of n-type and p-type levels originally contained in the crystal, and to reduce the density of the n-type and p-type levels that are generated during the device fabrication process. It is necessary to make the n-type and p-type level densities small and to make these densities uniform. The present invention has been made from this viewpoint, and by adding an appropriate amount of In to a GaAs crystal, the density of defects such as dislocations in the crystal can be reduced, and the density of n-type and p-type levels originally contained in the crystal can be reduced. It also suppresses defects that occur during the device fabrication process, especially high-temperature heat treatment, and suppresses abnormal diffusion of various impurities that are enhanced by defects during high-temperature heat treatment.
Therefore, an attempt is made to make the electron concentration uniform and to make the threshold value vth uniform.

Examples according to the present invention will be described below.

FIGS. 3(a) to 8(d) show the cross-sectional structure of the field effect transistor portion of the integrated circuit according to this embodiment at each step. Although the present invention is widely applicable without being limited to a particular transistor structure, a specific example will be shown here. The board used for 10 in Figure 3(,) is LE
This is a crystal grown by method C (liquid-filled Czochralski method). Single Ga is placed in a pBN crucible in a high-pressure pulling furnace.
*I n w As and G at high temperature and high pressure.
After synthesizing the aAs polycrystal, the semi-insulating GaAs single crystal containing In is pulled from the In-containing aAs melt. The crystal diameter is 2" to 3", and the wafer is cut to a thickness of about 500 μm from the tip to the back, and then roughly polished to about 50 μm and finished polished to about 30 μm. The wafer used was 3-6×IQ19an-8
It is a semi-insulating GaAs wafer containing In. 28 St ions were applied to this semi-insulating crystal lO at 50 KeV.
3.0X1012 dose/C on the surface area of 11 at
m” ion implantation was performed.

Next, as shown in Figure 3(b), apply a photoresist to a thickness of 1 μm.
A striped pattern 12 covering the gate electrode position was formed by coating the crystal surface to a thickness of 100 mL and performing a normal exposure phenomenon. Using this pattern 12 as a mask, 1111Ss ions were implanted into a portion of 13.14 at 180 KeV at a dose of Ix1013. Further ion implantation was added only to these portions 13 and 14 in order to reduce the series resistance between the gate and source and between the gate and drain.
If ion implantation is not increased in the 3.14 portion, 13.
Due to the depletion effect due to the high density of surface states on the crystal surface of 14, the 13 and 14 portions have a high resistance and do not function satisfactorily as a transistor.

Next, after removing the resist mask 12, plasma CVD
Using NHs gas, 5cH4 gas, and Ng gas as a carrier gas, a silicon nitride film was deposited on the crystal surface using the method.
A thickness of 20 OA was deposited. Using this silicon nitride film as a protective film, heat treatment was performed at 800° C. for 20 minutes in an N2 atmosphere to activate the ion implantation layer. Thereafter, the silicon nitride film was removed, and as shown in FIG. Next, the lift-off method was performed at 400O.
A gate electrode made of a three-layer metal Ti/Mo/Au consisting of Ti of A and Mo of 500 A and Au of 3000 A was formed as shown in FIG. 3(d). Threshold value vt of the Schottky gate field effect transistor created in this way
h was 10.5 V, and its standard deviation was 20 mV for the entire 2-inch wafer 1, with extremely small variations.

By the method described above, an integrated circuit having the differential amplifier section shown in FIG. 4 as a basic circuit was created.

Here, Ql-Qs are a pair of transistors, both of which have a gate length of 1.0 .mu.m and a gate width of 50 .mu.m, and are formed so that the distance between the transistors is approximately 5 .mu.m. At this time, the difference in Vth between the pair of transistors Ql and Q2 is because the defect density in the crystal is small, so the difference in Vth between adjacent transistors is sufficiently small to be 5 mV or less.

Conventionally, a technique for easily producing an integrated circuit including a differential amplifier section with such small variations in vth was unknown and extremely difficult. The present invention is a technology for easily producing an integrated circuit including a high-speed differential amplifier using GaAs, and is of great industrial value.

[Brief explanation of drawings]

Figures 1 and 2 are diagrams showing the structure of a conventional Schottky gate field effect transistor, and Figures 3 (,) (b), (
C) and (d) are diagrams for explaining the process of creating the structure of a field effect transistor of an integrated circuit as an embodiment of the present invention, and Figure 4 is a diagram illustrating a basic differential amplifier section using the structure of the present invention. FIG. 2 is a diagram showing an integrated circuit as a circuit. 1.6...GaAs semi-insulating crystal substrate 2.20.2
1, 22=n-type operating layer 3...Gate electrode 4...Source electrode 5...Drain electrode lO...GaAs Semi-insulating crystal substrate 11...Ga
As Semi-insulating/insulating crystal substrate surface 12...pattern...
Mask 13.14.15...N-type active layer 16...Source electrode 17...Drain electrode 18...Gate electrode W1 Figure 2 Figure *3 Seki (q) 7?3 Figure (b) 2 W3 diagram (C')

Claims (3)

[Claims] (1) GaAs containing neutral impurities After ion-implanting n-type impurities into a semi-insulating semiconductor substrate, it is activated by high-temperature heat treatment to form an active layer. An integrated circuit comprising an amplifier section within the circuit. (2) In as a neutral impurity 1011cm-8-8x
The integrated circuit according to claim 1, characterized in that a semi-insulating semiconductor substrate containing GaAs at a concentration of 10"cm-8 is used. (3) % S i + * S e + * as n-type impurity
After implanting ions such as S+, heat at 800°C20
Claim 1 characterized in that the heat treatment is performed for 1 minute.
Integrated circuits as described in Section.