JPS60150676A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPS60150676A JPS60150676A JP778884A JP778884A JPS60150676A JP S60150676 A JPS60150676 A JP S60150676A JP 778884 A JP778884 A JP 778884A JP 778884 A JP778884 A JP 778884A JP S60150676 A JPS60150676 A JP S60150676A
- Authority
- JP
- Japan
- Prior art keywords
- gaas
- implanted
- heat treatment
- ions
- crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 230000005669 field effect Effects 0.000 claims abstract description 11
- 238000010438 heat treatment Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- 230000007935 neutral effect Effects 0.000 claims abstract 4
- 239000000470 constituent Substances 0.000 claims description 3
- -1 Si+ Chemical class 0.000 claims 1
- 239000013078 crystal Substances 0.000 abstract description 25
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 6
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 3
- 230000001681 protective effect Effects 0.000 abstract description 2
- 239000011248 coating agent Substances 0.000 abstract 1
- 238000000576 coating method Methods 0.000 abstract 1
- 239000006185 dispersion Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 12
- 238000005468 ion implantation Methods 0.000 description 6
- 230000007547 defect Effects 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 235000012431 wafers Nutrition 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- 230000004913 activation Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000012159 carrier gas Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000001568 sexual effect Effects 0.000 description 1
- 230000002194 synthesizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0605—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits made of compound material, e.g. AIIIBV
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/207—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明はＧａＡｓ を半導体結晶として用いた電界効果
トランジスタを構成素子とする集積回路の特性の改良に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to improvements in the characteristics of integrated circuits whose constituent elements are field effect transistors using GaAs as a semiconductor crystal.
集積回路の動作速度を向上することは工業上きわめて重
要である。その有力な手段として半導体結晶に電子移動
度がＳｔ の５〜６倍大きいＧａＡｓを用いる研究が広
く行われている。その構成素子としては接合型電界効果
トランジスタまたはショットキゲート型電界効果トラン
ジスタのいずれかが通常用いられる。Increasing the operating speed of integrated circuits is of great industrial importance. As a promising means for achieving this goal, research is being widely conducted using GaAs, which has an electron mobility 5 to 6 times higher than that of St, as a semiconductor crystal. As its constituent elements, either a junction field effect transistor or a Schottky gate field effect transistor is usually used.
より一般的に用いられているショットキゲート型電界効
果ｌ・ランジスクについてその断面構造を第１図および
第２図に示す。ここで１はＧａＡｓ 半絶縁性基板結晶
、２．２０．２１．２２はｎ型動作層、３はゲート電極
、４はソース電極、５はドレイン電極である。The cross-sectional structure of the more commonly used Schottky gate field effect l-landisk is shown in FIGS. 1 and 2. Here, 1 is a GaAs semi-insulating substrate crystal, 2, 20, 21, and 22 are n-type active layers, 3 is a gate electrode, 4 is a source electrode, and 5 is a drain electrode.
第１図は動作層２が平坦な構造例、第２図は直列抵抗を
低減するために動作層の１部２０，２２をゲー、ト電極
８の真下の動作層２１よりも厚さを厚くまたは不純物濃
度をより大きくした例である。FIG. 1 shows an example of a structure in which the active layer 2 is flat, and FIG. 2 shows a structure in which one part 20, 22 of the active layer is gated to reduce the series resistance, and the thickness is thicker than the active layer 21 directly below the gate electrode 8. Alternatively, this is an example in which the impurity concentration is increased.
このような電界効果トランジスタの基本的な特性ｉ！支
の一つは閾値電圧ｖｔｈであり、次の第１式で与えられ
る。The basic characteristics of such a field effect transistor i! One of the supporting factors is the threshold voltage vth, which is given by the following first equation.
Ｎ
Ｖｔｈ ＝ Ｖ１３−−ａ” （１）
２ε
ここでｖｂ はビルトイン電圧、εは半導体結晶の誘電
率、ｑは電荷宏量、Ｊｅｔはそれぞれゲート電匝頁下部
分の動作層の厚さとその電子濃度である。電界効果トラ
ンジスタを複数個同一チップに形成した集積回路にふ・
いては、このＶｔｈがデツプ上のすべてのトランジスタ
につい−Ｃ１ある一定の許容１直以内の値であることが
、動作するために必要である。この許容（直は回路方式
、集積度で異なるが、例えば直接結合方式（ＤＣＦ Ｌ
）にてｌ Ｋビットメモリを作成するにはｖｔｈの標
準偏差はおよそ３０ｍｖ 以内である必要がある。N Vth = V13--a” (1) 2ε Here, vb is the built-in voltage, ε is the dielectric constant of the semiconductor crystal, q is the amount of charge, and Jet is the thickness of the active layer at the bottom of the gate capacitor and its electrons, respectively. This is the concentration.
In order to operate, this Vth must be within a certain tolerance of -C1 for all transistors on the deep circuit. This tolerance (direct) differs depending on the circuit system and degree of integration, but for example, the direct coupling method (DCF L
), the standard deviation of vth needs to be within about 30 mv.
従来は第１図あるいは第２図の１の半絶縁性ＧａＡｓ
結晶基板として深い準位を形成するクロムまたは酸素、
あるいはクロムと酸素を両者とも不純物として添加した
結晶、あるいは不純物を添加せず引」二げ法にて成長し
た結晶を用い、この結晶にｎ型不純物例えばＳｔ＋をイ
オン注入した後に８００〜８５０’Ｃの高温中にて熱処
理を行い活性化して２．２０．２１，２２の動作層を形
成していたが、このような従来の方法では閾値電圧ｖｔ
ｈのチップ内のばらつきが大きく標準偏差はＪ、ｏｏｍ
ｖ以」二となるのが通常であり、そのためＧａＡｓ 結
晶を用いて集積回路を作成することはきわめて困難であ
った。Conventionally, semi-insulating GaAs as shown in Fig. 1 or 2 was used.
Chromium or oxygen forming deep levels as a crystal substrate,
Alternatively, use a crystal to which both chromium and oxygen are added as impurities, or a crystal grown by the pull-down method without adding any impurities, and after ion-implanting an n-type impurity, such as St+, at 800-850°C. The active layers 2, 20, 21, and 22 were formed by heat treatment and activation at high temperatures, but in such conventional methods, the threshold voltage vt
There is large variation within the chip of h, and the standard deviation is J,oom
It is normal for the GaAs crystal to be less than 2, and therefore it has been extremely difficult to create integrated circuits using GaAs crystals.
本発明は以上に述べた困難を克服するためになされたも
のである。第１式から明らかな工うに、閾値電圧ｖｔｈ
のばらつきを小さくするためには電子濃度Ｎの均一性が
充分に良好である必要がある。The present invention has been made to overcome the above-mentioned difficulties. As is clear from the first equation, the threshold voltage vth
In order to reduce the variation in the electron concentration N, the uniformity of the electron concentration N needs to be sufficiently good.
電子濃度Ｎは次の第２式のようになる。The electron concentration N is expressed by the following second equation.
Ｎ＝ηＮＤ＋ＮＤｏ−ＮＡｏ（２）
ここで、ＮＤ はイオン注入で添加されるｎ型不純物の
濃度、ηは活性化率、ＮＤｏは結晶中に最初から存在す
るｎ型準位および高温熱処理等のプロセス中で発生する
欠陥等によるｎ型準位の総和、ＮＡＯは結晶中に最初か
ら存在するＰ型準位およびプロセス中で発生するＰ型準
位の総和である。従ってＮのばらつきを小さくし、故に
閾値ｖｔｈのばらつきを少なくするためには結晶中にも
ともと含まれているｎ型、Ｐ型の準位密度を小さくシ、
かつデバイス作成プロ七ス中に発生するｎ型Ｐ型の準位
密度を小さくシ、またこれらの密度を均一とする必要が
ある。本発明はかかる観点からなされたものであり、Ｉ
ｎを適量ＧａＡｓ 結晶中に添加することにより、結晶
の欠陥密度を低減し、もともと結晶中に含まれるｎ型、
Ｐ型の準位密度を小さくするとともにデバイス作成プロ
七ス特に高温熱処理によって発生する欠陥を抑制し、高
温熱処理中の欠陥によってエンハンスメントされる各種
不純物の異常拡散を抑圧し、かかるが故に電子濃度の均
一化を図り、閾値ｖｔｈの均一化を達成せんとするもの
である。N=ηND+NDo−NAo (2) Here, ND is the concentration of n-type impurity added by ion implantation, η is the activation rate, and NDo is the n-type level existing in the crystal from the beginning and processes such as high-temperature heat treatment. The sum of n-type levels due to defects etc. generated in the crystal, NAO, is the sum of the P-type levels existing in the crystal from the beginning and the P-type levels generated during the process. Therefore, in order to reduce the variation in N and therefore the variation in the threshold value vth, the density of the n-type and p-type levels originally contained in the crystal should be reduced.
In addition, it is necessary to reduce the n-type and p-type level densities generated during the device fabrication process, and to make these densities uniform. The present invention has been made from this point of view, and I
By adding an appropriate amount of n into the GaAs crystal, the defect density of the crystal can be reduced, and the n-type and
In addition to reducing the P-type level density, it suppresses defects that occur during device fabrication process, especially during high-temperature heat treatment, suppresses abnormal diffusion of various impurities that are enhanced by defects during high-temperature heat treatment, and therefore reduces the electron concentration. The purpose is to achieve uniformity of the threshold values vth.
以下に本発明による実施例につき説明する。Examples according to the present invention will be described below.
第８図（ａ）〜第３図（ｄ）は本実施例による集積回路
の電界効果トランジスタ部分の各工程における断面構造
を示したものである。本発明は特定のトランジスタ構造
に限定されることなく広く適用できるが、ここでは具体
的−例を示す。FIGS. 8(a) to 3(d) show the cross-sectional structure of the field effect transistor portion of the integrated circuit according to this embodiment at each step. Although the present invention is widely applicable without being limited to a particular transistor structure, a specific example will be shown here.
第３図（、）の１０に用いた基板は、ＬＥＣ法（液体封
止式チョクラルスキー法）により成長した結晶である。The substrate used in 10 of FIG. 3(, ) is a crystal grown by the LEC method (liquid-filled Czochralski method).
高圧引上炉内のｐＢＮルツボに単体Ｇａ ＋ Ｉ ｎ
＋Ａｓ を士ットし、高温、高圧下でＧａＡｓ 多結晶
を合成後、Ｉｎを含むＧａＡｓ 融液より、Ｉｎを含む
半絶縁性ＧａＡｓ 単結晶を引き上げる。結晶径は２″
〜３″りで、その先端から後端に向けて、約５００μｍ
の厚さに切り出し後、約５０μｍの荒研磨及び約３０／
ｌ ｍの仕上げ研摩を施したウェハーである。用いたウ
ェハーは３〜６ Ｘ １０”ｃｆｉ−８のＩｎ を含む
半絶縁性ＧａＡｓ ウェハーである。Single Ga + I n in a pBN crucible in a high-pressure pulling furnace
+As, and after synthesizing a GaAs polycrystal at high temperature and high pressure, the semi-insulating GaAs single crystal containing In is pulled from the GaAs melt containing In. Crystal diameter is 2″
~3" length, approximately 500 μm from the tip to the rear end.
After cutting to a thickness of about 50μm, rough polishing and about 30mm
This is a wafer that has undergone final polishing of 1 m. The wafers used were semi-insulating GaAs wafers containing 3-6 x 10'' cfi-8 In.
この半絶縁性結晶ｌＯにＱ ８ Ｓ １イオンを５０
ＫｅＶにて１１の表面部分に１．５ｘ、ＩＯ＋ｐ＋ ド
ーズ／ｃｍｓイオン注入を行った。次に第３図（ｂ）に
示すようにフォトレジストを１μｍの厚さに結晶表面上
に塗布し、通常の露光現像を行うことにより、ゲート電
極位置をおおうストライプ状パターン１２を形成した。50 Q 8 S 1 ions are added to this semi-insulating crystal lO.
A 1.5x IO+p+ dose/cms ion implantation was performed on the surface portion of 11 at KeV. Next, as shown in FIG. 3(b), a photoresist was applied to a thickness of 1 μm on the crystal surface, and conventional exposure and development was performed to form a striped pattern 12 covering the gate electrode position.
このパターン１２をマスクとして Ｓｉイオンを１８０
ＫｅＶにて１３、ｌ ４．の部分にｌＸｌ０１３ド一
ズ↓ｃｍ”イオン注入を行った。この１３．１４０部分
のみにさらにイオン注入を加えたのはゲート・ソース間
およびゲート・ドレイン間の直列抵抗を低減するために
行ったもので、本発明の閾値Ｖｔｈのばらつきが小さい
という特長をよりよく生かせる直接結合回路方式（ＤＣ
ＦＬ）においては、Ｖｔｂをほぼ０．１Ｖ に設定する
ため、この１３．１４部分へのイオン注入増加を行わな
いと、１３、ｌ ４．の結晶表面の高密度の表面準位に
よる空乏効果によって、１３．１４部分がきわめて高抵
抗となり充分にトランジスタとして機能しない。Using this pattern 12 as a mask, apply 180 Si ions to
13 at KeV, l 4. 1Xl013 dos ↓cm" ion implantation was performed in the 13.140 part. Further ion implantation was performed only in this 13.140 part to reduce the series resistance between the gate and source and between the gate and drain. A direct coupling circuit method (DC
FL), since Vtb is set to approximately 0.1V, unless ion implantation is increased to this 13.14 portion, 13, l4. Due to the depletion effect due to the high density of surface states on the crystal surface, the 13.14 portion becomes extremely high in resistance and does not function satisfactorily as a transistor.
次にレジストマスク１２を除去した後、プラズマＣＶＤ
法にてＮＨ，ガス、５ｃＨ４ガスおよびキャリアガスと
してＮ２ガスを用い、結晶表面にシリコン窒化膜を１２
ｏｏＸの厚さ堆積した。このシリコン窒化膜を保護膜と
してＮ２雰囲気中にて８００°Ｃ２０分の熱処理を行い
、イオン注入層の活性化に行った。その後シリコン窒化
膜を除去し、第３図（Ｃ）に示すごと＜１６のソース電
極、１７のドレイン電”ａ ｋ ＡｕＧｅ ／Ｎ ｉ
にてリフトオフ法によって形成し、Ｎ２ 雰囲気中にて
４３０゛ｃ５分間の合金処理を行った。次にリフトオフ
法にて、４０００ＡのＴｉ、５００ＡのＭｏ８０００Ａ
のＡｕ からなる３層金属Ｔｉ／Ｍｏ／Ａｕより成るゲ
ート電極を第３図（ｄ）のごとく形成した。Next, after removing the resist mask 12, plasma CVD
Using NH, gas, 5cH4 gas and N2 gas as a carrier gas, a silicon nitride film was deposited on the crystal surface for 12 minutes.
A thickness of ooX was deposited. Using this silicon nitride film as a protective film, heat treatment was performed at 800° C. for 20 minutes in a N2 atmosphere to activate the ion implantation layer. After that, the silicon nitride film is removed, and as shown in FIG.
The alloy was formed by the lift-off method at 430°C for 5 minutes in a N2 atmosphere. Next, using the lift-off method, 4000A Ti, 500A Mo8000A
A gate electrode consisting of a three-layer metal Ti/Mo/Au consisting of Au was formed as shown in FIG. 3(d).
このようにして作成したショットキゲート型電界効果ｌ
・ランジスタの閾値Ｖｔｈは０．１ｖ であり、その標
準）１１６差は２０ ｍＶであり、きわめてばらつきの
小さいものが得られた。このようにｖｔｈのばらつきを
小さくすることは、集積回路を作成する上で本質的に必
要とされることであり、この結果数千ゲート以上の集積
回路を容易に作成することが可能となった。Schottky gate field effect created in this way
- The threshold value Vth of the transistor was 0.1 V, and the standard)116 difference was 20 mV, resulting in extremely small variation. Reducing the variation in vth in this way is essentially required when creating integrated circuits, and as a result, it has become possible to easily create integrated circuits with several thousand gates or more. .
このように、 ｖｔｈのばらつきの小さい集積回路を容
易に作成する技術は従来は知られておらず、きわめて困
難であった。本発明はＧａＡｓ を用いた高速の高集積
度集積回路を容易に作成する技術であり、工業上の価値
の大きいものである。As described above, a technique for easily producing an integrated circuit with small variations in vth was not known in the past and was extremely difficult. The present invention is a technology for easily producing a high-speed, highly integrated circuit using GaAs, and is of great industrial value.
【図面の簡単な説明】
第１図および第２１ｇ目よ従来のショットキゲート型電
界効果トランジスタの（１１￥造を示す図、第３図（ａ
）、（ｂ）、（Ｃ）及び（ｄ）は本発明の一実施例とし
ての集積回路の電界効果トランジスタの構造を作るプロ
セスを説明するための図である。
１．６．１０・・・ＧａＡｓ 半絶縁性結晶基板２．２
０．２１．２２．１３．１４．１５・・・ｎ型動作層
３．１８・・・ゲート電極
４・、１６・・・ソース電極
５．１７・・・ ドレイン電極
１１・・・ＧａＡｓ 半絶縁性結晶基板表面】２・・・
パターン・マスク
７？１目
大２図
芳３図（０＞
１
大３図（１））
２
７？３図（ｄ）
５[Brief explanation of the drawings] Figures 1 and 21g are diagrams showing the structure of a conventional Schottky gate field effect transistor (11), Figure 3 (a)
), (b), (C), and (d) are diagrams for explaining a process for making a structure of a field effect transistor of an integrated circuit as an embodiment of the present invention. 1.6.10...GaAs semi-insulating crystal substrate 2.2
0.21.22.13.14.15...N-type active layer 3.18...Gate electrode 4, 16...Source electrode 5.17...Drain electrode 11...GaAs semi-insulating sexual crystal substrate surface】2...
Pattern mask 7? 1 large 2 figures Yoshi 3 figures (0> 1 large 3 figures (1)) 2 7? 3 figures (d) 5
Claims (3)
にｎ型不純物をイオン注入した後、高温熱処理を行うこ
とにより活性化して動作層を形成した電界効果トランジ
スタをその構成素子として用いたことを特徴とする集積
回路。(1) GaAs containing neutral impurities After ion-implanting n-type impurities into a semi-insulating semiconductor substrate, it is activated by performing high-temperature heat treatment to form an active layer, and a field-effect transistor is used as its constituent element. Features integrated circuits.
〜３ｘｌ Ｏ＋＊、ｍ−ａの濃度で含むＧａＡｓ 半
絶縁性半導体基板を用いたことを特徴とする特許請求範
囲第１項記載の集積回路。(2) Jl t-IQl as a neutral impurity? crn-a
The integrated circuit according to claim 1, characterized in that a GaAs semi-insulating semiconductor substrate containing GaAs at a concentration of ~3xl O+*, m-a is used.
イオンをイオン注入した後、８００°Ｃ２０分間の熱処
理を行うことを特徴とする特許請求範囲第１項記載の集
積回路。(3) The integrated circuit according to claim 1, wherein after implanting ions such as Si+, Se+, S+, etc. as n-type impurities, a heat treatment is performed at 800° C. for 20 minutes.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP778884A JPS60150676A (en) | 1984-01-18 | 1984-01-18 | Integrated circuit |
| CA000471025A CA1224885A (en) | 1984-01-18 | 1984-12-27 | Integrated circuit and method for producing it |
| EP85300214A EP0149541A3 (en) | 1984-01-18 | 1985-01-11 | Gaas integrated circuit device and method for producing it |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP778884A JPS60150676A (en) | 1984-01-18 | 1984-01-18 | Integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60150676A true JPS60150676A (en) | 1985-08-08 |
Family
ID=11675397
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP778884A Pending JPS60150676A (en) | 1984-01-18 | 1984-01-18 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60150676A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5834980A (en) * | 1981-08-25 | 1983-03-01 | Sumitomo Electric Ind Ltd | Schottky gate field effect transistor |
-
1984
- 1984-01-18 JP JP778884A patent/JPS60150676A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5834980A (en) * | 1981-08-25 | 1983-03-01 | Sumitomo Electric Ind Ltd | Schottky gate field effect transistor |
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