JPS58131774A - Manufacture of gaas schottky barrier type field-effect transistor - Google Patents

Abstract

PURPOSE:To reduce the contact resistance or source resistance of a source and a drain by thermally treating the whole in an atmospheric gas containing As under a state in which only both ion implanted layers of a source prearranged region and a drain prearranged region are coated with insulating films. CONSTITUTION:Si Ions 2 are implanted into a Cr doped semi-insulating GaAs base body 1, and an ion inplanted layer 3 is formed. The surface is coated with CVD SiO2, SiO2 films 341, 342 are left onto the source prearranged region 5 and the drain prearranged region 6, and others are removed. An operating layer 3' and a source region 5' and a drain region 6' are formed through annealing. The SiO2 films 341, 342 are removed, and the wgole surface on the base body is coated with a new SiO2 film. Openings for source and drain electrodes are formed, and metals ohmic-contacting such as Au-Ge are evaporated. The source electrode 8 and the drain electrode 9 are shaped, a predetermined opening for a gate electrode is formed, a gate metal such as Al is evaporated, and the gate electrode 10 is formed.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a GaA* Schottky barrier field effect transistor (GaAs 88 F Fj T ). Since the mobility and saturation speed are higher than that of 81, ultrahigh-speed formation is suitable as a semiconductor material for microwave devices.
IK GmAs 88FITFi is being put into practical use,
Recently, research and development of tGaAa ICs, which use this as the main component, has been actively conducted. Epitaxial growth has been adopted as the wafer manufacturing technology for these devices, but recently ion implantation has become the main component. It's coming. GaAs 8 B by the currently available ion implantation method
FI! I will not talk about the manufacturing method of Gaps '88, as shown in Figure 1 (A).
FET is 8 on a Cr-doped semi-insulating substrate (1).
Next, as shown in FIG. Other parts except the area t, 7 photoresist film or #1sto
, etc., and selectively inject n-type impurity ions (
The 71t% ion implantation layer (3) is also highly concentrated.
inject. Next, the insulating film α4T is removed by etching,
Thereafter, the ion-implanted layer (3
An ion implantation layer (
s), (6)ti, respectively, the source region (5') and drain region (six).

Next, an electrode metal is deposited, which is then heat-treated for gold alloying to form an ohmic contact, and a gate metal is deposited on the source electrode (8) and drain electrode +9) 1, and patterned using a lift-off technique. A gate electrode αG is formed as a Schottky contact, and a GmA@88FBT t- having the structure shown in the same figure (cl) is obtained.

[Problems with background technology]

The feature of this manufacturing method is that the source and drain regions are made with high electron concentration and thick n-type conductive material using ion implantation method.
The contact resistance of the source and drain electrodes, or the source resistance, can be reduced by forming the 88FIT.
l! In addition, in order to reduce the contact resistance, it is necessary to increase the electron concentration on the As surface that contacts the source and drain electrodes, which complicates the T manufacturing process, and also requires a thick conductive layer. In order to obtain this, it is necessary to perform so-called multi-stage ion implantation in which ions are implanted with different acceleration energies, and in this case, the ion implantation process has the disadvantage of requiring a lot of time.

[Purpose of the invention]

This invention eliminates the above-mentioned drawbacks and provides a method for manufacturing a 90aAs Schottky barrier field effect transistor with small source resistance and improved high frequency characteristics without involving complicated processes. [Summary] That is, this invention manufactures a G1 barrier type field effect transistor by an ion implantation method (at this time, an insulating film is deposited only on the ion-implanted layer in the intended source region and the intended drain region). The mold is then heat-treated in a gas-containing atmosphere to reduce mold by t%.

[Example of embroidery of invention]

The embodiments of this invention will be described below with reference to the drawings.
Do A ◎ First, on the stripe diagram 2, a dose of 3.5X'I 912 cm-2 with an acceleration energy of 120 keV is applied.
1 ion implanted into a tCr-doped semi-insulating GmAm substrate and annealed at 850C for 15 minutes to arsine (AaHl).
Ga
A film of 8 io is deposited on the surface of the As substrate and annealed.
The electron concentration distribution υ due to the so-called slow annealing has a higher electron concentration and a wider distribution than the electron concentration distribution (2) due to the filmless annealing. Cr-doped GaA
It is well known that Cr redistribution occurs when a s substrate is annealed at high temperatures o4! In the case of annealing with an 8 kOt film, this effect is remarkable, and a region where Cr atoms are reduced appears near the surface of the GmAm substrate. The above phenomenon occurs similarly when ions are implanted and annealed to a 90A Am substrate; due to the influence of residual donors originally contained in the substrate, the electron concentration distribution due to film annealing is as shown in Figure 2.
It becomes as shown in the + curve.

On the other hand, regarding the uniformity and reproducibility of the characteristics of the injection layer, annealing without a film is superior to annealing with a film, whose characteristics vary greatly depending on the film quality.

Utilizing the characteristics shown in Figure 2, film-less annealing with excellent uniformity is applied to the 8BFgT (D active layer), and film-less annealing is applied to the source and drain regions, which require a high concentration and thick conductive layer. GmAm 88 annealed to
An example of the manufacturing method of FWT will be described using Fig. 3 A to C. In Fig. 3 A, a Cr-doped cow insulating pin
8N ion weight) to 120 with @V energy
1 ion implantation layer (3
) to form.

Next, as shown in Figure 3, c is placed on the ion implantation layer (3).
vn sto, t-deposited and photoetched 8i on the intended source area (5) and intended drain area (6).
01 film (341χ(342) t) is left and the other film is removed. ◎Next, annealing is performed at 850°C for 15 minutes in an atmosphere containing A$ to form the active layer (3') and the source layer as shown in the opening in Figure 3. Zero-order 'IfC5iO1 films (341), (342) in which region'-(5') and drain region (6') are formed.
8i0tl['ie] is deposited on the entire surface of the substrate. Then, holes for the source and drain/electrode are formed by photo-etching using the photoresist film as a mask according to a conventional method, and metals for ohmic contact are formed. , for example A
Deposit u-Go. Then, use a step-off method to leave the ohmic metal only on the source and drain regions. Next, heat treatment is performed under appropriate conditions, for example, at 400°C for 10 minutes, to alloy the metals in ohmic contact, as shown in Figure 3 (
As shown in c), a source electrode (8) and a drain electrode (9) are formed. Next, a predetermined opening for the gate electrode is formed by photoetching again using the photoresist film as a mask, and then a gate metal, for example, 1/1 is deposited, and then the gate electrode 01t is formed using the 7-to-7 method. A barrier-type field effect transistor can be obtained by the steps of 0 or more. In this example, a 5tot film was used as the insulating film, but an 8i, N, film may also be used, and a carbon-doped substrate may be used. Although a GaAs substrate of Process tm
It is possible to provide a method for manufacturing a GaAm Schottky m-type field effect transistor in which the contact resistance of the source and drain or the source resistance can be reduced without the need for

[Brief explanation of the drawing]

Figure 1 shows a conventional GaAs8BFET manufactured by ion implantation.
Figure 2 is a cross-sectional view of the product obtained in the order of the manufacturing process, Figure 2 is a curve diagram showing each electron concentration distribution when the ion-implanted layer is annealed with a separate film and annealed without a film, and Figure 3 is a curve diagram showing the electron concentration distribution of the ion-implanted layer. This is a cross-sectional view of a product obtained in the order of the GaAs8BPIT manufacturing process related to (1)...Semi-insulating GaAm substrate (21, (71)
...N-type impurity ion (3)...Ion implantation layer
(141, (341), (342)...Insulating film (
5) , (61...high concentration ion implantation layer (3')
...Active layer (5')...Source region (6')...
...Drain region (8) ...Source electrode (9)
...Drain electrode Q (1...Gate electrode patent attorney Inoue -Male)

Claims (1)

[Claims] When manufacturing a GaAm Schottky barrier field effect transistor by the ion implantation method, after ion implantation was performed on the surface of a semi-insulating substrate, an insulating film was deposited only on both the ion implantation layers in the intended source and drain regions. Heat treatment in an atmospheric gas containing Yr in the state tII#
Manufacturing method of G1 S Schottky barrier field effect transistor using mold