JPS60130883A - Multilayer printed circuit board - Google Patents
Multilayer printed circuit boardInfo
- Publication number
- JPS60130883A JPS60130883A JP23946783A JP23946783A JPS60130883A JP S60130883 A JPS60130883 A JP S60130883A JP 23946783 A JP23946783 A JP 23946783A JP 23946783 A JP23946783 A JP 23946783A JP S60130883 A JPS60130883 A JP S60130883A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- multilayer printed
- circuit board
- printed circuit
- conductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】 発明の技術分野 本発明に、多層印刷配線板に関する。[Detailed description of the invention] Technical field of invention The present invention relates to a multilayer printed wiring board.
従来技術と問題点
多層印刷配線板Ａ板に、３層以上の導体層の中間に絶ａ
層？弁在し一体化するとともに、任意の導体層相互及び
実装する′電子部品のリードと任意の導体層との接続の
できる印刷配線板？いい１通常。Conventional technology and problems In multilayer printed wiring board A board, there is no aperture between three or more conductor layers.
layer? A printed wiring board that can be integrated and connected to any conductor layer and to the leads of electronic components to be mounted and any conductor layer. Good 1 Normal.
大１！ｌＨ’、以下に述べる諸工程？経て製造さ几る。Big 1! lH', the steps described below? It is manufactured after a long period of time.
（ｉｌｇ−１層（内層導体）ノ（ターンの形成（２１絶
縁層の形成
＋３１接着剤層の形成
（４）接着剤層の表面粗化
＋５１無電解化字（無電解銅）めつき
（６；電解（電気鋼）めっき
（７Ｌｊ’ ２ Ｊｔｌ （土層導体）のパターン形成
（８）ソルダレジスト。マーキング印刷（９）外形加工
しかし、従来の多層印刷配線板は、第１図に示すように
、下ｍ （第１１ｍ）となる導体層１の接続ランド２の
外径寸法と、この導体層１の上にガラスエポキシ材等か
らなる絶縁ｍ３’に介在せしめて形成する上層（２２Ｊ
鱒）となる導体層４の接続ランド５の外径寸法とを同径
に形成しである。(Formation of turns on ilg-1 layer (inner layer conductor) (21 Formation of insulating layer + 31 Formation of adhesive layer (4) Surface roughening of adhesive layer + 51 Electroless plating (electroless copper) (6 ; Pattern formation of electrolytic (electrical steel) plating (7Lj' 2 Jtl (soil layer conductor) (8) Solder resist. Marking printing (9) Outline processing However, conventional multilayer printed wiring boards, as shown in Figure 1, , the outer diameter dimension of the connection land 2 of the conductor layer 1 which is the lower m (11th m), and the upper layer (22J
The outer diameter dimension of the connection land 5 of the conductor layer 4 is formed to have the same diameter as that of the conductor layer 4.
ために、１Ｍ、解めっき工程に続く第２層のパターン形
成工程において下層となる導体層ｌと一上層となる導体
層４とのパターン間に僅かでもズレがある場合には一第
２図において破線で示す三日月状の部分６がエツチング
加工時に溶解さ几、パターン断線となる等の問題がある
。Therefore, if there is even a slight deviation between the patterns of the lower conductor layer l and the upper conductor layer 4 in the second layer pattern forming process following the deplating process, please refer to Figure 2. There are problems such as the crescent-shaped portion 6 shown by the broken line being dissolved during etching, resulting in pattern breakage.
発明の目的
本発明は、上述した問題に鑑み、パターン断線等を生じ
ない品質に優ｎた多層印刷配線板の提供を目的とする。OBJECTS OF THE INVENTION In view of the above-mentioned problems, an object of the present invention is to provide a multilayer printed wiring board with excellent quality that does not cause pattern breakage or the like.
発明の概−決
本発明に、土能目的會達成すべく、下層となる１、ｔ７
．体層の接続ランドに対しこ几と接続する上層となる心
体層の接続ランドを相対的に大径に形成し各層間のパタ
ーンのズレに対処し借るようにしたものである。Summary of the invention - Decision In order to achieve the purpose of the present invention, the lower layer 1, t7
．． The connection land of the core body layer, which is the upper layer, is formed to have a relatively large diameter with respect to the connection land of the body layer, so as to cope with pattern deviation between each layer.
Ｗ流側
以−ト１図面を参１に’ｔ Ｌ、てこの発明の詳細な説
明する。なお、以下の１況明において第１図と同一部分
には同一符号を伺して説明する。The invention of the lever will be described in detail with reference to the drawings. In the following description, parts that are the same as those in FIG. 1 are designated by the same reference numerals.
第３図は２本発明の一実施例を示す部分平面図で、この
実施例の多層印刷配線板に、ガラスエポキシ４（−・四
１ｉ（′からなる絶ｄ層３會弁任せしめて下層の２、Ｊ
１１＋胎１の上に形成した土層の環体）ＶＩ４の接続ラ
ンド５０面径會、下層の導体層ｌの接続ランド２の１【
１径よυ１．１宜に大径に形成しである。FIG. 3 is a partial plan view showing an embodiment of the present invention, in which a multilayer printed wiring board of this embodiment is coated with 3 layers of glass epoxy 4(-41i(') to form a lower layer. 2.J
11 + ring of soil layer formed on layer 1) Connection land 50 surface diameter of VI4, 1 of connection land 2 of lower conductor layer l [
It is formed to have a diameter larger than υ1.1.
したがって、上下の導体層４，１のパターンが上層とな
る導体層４のパターン形成工程において僅かにズしたと
しても、下層となる導体層１の接続ランド２は、土層と
なる心体層４の綴紐ランド５によりカバーさｎる。Therefore, even if the patterns of the upper and lower conductor layers 4, 1 are slightly misaligned during the pattern formation process of the upper conductor layer 4, the connection lands 2 of the lower conductor layer 1 will It is covered by the binding string land 5.
なお、上述した笑流側においては、勇１体Ｊｌ＃を３層
とした場合について述べたが、こ几に限定さ几るもので
はなく１例えば導体層を４層としたもの又は５層以上と
したものにも適用できる。In addition, on the above-mentioned side, we have described the case where 1 body Jl# has 3 layers, but it is not limited to this. For example, it may have 4 conductor layers or 5 or more layers. It can also be applied to
発明の効果
以上の如く本発明によｒしは一従来技術に比し、パター
ン断線等音生ずるおそｎはきわめて少ない。Effects of the Invention As described above, with the present invention, the possibility of occurrence of noise such as pattern disconnection is extremely small compared to the prior art.
７１図及び第２図はそｎぞ扛従米技術の平面１ン１及び
平面説明図、第３図は本発明の一実施例を示す平面図で
ある。
１・・・導体層
２・・・接続ランド
３ ・・・ 絶縁 ノ曽
４・・・導体層
５・・・接続ランド
６・・・三日月状の部分。
ｔｌ、１．、 Ｂ′ｐ出願人 中央銘機工条株式会社第
１図
第２図
第３図Figures 71 and 2 are 1-1 and illustrative plane views of the rice-rubbing technique, and Figure 3 is a plane view showing an embodiment of the present invention. 1... Conductor layer 2... Connection land 3... Insulation Noso 4... Conductor layer 5... Connection land 6... Crescent-shaped part. tl, 1. , B'p Applicant Chuo Meiki Kojo Co., Ltd. Figure 1 Figure 2 Figure 3
Claims (1)
してなるものにおいて、前記下層となる導体層の接続ラ
ンドに対しこｎと接続する上層となる導体層の接続ラン
ド？相対的に大径に形成したことを特徴とする多層印刷
配線孔(1) In a device formed by integrating three or more conductor layers with an insulating layer interposed between them, is the connection land of the upper conductor layer connected to the connection land of the lower conductor layer? Multilayer printed wiring hole characterized by being formed with a relatively large diameter
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23946783A JPS60130883A (en) | 1983-12-19 | 1983-12-19 | Multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23946783A JPS60130883A (en) | 1983-12-19 | 1983-12-19 | Multilayer printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60130883A true JPS60130883A (en) | 1985-07-12 |
| JPH0365677B2 JPH0365677B2 (en) | 1991-10-14 |
Family
ID=17045195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23946783A Granted JPS60130883A (en) | 1983-12-19 | 1983-12-19 | Multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60130883A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6249276U (en) * | 1985-09-13 | 1987-03-26 |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5444772A (en) * | 1977-09-16 | 1979-04-09 | Fujitsu Ltd | Multilayer printed board |
| JPS5583292A (en) * | 1978-12-19 | 1980-06-23 | Matsushita Electric Ind Co Ltd | Device for connecting printed circuit board |
| JPS5612797A (en) * | 1979-07-12 | 1981-02-07 | Matsushita Electric Ind Co Ltd | Multilayer printed circuit board and method of manufacturing same |
| JPS5694070U (en) * | 1979-12-20 | 1981-07-25 | ||
| JPS56115593A (en) * | 1980-02-16 | 1981-09-10 | Elna Co Ltd | Method of connecting flexible printed circuit board |
| JPS56137656A (en) * | 1980-03-31 | 1981-10-27 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Multilayer wiring structure and its manufacture |
| JPS5731876U (en) * | 1975-06-13 | 1982-02-19 | ||
| JPS5759475U (en) * | 1980-09-27 | 1982-04-08 | ||
| JPS57134987A (en) * | 1981-02-16 | 1982-08-20 | Hitachi Ltd | Ceramic circuit board |
| JPS57143891A (en) * | 1981-03-02 | 1982-09-06 | Hitachi Ltd | Multilayer circuit board |
| JPS58131798A (en) * | 1982-01-29 | 1983-08-05 | ソニー株式会社 | Multilayer circuit board |
| JPS593564U (en) * | 1982-06-30 | 1984-01-11 | 富士通株式会社 | Laminated structure of multilayer ceramic substrate |
| JPS5987896A (en) * | 1982-11-10 | 1984-05-21 | 富士通株式会社 | Multilayer printed board |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2435561C3 (en) * | 1974-07-24 | 1981-09-17 | Spenger-Zikesch, geb. Zikesch, Ursula, 8200 Rosenheim | Control valve |
| JPS593564B2 (en) * | 1975-12-08 | 1984-01-25 | 帝人株式会社 | Oyobi Souchi |
| JPS56131355A (en) * | 1980-03-17 | 1981-10-14 | Ootake Menki:Kk | Milling method of noodle band |
-
1983
- 1983-12-19 JP JP23946783A patent/JPS60130883A/en active Granted
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5731876U (en) * | 1975-06-13 | 1982-02-19 | ||
| JPS5444772A (en) * | 1977-09-16 | 1979-04-09 | Fujitsu Ltd | Multilayer printed board |
| JPS5583292A (en) * | 1978-12-19 | 1980-06-23 | Matsushita Electric Ind Co Ltd | Device for connecting printed circuit board |
| JPS5612797A (en) * | 1979-07-12 | 1981-02-07 | Matsushita Electric Ind Co Ltd | Multilayer printed circuit board and method of manufacturing same |
| JPS5694070U (en) * | 1979-12-20 | 1981-07-25 | ||
| JPS56115593A (en) * | 1980-02-16 | 1981-09-10 | Elna Co Ltd | Method of connecting flexible printed circuit board |
| JPS56137656A (en) * | 1980-03-31 | 1981-10-27 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Multilayer wiring structure and its manufacture |
| JPS5759475U (en) * | 1980-09-27 | 1982-04-08 | ||
| JPS57134987A (en) * | 1981-02-16 | 1982-08-20 | Hitachi Ltd | Ceramic circuit board |
| JPS57143891A (en) * | 1981-03-02 | 1982-09-06 | Hitachi Ltd | Multilayer circuit board |
| JPS58131798A (en) * | 1982-01-29 | 1983-08-05 | ソニー株式会社 | Multilayer circuit board |
| JPS593564U (en) * | 1982-06-30 | 1984-01-11 | 富士通株式会社 | Laminated structure of multilayer ceramic substrate |
| JPS5987896A (en) * | 1982-11-10 | 1984-05-21 | 富士通株式会社 | Multilayer printed board |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6249276U (en) * | 1985-09-13 | 1987-03-26 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0365677B2 (en) | 1991-10-14 |
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