JP2006253372A - Multi-layer printed wiring board and its manufacturing method - Google Patents

Multi-layer printed wiring board and its manufacturing method Download PDF

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JP2006253372A
JP2006253372A JP2005067078A JP2005067078A JP2006253372A JP 2006253372 A JP2006253372 A JP 2006253372A JP 2005067078 A JP2005067078 A JP 2005067078A JP 2005067078 A JP2005067078 A JP 2005067078A JP 2006253372 A JP2006253372 A JP 2006253372A
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hole
layer
pattern
multilayer
printed wiring
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Kazuhiko Ohashi
一彦 大橋
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board capable of solving the problem that a multi-layer core printed board has less flexibility of circuit designs because of wiring and connection using through-holes, and also a built-up board has high flexibility of designs, but it is unlikely to be used as a high frequency board because of its variation of a built-up layer. <P>SOLUTION: The multi-layer core board 12 in which a first core insulating layer 4 is put between a second core insulating layer 10 and a third core insulating layer 11, includes internal layer patterns 3, 5 on the inside thereof, and includes an upper layer pattern 1 and a lower layer pattern 6 on the outside thereof. Metal plating 9 is applied to inner surfaces of through-holes 8 formed in the multi-layer core board 12 to electrically connect the internal layer patterns 3, 5, and resin 13 is embedded in the through-holes 8. A receiving pattern 17 for the through-hole 8 is eliminated together with a part of the metal plating 9 in the through-holes 8 in etching of the lower layer pattern 6 to prevent the electrical connection between the lower layer pattern 6 and the internal layer patterns 3, 5, and to permit the electrical connection between the upper layer pattern 1 and the internal layer patterns 3, 5. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明は、多層プリント配線基板およびその製造方法に関するものである。   The present invention relates to a multilayer printed wiring board and a method for manufacturing the same.

従来の多層プリント配線基板は、図6に示すように、絶縁層基板の両面に接着された金属膜の導体層を、エッチング等の処理によって所望のパターン回路としての第1,第2の内層パターン3,5を形成してなる第1のコア絶縁層4と、この第1のコア絶縁層4と、金属膜の導体層が片面接着された半硬化状態の第2のコア絶縁層10および第3のコア絶縁層11とを有し、第2のコア絶縁層10および第3のコア絶縁層11の導体層が外面となるように、第1のコア絶縁層4を、第2のコア絶縁層10および第3のコア絶縁層11によって上下から挟み込み、熱プレス等で積層した多層コア基板を形成する。   As shown in FIG. 6, the conventional multilayer printed wiring board has first and second inner layer patterns as a desired pattern circuit by etching a metal film conductor layer bonded to both surfaces of an insulating layer substrate. 3 and 5, the first core insulating layer 4, the second core insulating layer 10 in a semi-cured state in which the conductor layer of the metal film is bonded on one side, and the first core insulating layer 4. 3, and the first core insulating layer 4 is the second core insulating layer so that the conductor layers of the second core insulating layer 10 and the third core insulating layer 11 are on the outer surface. A multilayer core substrate is formed which is sandwiched from above and below by the layer 10 and the third core insulating layer 11 and laminated by hot pressing or the like.

この多層コア基板に貫通孔8を形成し、貫通孔8の内部表面に金属メッキ9を施した後、貫通孔8内部に絶縁性の樹脂13を充填する。そして、前記コア多層基板の両面の金属膜の導体層をエッチング等により配線パターンや貫通孔の受けパターンとなる上層パターン1および下層パターン6を形成することにより、コア多層プリント配線基板が構成される。   A through hole 8 is formed in the multilayer core substrate, and a metal plating 9 is applied to the inner surface of the through hole 8, and then an insulating resin 13 is filled into the through hole 8. Then, the core multilayer printed wiring board is configured by forming the upper layer pattern 1 and the lower layer pattern 6 to be the wiring pattern and the through hole receiving pattern by etching or the like on the conductive layers of the metal films on both surfaces of the core multilayer board. .

ここで貫通孔の受けパターンとは、貫通孔の内部表面に金属メッキをする時に必要なパターンであり、少なくとも貫通孔の直径より50μm以上大きなパターンである。この受けパターンは、各層の配線パターンと一緒に含まれていることが多い。しかし、このコア多層プリント配線基板では、配線パターン設計の制約が多く、また貫通孔の径を小さくすることができない。また、貫通孔同士の距離も必要となり設計の自由度が非常に少ない。   Here, the through hole receiving pattern is a pattern required when metal plating is performed on the inner surface of the through hole, and is a pattern that is at least 50 μm larger than the diameter of the through hole. This receiving pattern is often included together with the wiring pattern of each layer. However, in this core multilayer printed wiring board, there are many restrictions on the wiring pattern design, and the diameter of the through hole cannot be reduced. In addition, the distance between the through holes is required, and the degree of design freedom is very small.

そのため、近年では、図7に示すように、前記第1のコア絶縁層4の基板に貫通孔8を設け、この貫通孔8の内部表面に金属メッキ9を施し、絶縁性の樹脂13を充填して、表面導体層をエッチング等で第1,第2の内層パターン3,5を形成した第1のコア絶縁層4上に、ビルトアップ絶縁層2を形成する。このビルトアップ絶縁層2をレーザ加工等で第1のコア絶縁層4の導体層までビアホール7を空けて、このビアホール7に金属メッキ9を施して、第1のコア絶縁層4の第1,第2の内層パターン3,5と電気的接続を行う。この繰り返しを行って積層されたビルトアップ多層プリント配線基板が、現在広く使用されている。
特開平10−341077号公報 特開2001−257470号公報
Therefore, in recent years, as shown in FIG. 7, a through hole 8 is provided in the substrate of the first core insulating layer 4, a metal plating 9 is applied to the inner surface of the through hole 8, and an insulating resin 13 is filled. Then, the built-up insulating layer 2 is formed on the first core insulating layer 4 on which the first and second inner layer patterns 3 and 5 are formed by etching or the like of the surface conductor layer. Via holes 7 are made in the built-up insulating layer 2 to the conductor layer of the first core insulating layer 4 by laser processing or the like, and metal plating 9 is applied to the via holes 7, so that the first, Electrical connection is made with the second inner layer patterns 3 and 5. A built-up multilayer printed wiring board laminated by repeating this process is widely used at present.
Japanese Patent Laid-Open No. 10-341077 JP 2001-257470 A

多層プリント配線基板において、コア多層プリント配線基板の場合には、貫通孔を用いて各層間の電気的接続を行うため、内層間同士の電気的接続ができない。そのため層間違いで電気的接続が必要な場合、ビルトアップ多層プリント配線基板が用いられる。ビルトアップ絶縁層のビアホールは、ビアの加工にレーザ等を用いて下層の導体パターンまで孔を空けることができるため、容易にビアホールを形成することができる。また、孔径も貫通孔よりも小さくすることができ、ビア間隔も貫通孔に対し狭くすることができる。そのため層間の電気的接続場所を自由に変えることができ、基板設計の自由度が大きくなる。   In a multilayer printed wiring board, in the case of a core multilayer printed wiring board, since electrical connection between each layer is performed using a through hole, electrical connection between inner layers cannot be performed. Therefore, a built-up multilayer printed wiring board is used when electrical connection is necessary due to a layer error. Since the via hole in the built-up insulating layer can be drilled to the underlying conductor pattern using a laser or the like for processing the via, the via hole can be easily formed. Also, the hole diameter can be made smaller than the through hole, and the via interval can be made narrower than the through hole. Therefore, the electrical connection place between the layers can be freely changed, and the degree of freedom in the board design is increased.

しかし、ビルトアップ絶縁層は粘度が低いため、層厚を大きくすることが困難である。また、層厚のバラツキもコア層に対して大きく、特に高周波多層プリント配線基板として用いた場合、マイクロストリップラインの特性インピーダンスが安定しない要因となる。   However, since the built-up insulating layer has a low viscosity, it is difficult to increase the layer thickness. Further, the variation in the layer thickness is large with respect to the core layer, and when used as a high-frequency multilayer printed wiring board, the characteristic impedance of the microstrip line becomes unstable.

製造工程においてもコア基板の両面パターン形成後、ビアホールを作成してメッキを施し、絶縁性の樹脂を充填してビルトアップ絶縁層が積層され、レーザ加工などによりビアホールを作成するためコア多層プリント配線基板を作成する工程時間よりも長く、また工数も多くなるため製造コストの上昇となる。   In the manufacturing process, after forming the double-sided pattern on the core substrate, via holes are created, plated, filled with an insulating resin, a built-up insulating layer is laminated, and core multilayer printed wiring is used to create via holes by laser processing etc. The manufacturing time is increased because the process time is longer than the process of creating the substrate and the number of steps is increased.

本発明は、コア多層プリント配線基板の工程を用いながらも、上記従来技術の課題を解決した多層プリント配線基板およびその製造方法を提供することを目的とする。   It is an object of the present invention to provide a multilayer printed wiring board and a method for manufacturing the same, which solve the above-described problems of the prior art while using the core multilayer printed wiring board process.

上記目的を達成するために、本発明の多層プリント配線基板の構成は、2層以上ある多層基板と、前記多層基板を貫通し、内部周辺を金属メッキしてなる貫通孔と、前記貫通孔内部に充填された樹脂とを有し、前記金属メッキによって前記多層基板における上下の配線パターンを電気的に接続する多層プリント配線基板において、前記貫通孔を、前記貫通孔における多層基板の上面、下面の少なくともどちらかに受けパターンのない構成としたことを特徴とする。   In order to achieve the above object, the multilayer printed wiring board according to the present invention comprises a multilayer board having two or more layers, a through hole penetrating the multilayer board and metal-plated inside, and the inside of the through hole. In the multilayer printed wiring board that electrically connects the upper and lower wiring patterns in the multilayer board by the metal plating, the through hole is formed on the upper surface and the lower surface of the multilayer board in the through hole. It is characterized in that at least either one has no receiving pattern.

また本発明は、受けパターンのない前記貫通孔内部の金属メッキの一部をエッチングしたことを特徴とする。   Further, the present invention is characterized in that a part of the metal plating inside the through hole without the receiving pattern is etched.

また本発明は、前記多層基板に、ビルトアップ絶縁層を少なくとも1層積層したことを特徴とする。   According to the present invention, at least one built-up insulating layer is laminated on the multilayer substrate.

また本発明は、受けパターンのない前記貫通孔をレジスト膜で覆ったことを特徴とする。   Further, the present invention is characterized in that the through hole having no receiving pattern is covered with a resist film.

また本発明は、前記受けパターンのない貫通孔と前記多層基板の2層を使って配線パターンを引くことによりインダクタ成分を持たせた構造としたことを特徴とする。   Further, the present invention is characterized in that an inductor component is provided by drawing a wiring pattern using two layers of the through hole without the receiving pattern and the multilayer substrate.

また本発明は、前記受けパターンのない貫通孔を用いて、配線パターンと貫通孔のグランドとの干渉を小さくしたことを特徴とする。   The present invention is characterized in that interference between the wiring pattern and the ground of the through hole is reduced by using the through hole without the receiving pattern.

また本発明は、2層以上ある多層基板と、前記多層基板を貫通し、内部周辺を金属メッキしてなる貫通孔と、前記貫通孔内部に充填された樹脂とを有し、前記金属メッキによって前記多層基板における上下の配線パターンを電気的に接続する多層プリント配線基板の製造方法において、前記多層基板の上下面に形成した導電層をエッチングして配線パターンを形成すると同時に、前記貫通孔の受けパターンをエッチングすることを特徴とする。   The present invention also includes a multilayer substrate having two or more layers, a through-hole formed by metal plating around the inside of the multilayer substrate, and a resin filled in the through-hole. In the method of manufacturing a multilayer printed wiring board in which upper and lower wiring patterns in the multilayer board are electrically connected, the conductive layers formed on the upper and lower surfaces of the multilayer board are etched to form a wiring pattern, and at the same time, receive the through-hole. The pattern is etched.

また本発明は、前記貫通孔の受けパターンのエッチングと同時に前記貫通孔の金属メッキの一部をエッチングすることを特徴とする。   Further, the present invention is characterized in that a part of the metal plating of the through hole is etched simultaneously with the etching of the receiving pattern of the through hole.

このように構成した本発明によれば、貫通孔を用いても最上層と内層、内層と最下層、内層間同士の電気的な接続でき、またそれによる工程を新たに追加する必要もなく短期間で作成することが可能である。更に、ビルトアップ層基板も用いず、半硬化状態の絶縁層基板を用いて積層するため絶縁層の厚みが安定しており、高周波用の多層プリント配線基板としても用いることができる。   According to the present invention configured as above, the uppermost layer and the inner layer, the inner layer and the lowermost layer, and the inner layer can be electrically connected to each other even if through holes are used, and there is no need to add a new process for a short time. It is possible to create between. Furthermore, since the laminated layer is formed using a semi-cured insulating layer substrate without using a built-up layer substrate, the insulating layer has a stable thickness, and can be used as a multilayer printed wiring board for high frequencies.

また、貫通孔内部表面の金属メッキがエッチング時に除去されるので、貫通孔と周りの配線パターンとの電磁界の干渉も起きにくい。そのため貫通孔の周辺まで配線パターンを持ってくることができるため配線のために基板面積を大きくする必要もない。   Further, since the metal plating on the inner surface of the through hole is removed during the etching, the interference of the electromagnetic field between the through hole and the surrounding wiring pattern hardly occurs. Therefore, since the wiring pattern can be brought to the periphery of the through hole, it is not necessary to increase the substrate area for wiring.

本発明によれば、ビルトアップ基板を用いることなく、貫通孔で層間の電気的接続ができるために従来よりも設計の自由度をあげることができ、新たな工程も追加せずに多層プリント配線基板を提供することができる。   According to the present invention, it is possible to increase the degree of design freedom as compared with the prior art because the electrical connection between the layers can be made through the through-hole without using a built-up board, and multilayer printed wiring without adding a new process. A substrate can be provided.

以下、本発明の実施形態について、図面を参照しながら説明する。   Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(第1の実施の形態)
図1は本発明の第1の実施の形態の多層配線プリント基板の構造を示す説明図である。第1のコア絶縁層4は、上下の導体層である第1の内層パターン3と第2の内層パターン5とによって挟まれており、さらに第1のコア絶縁層4を、第2のコア絶縁層10と第3のコア絶縁層11とによって挟みこむことによって多層コア基板12が構成される。この多層コア基板12の上下の面には導体層による配線パターンである上層パターン1と下層パターン6が形成されている。
(First embodiment)
FIG. 1 is an explanatory diagram showing the structure of the multilayer wiring printed board according to the first embodiment of the present invention. The first core insulating layer 4 is sandwiched between the first inner layer pattern 3 and the second inner layer pattern 5 which are upper and lower conductor layers, and the first core insulating layer 4 is further connected to the second core insulating layer 4. The multilayer core substrate 12 is configured by being sandwiched between the layer 10 and the third core insulating layer 11. On the upper and lower surfaces of the multi-layer core substrate 12, an upper layer pattern 1 and a lower layer pattern 6 which are wiring patterns made of conductor layers are formed.

多層コア基板12には貫通孔8が形成されており、この貫通孔8の内部表面に金属メッキ9を施されており、この金属メッキ9を介して第1,第2の内層パターン3,5、あるいは第1,第2の内層パターン3,5と、上層パターン1または下層パターン6の少なくとも一方とが電気的に接続されている。ここで、貫通孔8の形成方法については特に制限はなく、機械的研削によって形成すればよい。また、貫通孔8の内部には、樹脂13が埋め込まれおり、この樹脂13の材料については特に制限がなく絶縁性樹脂でも導電性樹脂でもその目的が達成される限り特に制限がない。   A through-hole 8 is formed in the multilayer core substrate 12, and a metal plating 9 is applied to an inner surface of the through-hole 8, and the first and second inner layer patterns 3, 5 are provided via the metal plating 9. Alternatively, the first and second inner layer patterns 3 and 5 are electrically connected to at least one of the upper layer pattern 1 or the lower layer pattern 6. Here, there is no restriction | limiting in particular about the formation method of the through-hole 8, What is necessary is just to form by mechanical grinding. The resin 13 is embedded in the through-hole 8, and the material of the resin 13 is not particularly limited and is not particularly limited as long as the purpose is achieved with either an insulating resin or a conductive resin.

図2は、多層コア基板12に上層パターン1と下層パターン6を形成する前後の時点における構造を示す説明図であり、17は貫通孔8の受けパターンを示す。受けパターン17は、背景技術の欄でも説明したように、貫通孔8の内部表面に金属メッキをする時に必要なパターンである。   FIG. 2 is an explanatory view showing the structure before and after forming the upper layer pattern 1 and the lower layer pattern 6 on the multilayer core substrate 12, and 17 shows a receiving pattern of the through holes 8. As described in the background art section, the receiving pattern 17 is a pattern required when metal plating is performed on the inner surface of the through hole 8.

まず、第1の内層パターン3と第2の内層パターン5が形成された第1のコア絶縁層4の両側から、上層パターン1が形成されていない第2のコア絶縁層10と、下層パターン6が形成されていない第3のコア絶縁層11とを挟みつけて多層コア基板12を作成する。   First, from both sides of the first core insulating layer 4 in which the first inner layer pattern 3 and the second inner layer pattern 5 are formed, the second core insulating layer 10 in which the upper layer pattern 1 is not formed, and the lower layer pattern 6 A multilayer core substrate 12 is formed by sandwiching the third core insulating layer 11 on which no is formed.

次に、多層コア基板12の両面に、上層パターン1または下層パターン6となる導電層を形成してから、多層コア基板12に貫通孔8を形成する。さらに、貫通孔8の内部表面に金属メッキを施してから貫通孔8に樹脂13を充填する。   Next, after forming a conductive layer to be the upper layer pattern 1 or the lower layer pattern 6 on both surfaces of the multilayer core substrate 12, the through holes 8 are formed in the multilayer core substrate 12. Further, the inner surface of the through hole 8 is subjected to metal plating, and then the through hole 8 is filled with the resin 13.

次に、多層コア基板12の両面の導電層にパターンエッチングを施すことにより、上層パターン1または下層パターン6が形成される。   Next, the upper layer pattern 1 or the lower layer pattern 6 is formed by performing pattern etching on the conductive layers on both surfaces of the multilayer core substrate 12.

ここで、貫通孔8の受けパターン17に相当する領域の導電層が、図2(a)に示すように、第2のコア絶縁層11に形成されている場合には、下層パターン6のパターンエッチング時に同時にエッチングされることで除去される。また、貫通孔8内部の金属メッキ9も同時にエッチングされ金属メッキ9の無い除去部14が形成され、下層パターン6と第2の内層パターン5とは電気的に接続されていない。   Here, when the conductive layer in the region corresponding to the receiving pattern 17 of the through-hole 8 is formed on the second core insulating layer 11 as shown in FIG. 2A, the pattern of the lower layer pattern 6 It is removed by being etched at the same time as etching. Further, the metal plating 9 inside the through-hole 8 is also etched at the same time to form a removal portion 14 without the metal plating 9, and the lower layer pattern 6 and the second inner layer pattern 5 are not electrically connected.

そうすることで上層パターン1と第1,第2の内層パターン3,5との電気的接続が可能となる。例えば、厚さ約40μmの導体パターンをエッチングした時、Φ150μmの貫通孔の側面の金属メッキは約20μmの深さまでエッチングされる。そのため、第2,3のコア絶縁層10,11の厚さは50μm以上あることが望ましい。   By doing so, the upper layer pattern 1 and the first and second inner layer patterns 3 and 5 can be electrically connected. For example, when a conductor pattern having a thickness of about 40 μm is etched, the metal plating on the side surface of the through hole having a diameter of 150 μm is etched to a depth of about 20 μm. Therefore, the thickness of the second and third core insulating layers 10 and 11 is desirably 50 μm or more.

なお、電気的に接続されていない部分は、図2(b)に示すように上層のパターン1を形成する配線層と内部の第1,第2の内層パターン3,5を形成する配線層であってもよい。また、図2(c)に示すように、上層,下層パターン1,6と第1,第2の内層パターン3,5との接続がなく、第1,第2の内層パターン3,5を形成する導体層間で接続された多層基板でもよい。   In addition, the part which is not electrically connected is a wiring layer which forms the pattern 1 of an upper layer and the wiring layer which forms the 1st, 2nd inner layer patterns 3 and 5 inside as shown in FIG.2 (b). There may be. Further, as shown in FIG. 2 (c), there is no connection between the upper and lower layer patterns 1 and 6 and the first and second inner layer patterns 3 and 5, and the first and second inner layer patterns 3 and 5 are formed. It may be a multilayer substrate connected between conductive layers.

さらに、図3に示すようにコア絶縁層が2層の場合でもよい。なお、図3(a)はコア絶縁層4,11の2層、図3(b)はコア絶縁層10,4の2層の場合をそれぞれ示すものである。   Further, as shown in FIG. 3, the core insulating layer may be two layers. 3A shows the case of two layers of core insulating layers 4 and 11, and FIG. 3B shows the case of two layers of core insulating layers 10 and 4, respectively.

(第2の実施の形態)
図4は本発明の第2の実施の形態における多層プリント配線基板の構造を示す説明図である。この第2の実施の形態は、図1〜図3に示す第1の実施の形態の多層プリント配線基板に、さらに、ビルトアップ絶縁層2を積層したものである。すなわち、上層パターン1および下層パターン6を挟むように、第2のコア絶縁層10および第3のコア絶縁層11にビルトアップ絶縁層2を積層する。このビルトアップ絶縁層2にレーザ加工等で第2のコア絶縁層10の導体層および第3のコア絶縁層11の導体層までビアホール7を空けて、このビアホール7に金属メッキを施して、上層パターン1および下層パターン6あるいは第1のコア絶縁層4の第1,第2の内層パターン3,5と電気的に接続する。
(Second Embodiment)
FIG. 4 is an explanatory view showing the structure of the multilayer printed wiring board according to the second embodiment of the present invention. In the second embodiment, a built-up insulating layer 2 is further laminated on the multilayer printed wiring board of the first embodiment shown in FIGS. That is, the built-up insulating layer 2 is laminated on the second core insulating layer 10 and the third core insulating layer 11 so as to sandwich the upper layer pattern 1 and the lower layer pattern 6. Via holes 7 are formed in the built-up insulating layer 2 to the conductor layer of the second core insulating layer 10 and the conductor layer of the third core insulating layer 11 by laser processing or the like, and metal plating is applied to the via hole 7 to form an upper layer. The pattern 1 and the lower layer pattern 6 or the first and second inner layer patterns 3 and 5 of the first core insulating layer 4 are electrically connected.

(第3の実施の形態)
図5は本発明の第3の実施の形態における多層プリント配線基板の構造を示す説明図である。図2に示す第1の実施の形態の多層プリント配線基板において、裏面に受けパターン17のない貫通孔8があると、実装時に、はんだがまわってショートする可能性がある。そのため、この第3の実施の形態は、貫通孔8の部分をソルダーレジスト16で覆ったものである。
(Third embodiment)
FIG. 5 is an explanatory view showing the structure of a multilayer printed wiring board according to the third embodiment of the present invention. In the multilayer printed wiring board according to the first embodiment shown in FIG. 2, if there is a through hole 8 without a receiving pattern 17 on the back surface, solder may turn around and cause a short circuit during mounting. Therefore, in the third embodiment, the portion of the through hole 8 is covered with the solder resist 16.

このように構成することにより、はんだが貫通孔8に進入することがなくなるため、ショートすることを防止することができる。   By comprising in this way, since a solder does not approach into the through-hole 8, it can prevent a short circuit.

本発明の多層プリント配線基板は、コア多層基板で貫通孔を用いながらも基板面積を大きくさせることも無く集積化させることができる多層プリント基板の低コスト化技術として有用である。   The multilayer printed wiring board of the present invention is useful as a technique for reducing the cost of a multilayer printed board that can be integrated without increasing the board area while using a through-hole in the core multilayer board.

本発明の第1の実施の形態の多層プリント配線基板の構造を示す斜視図The perspective view which shows the structure of the multilayer printed wiring board of the 1st Embodiment of this invention 第1の実施の形態における、多層コア基板12に上層パターン1と下層パターン6を形成する前後の時点における構造を示す断面図Sectional drawing which shows the structure in the time before and behind forming the upper layer pattern 1 and the lower layer pattern 6 in the multilayer core board | substrate 12 in 1st Embodiment 本発明の第1の実施の形態を2層のプリント配線基板に適用した構造を示す断面図Sectional drawing which shows the structure which applied the 1st Embodiment of this invention to the printed wiring board of two layers 本発明の第2の実施の形態の多層プリント配線基板の構造を示す斜断面図FIG. 3 is an oblique sectional view showing the structure of the multilayer printed wiring board according to the second embodiment of the present invention 本発明の第3の実施の形態の多層プリント配線基板の構造を示す断面図Sectional drawing which shows the structure of the multilayer printed wiring board of the 3rd Embodiment of this invention 従来のコア多層配線基板の断面図Sectional view of a conventional core multilayer wiring board 従来のビルトアップ多層配線基板の断面図Cross-sectional view of a conventional built-up multilayer wiring board

符号の説明Explanation of symbols

1 上層パターン
2 ビルトアップ絶縁層
3 第1の内層パターン
4 第1のコア絶縁層
5 第2の内層パターン
6 下層パターン
7 ビアホール
8 貫通孔
9 金属メッキ
10 第2のコア絶縁層
11 第3のコア絶縁層
12 多層コア基板
13 樹脂
14 除去部
15 ビルトアップ多層基板
16 ソルダーレジスト
DESCRIPTION OF SYMBOLS 1 Upper layer pattern 2 Built-up insulating layer 3 1st inner layer pattern 4 1st core insulating layer 5 2nd inner layer pattern 6 Lower layer pattern 7 Via hole 8 Through-hole 9 Metal plating 10 2nd core insulating layer 11 3rd core Insulating layer 12 Multi-layer core substrate 13 Resin 14 Removal portion 15 Built-up multilayer substrate 16 Solder resist

Claims (8)

2層以上ある多層基板と、前記多層基板を貫通し、内部周辺を金属メッキしてなる貫通孔と、前記貫通孔内部に充填された樹脂とを有し、前記金属メッキによって前記多層基板における上下の配線パターンを電気的に接続する多層プリント配線基板において、前記貫通孔を、前記貫通孔における多層基板の上面、下面の少なくともどちらかに受けパターンのない構成としたことを特徴とする多層プリント配線基板。   A multilayer substrate having two or more layers; a through-hole formed by metal plating the inner periphery of the multilayer substrate; and a resin filled in the through-hole. In the multilayer printed wiring board for electrically connecting the wiring patterns of the multilayer printed wiring board, the through hole is configured to have no receiving pattern on at least one of the upper surface and the lower surface of the multilayer substrate in the through hole. substrate. 受けパターンのない前記貫通孔内部の金属メッキの一部をエッチングしたことを特徴とする請求項1記載の多層プリント配線基板。   2. The multilayer printed wiring board according to claim 1, wherein a part of the metal plating inside the through hole having no receiving pattern is etched. 前記多層基板に、ビルトアップ絶縁層を少なくとも1層積層したことを特徴とする請求項1または2記載の多層プリント配線基板。   The multilayer printed wiring board according to claim 1, wherein at least one built-up insulating layer is laminated on the multilayer board. 受けパターンのない前記貫通孔をレジスト膜で覆ったことを特徴とする請求項1または2記載の多層プリント配線基板。   3. The multilayer printed wiring board according to claim 1, wherein the through-hole having no receiving pattern is covered with a resist film. 前記受けパターンのない貫通孔と前記多層基板の2層を使って配線パターンを引くことによりインダクタ成分を持たせた構造としたことを特徴とする請求項1,2または3記載の多層プリント配線基板。   4. The multilayer printed wiring board according to claim 1, 2, or 3, wherein an inductor component is provided by drawing a wiring pattern using two layers of the through hole without the receiving pattern and the multilayer board. . 前記受けパターンのない貫通孔を用いて、配線パターンと貫通孔のグランドとの干渉を小さくしたことを特徴とする請求項1,2または3記載の多層プリント配線基板。   4. The multilayer printed wiring board according to claim 1, wherein interference between the wiring pattern and the ground of the through hole is reduced by using the through hole without the receiving pattern. 2層以上ある多層基板と、前記多層基板を貫通し、内部周辺を金属メッキしてなる貫通孔と、前記貫通孔内部に充填された樹脂とを有し、前記金属メッキによって前記多層基板における上下の配線パターンを電気的に接続する多層プリント配線基板の製造方法において、
前記多層基板の上下面に形成した導電層をエッチングして配線パターンを形成すると同時に、前記貫通孔の受けパターンをエッチングすることを特徴とする多層プリント配線基板の製造方法。
A multilayer substrate having two or more layers; a through-hole formed by metal plating the inner periphery of the multilayer substrate; and a resin filled in the through-hole. In the manufacturing method of the multilayer printed wiring board for electrically connecting the wiring patterns of
A method of manufacturing a multilayer printed wiring board, comprising: etching a conductive layer formed on the upper and lower surfaces of the multilayer board to form a wiring pattern, and simultaneously etching the receiving pattern of the through hole.
前記貫通孔の受けパターンのエッチングと同時に前記貫通孔の金属メッキの一部をエッチングすることを特徴とする請求項7記載の多層プリント配線基板の製造方法。   8. The method of manufacturing a multilayer printed wiring board according to claim 7, wherein a part of the metal plating of the through hole is etched simultaneously with the etching of the receiving pattern of the through hole.
JP2005067078A 2005-03-10 2005-03-10 Multi-layer printed wiring board and its manufacturing method Pending JP2006253372A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101483876B1 (en) 2013-08-14 2015-01-16 삼성전기주식회사 Inductor element and method of manufacturing the same
CN111836484A (en) * 2020-07-29 2020-10-27 欣强电子(清远)有限公司 Processing method for PCB (printed circuit board) backrest design

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101483876B1 (en) 2013-08-14 2015-01-16 삼성전기주식회사 Inductor element and method of manufacturing the same
CN111836484A (en) * 2020-07-29 2020-10-27 欣强电子(清远)有限公司 Processing method for PCB (printed circuit board) backrest design

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