JPS58131798A - Multilayer circuit board - Google Patents

Multilayer circuit board

Info

Publication number
JPS58131798A
JPS58131798A JP57014176A JP1417682A JPS58131798A JP S58131798 A JPS58131798 A JP S58131798A JP 57014176 A JP57014176 A JP 57014176A JP 1417682 A JP1417682 A JP 1417682A JP S58131798 A JPS58131798 A JP S58131798A
Authority
JP
Japan
Prior art keywords
hole
wiring pattern
wiring board
base material
multilayer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57014176A
Other languages
Japanese (ja)
Inventor
徳光 始
健治 大沢
隆夫 伊藤
正美 石井
告原 信俊
大沢 正行
倉田 警二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP57014176A priority Critical patent/JPS58131798A/en
Publication of JPS58131798A publication Critical patent/JPS58131798A/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は多層配線基板に関し、その目的とするところは
配線パターンの高密度化、製造工程の簡略化、上下配線
パターン間の接続S(以下層間接続部と云う)の信頼性
の向上等を図ることにあり、特に可撓性多層配線基板に
適用して好適ならしめんとするものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multilayer wiring board, and its objectives are to increase the density of wiring patterns, to simplify manufacturing processes, and to improve connections S between upper and lower wiring patterns (hereinafter referred to as interlayer connections). The purpose of this invention is to improve reliability, and it is intended to be particularly suitable for application to flexible multilayer wiring boards.

従来の可撓性多層配線基板は、例えば纂1図A〜C(平
面図)及び纂2図A〜C(断面図)に示すよjKITI
I性絶縁基材(1)の両面に導電箔(例えば鋼11 ’
) +2)及びtatを貼着し、その層間接続部に対応
する位置に透孔(4)を穿設し【後、透孔(4)内に金
属メッキ(側部スルーホールメッキ)(5Jを施して上
下の金属箔(2)及び(3)を電気的に接続し、次いで
両金属箔(2)及び(3)を夫々所定パターンに選択エ
ツチングしてIIIEI及び$12の配線パターン(6
)及び(7)を形成して構成される。しかるに、このよ
5な多層配線基板においては次のような欠点を有してい
た。先ずスルーホールメッキを必要とするので工程が所
麟バッジ式となり、製造工程の連続化が出来ない。透孔
(4)の径が小さくなるとメッキ液の流れが悪くなり安
定なメツ中厚が得られないので透孔径に限界がある(通
常直II O,8閣が限界である)。
Conventional flexible multilayer wiring boards are shown, for example, in Figures 1 A to C (plan view) and Figures 2 A to C (sectional view).
Conductive foil (for example, steel 11'
)+2) and tat are pasted, and a through hole (4) is drilled at a position corresponding to the interlayer connection part. The upper and lower metal foils (2) and (3) are electrically connected by etching, and then both metal foils (2) and (3) are selectively etched into predetermined patterns to form wiring patterns (6) of IIIEI and $12.
) and (7). However, such a multilayer wiring board has the following drawbacks. First, through-hole plating is required, so the process becomes a badge-type process, making it impossible to make the manufacturing process continuous. If the diameter of the through hole (4) becomes small, the flow of the plating solution will be poor and a stable thickness cannot be obtained, so there is a limit to the through hole diameter (normally, the limit is 30 mm, 8 mm).

金属メッキt5Jが゛透孔(4)部分以外の配線パター
ン上にも付着するので多層配線基板の可撓性が損われる
。スルホール形成に時間を資しく略1時間〜2時間)、
しかも温水浴中を通過するので、可撓性絶縁基材とし【
は特に耐湿性を有する限られたものしか使用できない、
また酸中な通過するときに酸を絶縁基材中に吸着し、実
装後に電融作用によリマイグレーション発生する要因と
なり易い。さらK、メッキ液管理が煩雑であり、しかも
大量の廃水を生ずるので大がかりな廃水処理施設が必要
となり、コスト高の原因となるものであった。
Since the metal plating t5J also adheres to the wiring pattern other than the through hole (4) portion, the flexibility of the multilayer wiring board is impaired. (approximately 1 to 2 hours to allow time for throughhole formation),
Moreover, since it passes through a hot water bath, it can be used as a flexible insulating base material [
In particular, only a limited number of moisture-resistant materials can be used.
Furthermore, when passing through acid, the acid is adsorbed into the insulating base material, which tends to cause remigration due to electrofusion after mounting. Furthermore, managing the plating solution is complicated, and since a large amount of wastewater is generated, a large-scale wastewater treatment facility is required, resulting in high costs.

本発明は、上述の欠点を改善した多層配線基板を提供す
るものである。
The present invention provides a multilayer wiring board that has improved the above-mentioned drawbacks.

以下、図面を用い【本発明による多層配線基板の!I!
施例について、その製法と共に詳述する。
The following is a description of the multilayer wiring board according to the present invention using drawings. I!
Examples will be described in detail along with their manufacturing methods.

第3図は本発明の一実施例を示す。但し、同図は層間接
続部分を示し、その一部を断面とした斜視囚である。
FIG. 3 shows an embodiment of the invention. However, this figure shows an interlayer connection part and is a perspective view with a part of it in cross section.

本発明においては、II3図Aに示すように可撓性絶縁
基材とし【一般のポリイミド、ポリスチル等からなる可
撓性絶縁基板aυを用い、この基板1υの一面に導電箔
層例えば鋼箔層からなる第1の配線パターンu3を形成
して後、その第1の配線パターンQ311の層間接a部
(例えば円形状)13に、第3図Bに示すようにパンチ
ング又はドリル等によって例えば円形の透孔Iを穿設す
る。この透孔Iの形成時に、同時に図示せざるも他sに
おいて電気部品のリード挿A孔を穿設するを可とする。
In the present invention, as shown in FIG. After forming the first wiring pattern u3 consisting of the following, for example, a circular shape is formed in the interlayer a portion (for example, circular shape) 13 of the first wiring pattern Q311 by punching or drilling as shown in FIG. 3B. Drill through hole I. At the time of forming the through hole I, it is also possible to simultaneously drill a lead insertion hole A for an electrical component in another hole (not shown).

次に、第3図Cに示すように基板αυの他面に透一孔1
14を含む全面に半硬化状態の接着剤層(151を付し
た導電箔層例えば鋼箔層tteをロールラミネート装置
(例えば1801Z’に熱せられた対の熱ロール関に挿
通せしめる)を用いて積層合体する。この半硬化状態の
接着剤層αSは後に選択エツチングする金属箔層(例え
ば鋼箔層)のエツチング液におかされず、有機溶剤に溶
解し、最終的に電子線、熱等の硬化エネルギーを加える
ことによって3次元硬化し、硬化後はcITIIi性を
呈する等の性質を有する。
Next, as shown in FIG. 3C, a through hole 1 is formed on the other surface of the substrate
A semi-hardened adhesive layer (for example, a conductive foil layer marked with 151, such as a steel foil layer tte) is laminated on the entire surface including 14 using a roll laminating device (for example, inserted through a pair of hot rolls heated to 1801Z'). This semi-hardened adhesive layer αS is not affected by the etching solution of the metal foil layer (for example, steel foil layer) that will be selectively etched later, but is dissolved in an organic solvent, and finally hardened by electron beam, heat, etc. It has properties such as three-dimensional hardening by applying energy and exhibiting cITIIi properties after hardening.

この接着剤層α9は最終的には配線パターンの支持体を
兼る。
This adhesive layer α9 ultimately also serves as a support for the wiring pattern.

次に、第3図りに示すように銅箔鳩四を通電のホトエツ
チング技術を用いて所定パターンに選択エツチングし、
嬉2の配線パターン07)を形成する。
Next, as shown in the third diagram, the copper foil dovetails are selectively etched into a predetermined pattern using a photo-etching technique using electricity.
Form 2 wiring pattern 07).

このとき第2の配線パターyaD側の層間接続部分は中
細に形成し、丁度スルホールQ4)上Kjfi艇するよ
うに形成する。との鋼箔層1eの選択エツチングでは半
硬化状態の接着剤層α9はエツチングされずに残る。
At this time, the interlayer connection portion on the second wiring pattern yaD side is formed to be medium-thin, and is formed so as to fit just above the through hole Q4). In the selective etching of the steel foil layer 1e, the semi-hardened adhesive layer α9 remains without being etched.

次に、第j図Eに示すように8gl及び第2の配線パタ
ーンリ1及び(17)が形成されている両面上に夫夫上
の層間接続部分を除いて可撓性を呈するソルダーレジス
ト層Qlを印刷等によって被着形成するOこのソルダー
レジスト層(IIは耐溶剤性を有し、透孔(14におけ
る接着剤層α9を選択除去するためのマスク部材な康ね
るものであり、ソルダーレジスト層Qsによって覆われ
ない部分に夫々の接続部0及びa・が臨むように形成す
る。
Next, as shown in FIG. This solder resist layer (II has solvent resistance and serves as a mask member for selectively removing the adhesive layer α9 in the through hole (14) is formed by printing or the like. The connecting portions 0 and a. are formed so as to face the portions not covered by the layer Qs.

久に、第3図Fに示すようにフルダーレジスト層四と鋼
箔層からなる層間接続m5(13及びα11スクとし℃
有機溶剤により選択的に接着剤層(15を溶解除去し、
透孔α(転)を開口する。このとき、透孔α尋上Kf、
長されているII2の配線ノ(ターンaDの接続部側の
裏面の接着剤層(15も剥離される。この後、半硬化状
態の接着剤層Q5を電子線、熱等によって硬化させる。
For a long time, as shown in Fig. 3F, an interlayer connection m5 (13 and
The adhesive layer (15) is selectively dissolved and removed using an organic solvent,
Open the through hole α (turn). At this time, Kf above the through hole α fathom,
The adhesive layer (15) on the back side of the connection part side of the long wiring II2 (turn aD) is also peeled off. Thereafter, the semi-hardened adhesive layer Q5 is hardened by electron beam, heat, etc.

次に、第3図GK示すように第2の配線〕(ターン(I
7)lIの接fd郁αυを高圧洗浄ある(1はチー、<
付ポンチにて透孔Q41’内に折り曲げる。接続部us
の先端はillの配線パターンαり備の接続部α3より
突出する方が望ましい。なお、この場合、I114図に
示すように接続11鵠の先端をさらに纂lの配線)(タ
ーンa′JJ儒の接続1t(13に近ずくように曲げて
もよ(・。
Next, as shown in FIG.
7) High pressure cleaning of lI contact fd αυ (1 is Qi, <
Bend it into the through hole Q41' using the attached punch. Connection part us
It is preferable that the tip of the ill be protruded from the connection part α3 of the wiring pattern α of ill. In this case, as shown in Figure I114, the tip of connection 11 may be further bent to approach connection 1t (13) of turn a'JJ.

又、謳5図に示すよ5に、絶縁基材の厚みt、透孔Iの
径り及び接続部側の長さ慮は1)1  、ε≦Lを満足
するように選ぶ。
In addition, as shown in Figure 5, the thickness t of the insulating base material, the diameter of the through hole I, and the length of the connecting portion side are selected so as to satisfy 1) 1, ε≦L.

しかる後、纂3図HK示すように透孔(141にお〜・
【導電材料gIjKよつ【両接続部0及び賭を電気的に
接続する。このとき、IF5図に示すように電気部品r
2υのリードのを挿入して後導電材料■で接続すること
も出来る。導電材′PtCaとしては、半田。
After that, as shown in Figure 3, open the through hole (141~).
[Conductive material gIjK] [Both connection parts 0 and the wire are electrically connected. At this time, as shown in the IF5 diagram, the electrical component r
It is also possible to insert a 2υ lead and then connect with conductive material ■. The conductive material 'PtCa is solder.

鍋ペイント、鋼ペイント、カーボンペイント、カリクム
合金(当初作業装置においてペースト状をなし、その後
経時的に合金化し凝固する性質を有する)等を用い得る
。斯くして、II3図HK示す如く一方の配線パターン
俣ηの接続5QIIが透孔I41内に屈曲され、そのI
II絖部舖と他方の配縁ノ(ターン(I21の接続IB
(13とが導電材料(至)で接続されて成る目的の可撓
性多層配線基板Ωが得られる。
Pot paint, steel paint, carbon paint, calicum alloy (which initially forms a paste in the working equipment and then has the property of alloying and solidifying over time), etc. can be used. In this way, as shown in Figure II3 HK, the connection 5QII of one wiring pattern η is bent into the through hole I41, and the I
II Abe and the other connection (turn (I21 connection IB)
(13) are connected with a conductive material (to) to obtain the desired flexible multilayer wiring board Ω.

かかる多層配線基板(ZIKよれば、層間接続部分にお
いて一方の配線パターンαη肯の接続l5QIIを透孔
α4内に屈曲させ、その先端を他方の配線パターンQ3
備の接続11(13に近接せしめ、両接続郁舖及びαl
を透孔α41におい【半田等の導電材料(至)で接続せ
しめたことKより、導電材料■が′透孔α尋だけで他方
に付着されず、従って従来のメッキ法にて層間接続する
多層配線基板に比して配線基板の可憐性が優れるもので
ある。又、透孔α尋の径L 、 m1llio峠の長さ
C及び絶縁基材の厚さtの関係が1〉tt≦Lの関係か
ら、必要な透孔Q41の径りは絶縁基材の厚さ1以上で
あれば嵐く、これが為透孔α尋の11Lを充分小さくす
ることが可能と′なり、配線パターンの高密度化ができ
る。
Such a multilayer wiring board (according to ZIK, one wiring pattern αη positive connection l5QII is bent into the through hole α4 in the interlayer connection part, and its tip is connected to the other wiring pattern Q3).
Connection 11 (close to 13, both connections Ikuo and αl)
The conductive material ■ is not attached to the other side only through the through hole α41, and therefore the multilayer layer is connected between the layers using the conventional plating method. The prettiness of the wiring board is superior to that of the wiring board. Also, since the relationship between the diameter L of the through hole α fathom, the length C of the m1llio pass, and the thickness t of the insulating base material is 1>tt≦L, the required diameter of the through hole Q41 is the thickness of the insulating base material. If the diameter is 1 or more, it will be difficult to use, and this makes it possible to make the through hole α fathom 11L sufficiently small, and it is possible to increase the density of the wiring pattern.

又、816図に示すように層間接続部における透孔a尋
に電気部品G11lのリード@を挿通し【電気部品の実
俟が同時にできるのでさらに低コスト化が図れる。さら
に、層間接続KIIL?は半田フローをそのまま使用で
きるので、層間接続が蝋時閲K(数秒で町)、LJ&も
容易にでき、また、製造的にはメツキエ橿を有しないの
で側副ロールからロールへの連続化が可能となり、製造
の簡略化及び低コスト化が図れる。又、溶融半田ディツ
プで両接続部Q8及び113の接続を行う場合、透孔I
がガス逃げ用の孔となり、半田の付きが良好となる。又
、メツ中工程を有しないので、絶縁基材としては従来の
ような耐湿性を有するものに限らず、自由に選択でき、
且つマイグレーションの発生もない。
In addition, as shown in Figure 816, the lead of the electrical component G11l is inserted into the through hole a-fat in the interlayer connection part. Furthermore, interlayer connection KIIL? Since the solder flow can be used as is, interlayer connections can easily be made by soldering (in a few seconds) and LJ&, and in terms of manufacturing, since it does not have a metal fitting, continuity from side roll to roll is possible. This makes it possible to simplify manufacturing and reduce costs. Also, when connecting both connecting parts Q8 and 113 with molten solder dip, the through hole I
This becomes a hole for gas escape, which improves solder adhesion. In addition, since there is no intermediate process, the insulating base material can be freely selected, not only those with moisture resistance as in the past.
Moreover, no migration occurs.

纂7図は本発明の他の実施例を示す。本例は配線パター
ンを支持する絶縁基材として半硬化状態の接着剤層を用
いた場合である。先ず、纂7図AK示すように半硬化状
態の接着剤層a9の一主面に導電箔層例えば鋼箔層から
なるll[の配線パターンaりを形成する。これは、例
えば半硬化接着剤付きの鋼箔層をバター二/ダして得ら
れる。第1の配線パターンa3の層間接続部0は、この
場合例えば長方形の環状に形成する。この菖1の配線パ
ターンaりを有した接着剤1(15の他面に謳7図Bに
示すようにさらに半硬化状態の接着剤層α9を付した導
電箔層例えば鋼箔層ueをロールラミネート装置を用い
て積層合体する。
Figure 7 shows another embodiment of the invention. In this example, a semi-cured adhesive layer is used as the insulating base material supporting the wiring pattern. First, as shown in Figure 7AK, a wiring pattern a made of a conductive foil layer, such as a steel foil layer, is formed on one main surface of the semi-cured adhesive layer a9. This can be obtained, for example, by butter-coating a steel foil layer with a semi-cured adhesive. In this case, the interlayer connection portion 0 of the first wiring pattern a3 is formed, for example, in a rectangular ring shape. Roll a conductive foil layer, for example, a steel foil layer ue, with a semi-hardened adhesive layer α9 on the other side of the adhesive 1 (15) having the wiring pattern a of this irises 1. Laminate and combine using a laminating device.

久に、總7図eH示すよ5に通常のホトエツチング技術
を用いて鋼箔層四を選択エツチングして菖2の配線パタ
ーンαηを形成する。このとき第2の配線パターンαη
儒の中細の接続部賭は、纂l配線パターンu3儒の環状
の接続su3の位置に対応し、且つその外形寸法を接続
5(131の内寸法以下Kl’C形成する。
After a while, as shown in Figure 7eH, the steel foil layer 4 is selectively etched using a conventional photoetching technique to form the wiring pattern αη of the irises 2. At this time, the second wiring pattern αη
The medium-thin connecting portion of the wire corresponds to the position of the ring-shaped connection su3 of the coiled wiring pattern U3, and its outer dimension is equal to or smaller than the inner dimension of the connection 5 (131) Kl'C.

次に、纂7図1)K示すよ5に夫々配線パターンα2及
びQDが形成された画表向上に夫々接続部Q3及びu8
を除くようにしてンルダーレジスト層α湯を印刷等によ
り被着形成する。このツルf−レジスト層Qlは土偶と
同様に接着剤層α9を選択除去するためのマスク部材を
兼ねる。しかる後、謳7図g<示すようにノルダーレジ
スト層a嚇及び鋼箔による両接続部(13、d碍をマス
クとして、環状の接続部αJに囲まれた1肯の接着剤層
(19を選択的に有機溶剤にて溶解剥離し透孔a4を形
成する。これKよって籐2の配線パターンα′r)ll
の接続部−は丁度透孔α番上に位置するよう、、になる
。接着剤層α9の選択エツチング完了後、接着剤層a5
を硬化して絶縁支持体(至)とする。
Next, as shown in Fig. 7 (1) K, connecting portions Q3 and u8 are formed on the surface of the screen on which the wiring patterns α2 and QD are formed, respectively.
A resist resist layer α is deposited by printing or the like so as to remove the remaining resist layer α. This crane f-resist layer Ql also serves as a mask member for selectively removing the adhesive layer α9, similar to the clay figure. After that, as shown in Figure 7, using the solder resist layer a and the steel foil connections (13 and d) as masks, apply the adhesive layer (19) surrounded by the annular connection αJ. is selectively dissolved and peeled off using an organic solvent to form a through hole a4.Thus, the wiring pattern α'r)ll of the rattan 2 is formed.
The connecting part - is located exactly above the through hole α. After selective etching of adhesive layer α9 is completed, adhesive layer a5
is cured to form an insulating support.

次に、II7図Fに示すように第2の配線パターンaD
偶の接続部0秒(裏面の接着剤層α9は剥離されている
)を高圧洗浄あるいはテーバ付ポンチにて透孔α−1に
屈曲させ、その先端な菖1の配線パターン偶の接続部Q
3に近接させて後、第7図qに示すように半田等の導電
材料(2)にて両接続部αJ及び餞を接続し目的の可撓
性多層配線基板(至)を得る。
Next, as shown in FIG. II7F, a second wiring pattern aD is formed.
Bend the double connection part 0 seconds (the adhesive layer α9 on the back side has been peeled off) into the through hole α-1 using high-pressure cleaning or a punch with a taper, and make the wiring pattern of the irises 1 at the tip of the joint part Q.
3, as shown in FIG. 7Q, both connecting portions αJ and the solder are connected with a conductive material (2) such as solder to obtain the desired flexible multilayer wiring board.

この可撓性多層配線基板(至)は、1113図の場合と
同様の作用効果を奏すると共に、さらに絶縁基材として
kIPiI化状態の接状態層Q9を有用しているので、
より製造が容易となり、また透孔α尋の形成が化学エツ
チングでなされるのでより配線パターンの微細化が可能
となる。なお、lE7#ABの工程において、第8#A
K示すようKM接着剤αシ間に印刷その他等による任意
の厚さの絶縁層(至)を入れることもできる。
This flexible multilayer wiring board (to) has the same effect as the case shown in FIG.
Manufacturing is easier, and since the through-holes are formed by chemical etching, the wiring pattern can be made finer. In addition, in the process of lE7#AB, the 8th #A
As shown in K, an insulating layer (up to) of arbitrary thickness can be inserted between the KM adhesive α by printing or the like.

菖2配線パターンaη側の接続部α$の形状は、纂9a
QA及びBK示すように透孔α4に一方より延長する巾
細り接続部α優を形成して之を透孔α舎内に屈曲して成
る基本型の他に、例えば第10図〜第12図に示すよう
に透孔(141に対して両側より延長する対の接続11
5QIを形成し、第13図に示すように夫夫を透孔α尋
内に屈曲せしめて導電材料(7)で接続する形状、ある
いは3114図人及びBに示すように透孔Q4上におい
て接続11QIを4分割し夫々な透孔Q4内に屈曲させ
るようKした形状等、種々考えられる。
The shape of the connection part α$ on the side of the iris 2 wiring pattern aη is 纂9a
In addition to the basic model in which a narrow connecting part α extending from one side is formed in the through hole α4 as shown in QA and BK, and this is bent into the through hole α, for example, in FIGS. 10 to 12. As shown in FIG.
5QI is formed, and the shape is bent into the through hole α as shown in Fig. 13 and connected with the conductive material (7), or connected on the through hole Q4 as shown in Fig. Various shapes are conceivable, such as a shape in which 11QI is divided into four parts and bent into each through hole Q4.

l115図は本発明のさらに他の実施例を示すものであ
る。これは4層の配、II パターン61J、(ロ)、
03及び図を半硬化状態の接着剤αSを介して積層合体
した多層配線基板であり、各パターンの接続部<32m
)、 (33a)、 (34m)を透孔(141内に屈
曲せしめて接続its (31a)と共通に接続するこ
とができる。
Figure 1115 shows still another embodiment of the present invention. This is a 4-layer arrangement, II pattern 61J, (b),
03 and the figure are laminated together via semi-cured adhesive αS, and the connecting portion of each pattern is <32 m.
), (33a), and (34m) can be bent into the through hole (141) and connected in common with its connection (31a).

尚、土偶では可撓性多層配線基板に適用したが、硬質基
板による多層配線基板にも適用することが可能である。
Although the clay figure was applied to a flexible multilayer wiring board, it can also be applied to a multilayer wiring board using a hard substrate.

上述せる如く、本発明によれば多層配線基板において、
その配爛パター7の高書度化、製造工程の簡略化1層間
接続部の信頼性の向上等を図ることができるものであり
、特に可撓性多層配線基板に適用して好適である。
As mentioned above, according to the present invention, in the multilayer wiring board,
It is possible to improve the writing quality of the spread pattern 7, simplify the manufacturing process, and improve the reliability of the connection between one layer, and is particularly suitable for application to a flexible multilayer wiring board.

【図面の簡単な説明】[Brief explanation of the drawing]

111111A−Cは従来の多層配線基板の例を示す製
造工1111[の平面図、縞2図A〜Cは夫々第1図A
−CF)l −Ill上の断面図、@3図は本発明によ
る多層配線基板の一実施例を示す製造工程順の一部断面
とした斜視図、114図〜第6図は夫々層間接続部の説
明に供する要部の断面図、第7図は本発明の多層配線基
板の他の実施例を示す製造工程順の一部断面とした斜視
図、纂8図は本発明の多層配線基板の他の実施例を示す
途中工程の断面図、lls図人及びBは本発明に適用さ
れる接続部の形状の基本臘を示す平面図及び屈曲後の断
面図、纂lO図〜菖121iは夫々接続部の形状の変形
例を示す平面図、篇13図はその屈曲後の断面図、第1
4図人及びBはW!絖部の形状のさらに他の変形例を示
す平面図及び屈曲状態を示す斜視図、第15図は本発明
の多層配線基板のさらに他の実施例を示す一部断面とし
た斜視図である。 αυは絶縁基板、α3Qηは配縁パターン、α3Qs&
末接続部、α9は半硬化状態の接着剤層、■は導電材料
である。 第81ス1     第12図 、、、 l Oト:      第13図第15図 第1頁の続き 、か発 明 者 倉田警二 東京都大田区東糀谷5丁目21番 15号ソニー株式会社羽田工場内
111111A-C is a plan view of a manufacturing process 1111 [showing an example of a conventional multilayer wiring board, and stripes A to C are respectively shown in FIG. 1A.
-CF)l -Ill is a cross-sectional view, Figure @3 is a partially cross-sectional perspective view showing an embodiment of the multilayer wiring board according to the present invention in the order of manufacturing steps, and Figures 114 to 6 are interlayer connections, respectively. FIG. 7 is a partially sectional perspective view showing another embodiment of the multilayer wiring board of the present invention in the order of manufacturing steps, and FIG. 8 is a partial cross-sectional view of the multilayer wiring board of the present invention. A cross-sectional view of an intermediate process showing another embodiment, Figures 121i and 121i are a plan view and a cross-sectional view after bending, respectively, showing the basic shape of the connection part applied to the present invention. A plan view showing a modified example of the shape of the connection part, Figure 13 is a sectional view after bending, and Figure 1
Figure 4 person and B are W! FIG. 15 is a plan view showing still another modification of the shape of the groove and a perspective view showing a bent state. FIG. 15 is a partially sectional perspective view showing still another embodiment of the multilayer wiring board of the present invention. αυ is an insulating substrate, α3Qη is a wiring pattern, α3Qs&
In the terminal connection part, α9 is a semi-cured adhesive layer, and ■ is a conductive material. 81st 1 Figure 12...l Ot: Figure 13 Figure 15 Continuation of page 1 Inventor Keiji Kurata Inside the Sony Corporation Haneda Factory, 5-21-15 Higashikojiya, Ota-ku, Tokyo

Claims (1)

【特許請求の範囲】[Claims] 絶縁基材と、核絶縁基材の所定の位置に設けられた透孔
と、前記絶縁基材の第1のilK前記透孔に隣接するご
とく設けられた第1の導電箔層と、前記絶縁基材の第1
の面の反対面に設けられ前記透孔に屈曲された部分を有
する第2の導電箔層と、前記第1及び$112の導電箔
層な前記透孔において接続する導電材料より成る多層配
線基板。
an insulating base material, a through hole provided at a predetermined position of the core insulating base material, a first conductive foil layer provided adjacent to the first ilK of the through hole of the insulating base material, and the insulating base material. First base material
a second conductive foil layer provided on the opposite side of the surface and having a bent portion in the through hole; and a multilayer wiring board made of a conductive material that connects the first and $112 conductive foil layers at the through hole. .
JP57014176A 1982-01-29 1982-01-29 Multilayer circuit board Pending JPS58131798A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57014176A JPS58131798A (en) 1982-01-29 1982-01-29 Multilayer circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57014176A JPS58131798A (en) 1982-01-29 1982-01-29 Multilayer circuit board

Publications (1)

Publication Number Publication Date
JPS58131798A true JPS58131798A (en) 1983-08-05

Family

ID=11853829

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57014176A Pending JPS58131798A (en) 1982-01-29 1982-01-29 Multilayer circuit board

Country Status (1)

Country Link
JP (1) JPS58131798A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60130883A (en) * 1983-12-19 1985-07-12 中央銘板工業株式会社 Multilayer printed circuit board
JPS60109362U (en) * 1983-12-28 1985-07-25 アルプス電気株式会社 Earth structure of multilayer printed circuit board
KR100774894B1 (en) * 1999-11-11 2007-11-08 신꼬오덴기 고교 가부시키가이샤 Semiconductor device
JP2013157566A (en) * 2012-01-31 2013-08-15 Sumitomo Electric Printed Circuit Inc Printed wiring board and method of manufacturing the printed wiring board

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50139364A (en) * 1974-04-24 1975-11-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50139364A (en) * 1974-04-24 1975-11-07

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60130883A (en) * 1983-12-19 1985-07-12 中央銘板工業株式会社 Multilayer printed circuit board
JPH0365677B2 (en) * 1983-12-19 1991-10-14
JPS60109362U (en) * 1983-12-28 1985-07-25 アルプス電気株式会社 Earth structure of multilayer printed circuit board
JPH0223024Y2 (en) * 1983-12-28 1990-06-21
KR100774894B1 (en) * 1999-11-11 2007-11-08 신꼬오덴기 고교 가부시키가이샤 Semiconductor device
JP2013157566A (en) * 2012-01-31 2013-08-15 Sumitomo Electric Printed Circuit Inc Printed wiring board and method of manufacturing the printed wiring board

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