JPS60128697A - 半導体素子搭載用多層配線基板 - Google Patents

半導体素子搭載用多層配線基板

Info

Publication number
JPS60128697A
JPS60128697A JP58237602A JP23760283A JPS60128697A JP S60128697 A JPS60128697 A JP S60128697A JP 58237602 A JP58237602 A JP 58237602A JP 23760283 A JP23760283 A JP 23760283A JP S60128697 A JPS60128697 A JP S60128697A
Authority
JP
Japan
Prior art keywords
semiconductor element
diamond
alloy
layer
multilayer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58237602A
Other languages
English (en)
Japanese (ja)
Other versions
JPH043120B2 (enExample
Inventor
小笠　伸夫
陽 土居
昭 大塚
直治 藤森
剛 吉岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP58237602A priority Critical patent/JPS60128697A/ja
Publication of JPS60128697A publication Critical patent/JPS60128697A/ja
Publication of JPH043120B2 publication Critical patent/JPH043120B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP58237602A 1983-12-15 1983-12-15 半導体素子搭載用多層配線基板 Granted JPS60128697A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58237602A JPS60128697A (ja) 1983-12-15 1983-12-15 半導体素子搭載用多層配線基板

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58237602A JPS60128697A (ja) 1983-12-15 1983-12-15 半導体素子搭載用多層配線基板

Publications (2)

Publication Number Publication Date
JPS60128697A true JPS60128697A (ja) 1985-07-09
JPH043120B2 JPH043120B2 (enExample) 1992-01-22

Family

ID=17017750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58237602A Granted JPS60128697A (ja) 1983-12-15 1983-12-15 半導体素子搭載用多層配線基板

Country Status (1)

Country Link
JP (1) JPS60128697A (enExample)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01181550A (ja) * 1988-01-12 1989-07-19 Toppan Printing Co Ltd 多層電子回路
JPH0223639A (ja) * 1988-07-13 1990-01-25 Fujitsu Ltd 電子装置
US5682063A (en) * 1993-05-28 1997-10-28 Sumitomo Electric Industries, Ltd. Substrate for semiconductor device
WO2004107438A1 (ja) * 2003-05-29 2004-12-09 Sumitomo Electric Industries, Ltd. サブマウントおよびそれを用いた半導体装置
JP2008210847A (ja) * 2007-02-23 2008-09-11 Jtekt Corp 回路構造

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01181550A (ja) * 1988-01-12 1989-07-19 Toppan Printing Co Ltd 多層電子回路
JPH0223639A (ja) * 1988-07-13 1990-01-25 Fujitsu Ltd 電子装置
US5682063A (en) * 1993-05-28 1997-10-28 Sumitomo Electric Industries, Ltd. Substrate for semiconductor device
WO2004107438A1 (ja) * 2003-05-29 2004-12-09 Sumitomo Electric Industries, Ltd. サブマウントおよびそれを用いた半導体装置
JP2008210847A (ja) * 2007-02-23 2008-09-11 Jtekt Corp 回路構造

Also Published As

Publication number Publication date
JPH043120B2 (enExample) 1992-01-22

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