JPS60124840A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法Info
- Publication number
- JPS60124840A JPS60124840A JP58233125A JP23312583A JPS60124840A JP S60124840 A JPS60124840 A JP S60124840A JP 58233125 A JP58233125 A JP 58233125A JP 23312583 A JP23312583 A JP 23312583A JP S60124840 A JPS60124840 A JP S60124840A
- Authority
- JP
- Japan
- Prior art keywords
- interface
- groove
- polysilicon
- substrate
- shaped groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H10W10/00—
-
- H10W10/01—
Landscapes
- Element Separation (AREA)
- Weting (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58233125A JPS60124840A (ja) | 1983-12-09 | 1983-12-09 | 半導体装置の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58233125A JPS60124840A (ja) | 1983-12-09 | 1983-12-09 | 半導体装置の製造方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60124840A true JPS60124840A (ja) | 1985-07-03 |
| JPH0340948B2 JPH0340948B2 (index.php) | 1991-06-20 |
Family
ID=16950142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58233125A Granted JPS60124840A (ja) | 1983-12-09 | 1983-12-09 | 半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60124840A (index.php) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5583065A (en) * | 1994-11-23 | 1996-12-10 | Sony Corporation | Method of making a MOS semiconductor device |
| US6277706B1 (en) | 1997-06-13 | 2001-08-21 | Nec Corporation | Method of manufacturing isolation trenches using silicon nitride liner |
| WO2001061747A3 (en) * | 2000-02-15 | 2002-01-24 | Koninkl Philips Electronics Nv | Method for eliminating stress induced dislocation in cmos devices |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5882532A (ja) * | 1981-11-11 | 1983-05-18 | Toshiba Corp | 素子分離方法 |
| JPS58168259A (ja) * | 1982-03-30 | 1983-10-04 | Nippon Telegr & Teleph Corp <Ntt> | 半導体集積回路装置の製造方法 |
-
1983
- 1983-12-09 JP JP58233125A patent/JPS60124840A/ja active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5882532A (ja) * | 1981-11-11 | 1983-05-18 | Toshiba Corp | 素子分離方法 |
| JPS58168259A (ja) * | 1982-03-30 | 1983-10-04 | Nippon Telegr & Teleph Corp <Ntt> | 半導体集積回路装置の製造方法 |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5583065A (en) * | 1994-11-23 | 1996-12-10 | Sony Corporation | Method of making a MOS semiconductor device |
| US6277706B1 (en) | 1997-06-13 | 2001-08-21 | Nec Corporation | Method of manufacturing isolation trenches using silicon nitride liner |
| WO2001061747A3 (en) * | 2000-02-15 | 2002-01-24 | Koninkl Philips Electronics Nv | Method for eliminating stress induced dislocation in cmos devices |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0340948B2 (index.php) | 1991-06-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100258653B1 (ko) | 집적 회로의 실리콘층 내에 매립된 분리 부재 및 그의 형성 방법 | |
| JP3079011B2 (ja) | 分離部材を形成する方法 | |
| US6727159B2 (en) | Method of forming a shallow trench isolation in a semiconductor substrate | |
| JP2002289683A (ja) | トレンチ分離構造の形成方法および半導体装置 | |
| JPH01117043A (ja) | 基板中にエピタキシヤル・シリコン成長層を形成する方法 | |
| JP2001160589A (ja) | トレンチ素子分離構造とこれを有する半導体素子及びトレンチ素子分離方法 | |
| US6475865B1 (en) | Method of fabricating semiconductor device | |
| EP0224039B1 (en) | Process for making a planar trench semiconductor structure | |
| JPH11204645A (ja) | 半導体素子の層間絶縁膜及びその製造方法 | |
| US6649488B2 (en) | Method of shallow trench isolation | |
| JP2000332099A (ja) | 半導体装置およびその製造方法 | |
| JPH11330226A (ja) | 浅いトレンチアイソレ―ション方法 | |
| JP3003250B2 (ja) | 半導体装置の製造方法 | |
| JPS60124840A (ja) | 半導体装置の製造方法 | |
| US6503815B1 (en) | Method for reducing stress and encroachment of sidewall oxide layer of shallow trench isolation | |
| US6838356B2 (en) | Method of forming a trench isolation | |
| JPH02257640A (ja) | 半導体素子の製造方法 | |
| US6849493B2 (en) | Methods of forming polished material and methods of forming isolation regions | |
| US6316330B1 (en) | Method of fabricating a shallow trench isolation semiconductor device | |
| JP2000183150A (ja) | 半導体装置の製造方法 | |
| US6500729B1 (en) | Method for reducing dishing related issues during the formation of shallow trench isolation structures | |
| KR950009888B1 (ko) | 반도체장치의 제조방법 | |
| JPH11274287A (ja) | 素子分離領域の形成方法 | |
| JP3367484B2 (ja) | 半導体装置及びその製造方法 | |
| US20030194870A1 (en) | Method for forming sidewall oxide layer of shallow trench isolation with reduced stress and encroachment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |