JPS60124840A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS60124840A
JPS60124840A JP23312583A JP23312583A JPS60124840A JP S60124840 A JPS60124840 A JP S60124840A JP 23312583 A JP23312583 A JP 23312583A JP 23312583 A JP23312583 A JP 23312583A JP S60124840 A JPS60124840 A JP S60124840A
Authority
JP
Japan
Prior art keywords
interface
groove
polysilicon
substrate
shaped groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23312583A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0340948B2 (enExample
Inventor
Kenichi Suzuki
謙一 鈴木
Fumio Yanagihara
柳原　文雄
Makoto Serigano
芹ケ野　誠
Nobuhiro Sano
佐野　伸弘
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23312583A priority Critical patent/JPS60124840A/ja
Publication of JPS60124840A publication Critical patent/JPS60124840A/ja
Publication of JPH0340948B2 publication Critical patent/JPH0340948B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Weting (AREA)
JP23312583A 1983-12-09 1983-12-09 半導体装置の製造方法 Granted JPS60124840A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23312583A JPS60124840A (ja) 1983-12-09 1983-12-09 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23312583A JPS60124840A (ja) 1983-12-09 1983-12-09 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS60124840A true JPS60124840A (ja) 1985-07-03
JPH0340948B2 JPH0340948B2 (enExample) 1991-06-20

Family

ID=16950142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23312583A Granted JPS60124840A (ja) 1983-12-09 1983-12-09 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS60124840A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5583065A (en) * 1994-11-23 1996-12-10 Sony Corporation Method of making a MOS semiconductor device
US6277706B1 (en) 1997-06-13 2001-08-21 Nec Corporation Method of manufacturing isolation trenches using silicon nitride liner
WO2001061747A3 (en) * 2000-02-15 2002-01-24 Koninkl Philips Electronics Nv Method for eliminating stress induced dislocation in cmos devices

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5882532A (ja) * 1981-11-11 1983-05-18 Toshiba Corp 素子分離方法
JPS58168259A (ja) * 1982-03-30 1983-10-04 Nippon Telegr & Teleph Corp <Ntt> 半導体集積回路装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5882532A (ja) * 1981-11-11 1983-05-18 Toshiba Corp 素子分離方法
JPS58168259A (ja) * 1982-03-30 1983-10-04 Nippon Telegr & Teleph Corp <Ntt> 半導体集積回路装置の製造方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5583065A (en) * 1994-11-23 1996-12-10 Sony Corporation Method of making a MOS semiconductor device
US6277706B1 (en) 1997-06-13 2001-08-21 Nec Corporation Method of manufacturing isolation trenches using silicon nitride liner
WO2001061747A3 (en) * 2000-02-15 2002-01-24 Koninkl Philips Electronics Nv Method for eliminating stress induced dislocation in cmos devices

Also Published As

Publication number Publication date
JPH0340948B2 (enExample) 1991-06-20

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees