JPS60110151A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the variation in the resistance value of a high resistance polycrystalline silicon layer as a resistor by removing at least the portion on the high resistance polycrystalline silicon layer of a silicon nitride film as a protecting film or an interlayer insulating film. CONSTITUTION:A P type silicon substrate 1, N<+> type source, drain regions 2, 2', a channel stopper region 3, a field oxide silicon film 4, gate electrodes 5, 5' form an N channel MOS transistors A, B. A flip-flop formed by using polycrystalline silicon layer 8 as a resistor form 1 bit. An interlayer insulating film 10 and aluminum wirings 11 are coated, and a PSG film 12 and a silicon nitride film 13 are used as protective films. However, the silicon nitride film of the portion of the polycrystalline silicon layer 8 is removed. Thus, the layer 8 as a resistor is not affected by the adverse influence of the film 13.

Description

Detailed description of the invention [Technical field to which the invention pertains] The present invention relates to a semiconductor integrated circuit, particularly a semiconductor integrated circuit having a resistive polycrystalline silicon layer as a resistor and a C silicon nitride film as a protective film or interlayer insulating film. Regarding circuits.

[Prior art]

The surface of a semiconductor integrated circuit is covered with a protective film. This is to prevent contaminants from entering the semiconductor integrated circuit to prevent deterioration of element characteristics, and to prevent moisture from entering the air to prevent all-pole wiring from breaking due to corrosion. Phosphorsilicate glass (hereinafter referred to as PSG) has been widely used as a material for the protective film.

PEG contains a large amount of phosphorus (P), which fixes contaminants within the film and prevents them from diffusing into the interior of the confectionery. However, depending on the concentration of phosphorus, there are problems in that it has strong water absorption and is prone to cracking, making it incomplete as a surface protective film.

On the other hand, silicon nitride films formed by the plasma vapor deposition method, which has started to be used in recent years, can be produced at low temperatures because plasma is generated in reduced pressure gas and the reaction proceeds. It is attracting attention as a stronger protective film than PSG because it is a substance that is difficult for pollutants to diffuse. However, silicon nitride films also have problems, such as high internal stress and large amounts of ammonia and hydrogen in the film, which can become gases and diffuse into the semiconductor integrated circuit, causing electrical problems. Characteristics may change.

The inventors have recently discovered that the resistance value of a high resistance polycrystalline silicon layer incorporated into a semiconductor integrated circuit as a resistor changes significantly when a silicon nitride film is deposited by vapor phase growth. The resistance value of high-resistance polycrystalline silicon in a semiconductor integrated circuit that is not fully coated with a silicone film is lOΩ.
In contrast, that of the semiconductor integrated circuit coated with the C1 silicon nitride film was lOΩ. It is not necessarily clear whether the mechanism of the resistance value fluctuation is due to internal stress caused by depositing the silicon nitride film, or whether it is due to the gas contained in the t;L film. However, when the absolute value of the resistance is required at the 10Ω level, this large variation is beyond the permissible range.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit which can use a silicon nitride film as a protective film or an interlayer insulating film without causing a change in the resistance value of the resistive polycrystalline silicon layer as a resistor. It is about providing.

[Structure of the invention]

The semiconductor integrated circuit of the present invention includes a semiconductor ff[ having a high resistance polycrystalline silicon layer at °C as a resistor and a silicon nitride film at °C as a protective film or an interlayer insulating film.
It is constructed by removing at least a portion of the silica silicon film above the red resistive polycrystalline silicon layer.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

1 and 2 are cross-sectional views showing essential parts of an embodiment of the present invention, respectively, in two directions of a static memory cell, that is, FIG. The figure is the first
C represents a cross-sectional view taken along the line xx' in the figure.

In this embodiment, a high resistance polycrystalline silicon layer 8 as a resistor is used.
In a semiconductor integrated circuit having a silica silicon film 13 as a protective film, the portion of the silicon nitride film 13 above the high-resistance polycrystalline silicon layer 8 is removed.

Here, 1 is the P-type silicon substrate, 2 and 2' are the north drain regions of N+ya 1, and 3 is the channel stock/"6JJ
L4 is field silicon DQ ms s + s'
is a 5ios transistor A with a gate voltage of N channel
, Ll is formed at °C.

In this embodiment, a solid flop circuit formed using a polycrystalline silicon layer 8 as a resistor constitutes one bit. The resistance value of the polycrystalline silicon layer 8 determines the standby current of the memory chip.

In a 64-bit static memory, IW is typically set to about 7410''Ω.
Phosphorus is ion-implanted into the material, and C is determined by the phosphorus installation. Phosphorus concentrations on the order of 10''/ctrt'' are commonly used. Of course, depending on the resistance value, phosphorus may not be doped, or other atoms may be doped.

Portions 7 and 7' at both ends of the polycrystalline silicon layer 8 used as a resistor are doped with phosphorus or arsenic at a high concentration.
C is used as a conductive layer. Polycrystalline silicon layer 7 is yos) Source/drain region 2 of transistor A
The polycrystalline 7 recon #7' is connected to the power supply voltage V
cc K connected. The above-mentioned phosphorus or arsenic step is carried out using a silicon oxide film as a mask, but the impurities in the polycrystalline silicon layer 7 are the impurities in the source/drain region 2 and the gate electrode 5' which is the polycrystalline silicon layer. It is doped by diffusion, and the reason why the edge of the -edge length crystalline silicon layer 7' penetrates into the interior K of the silicon oxide film 9 serving as a mask for impurity doping is due to the diffusion. Polycrystalline silicon layers 7.7' and 81-1M0B deposited to form this resistor.) Gate electrodes 5 and 5' of transistors A and B are made of polycrystalline silicon as the first layer. °C is the second layer. Insulation between these two layers is provided by an interlayer insulating film 6. Further, an interlayer insulating film 10 made of Kt'1PSG is deposited on the second polycrystalline silicon layers 7.7' and 8, and an aluminum wiring layer 11 is deposited thereon.

Two protective films are used: a CP8G film 12 and a silicon nitride film 13 layered on top of the CP8G film 13 by plasma vapor deposition. The silicon nitride film has been removed.

Therefore, the polycrystalline silicon layer 8 as a resistor is not affected by the internal stress of the silicon nitride film 13, nor is it affected by the ammonia gas or hydrogen gas contained in the nitride film. The temperature of the semiconductor substrate shown in FIGS. 1 and 2 was raised to 500°C, and the characteristics were then measured, and the resistance value was 10Ω, as expected, indicating that there was no sudden effect of the silicon nitride film 13. confirmed.

The removed portion of the silicon nitride film 13 can be captured only by the PEG film 12, but most of the other area will be covered by the silicon nitride film 13, and the effect will be over the entire surface. It is not much inferior to the case where it is covered with a silicon nitride film.

Note that if a second metal wiring layer is further deposited on top of FIGS. 1 and 2, the silicon nitride film 13 will be used as an interlayer insulating film, but in that case, the same procedure as above will be applied. Effects can be obtained.

Further, although the above embodiment uses an N-channel MO8 transistor, the present invention is not limited thereto.

〔Effect of the invention〕

As explained above, according to the present invention, since there is no capping silicon film on the local resistance polycrystalline silicon layer, the resistance value is as low as 14%. Moreover, since the silicon nitride film is deposited on the area of large ilV other than the resistive polycrystalline silicon layer, it has a sufficient effect as a protective pattern or a two-layer film between the layers. A semiconductor integrated circuit is obtained in which it is possible to perform the following steps.

[Brief explanation of drawings]

1 and 2 are sectional views showing the main parts of the present invention, respectively.
It is a sectional view in the direction along -Xt. l...P-type silicon substrate, 2.2'...
・N-type source/drain region, 3...Channel horn (region, 4...Field silicon oxide film, 5.5'...°°gegu'@pole, 6 ...
...Interlayer insulating film, 7.7'...Polycrystalline silicon layer (as a conductive layer), 8...Resistance polycrystalline silicon layer, 9...°°゛Silicon oxide Membrane, 10...
... Interlayer insulating film, 11 ... Aluminum wiring layer, 12°° ... ° Phosphorus silicate glass film, 13.
...Silicon nitride film, A, H...N channel uMOs transistor. 2 territories

Claims (1)

[Claims] In a semiconductor integrated circuit having a resistive polycrystalline silicon layer as a resistor and a silicon nitride film as a protective film or an interlayer insulating film, at least a portion of the silicon nitride film above the high-resistance polycrystalline silicon layer is removed. A semiconductor integrated circuit characterized by: