JPS60107868A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS60107868A
JPS60107868A JP58214156A JP21415683A JPS60107868A JP S60107868 A JPS60107868 A JP S60107868A JP 58214156 A JP58214156 A JP 58214156A JP 21415683 A JP21415683 A JP 21415683A JP S60107868 A JPS60107868 A JP S60107868A
Authority
JP
Japan
Prior art keywords
bonding pad
gate
power supply
drain
divided
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58214156A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0547983B2 (enrdf_load_stackoverflow
Inventor
Jun Fukaya
深谷　潤
Yutaka Hirano
裕 平野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58214156A priority Critical patent/JPS60107868A/ja
Publication of JPS60107868A publication Critical patent/JPS60107868A/ja
Publication of JPH0547983B2 publication Critical patent/JPH0547983B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Junction Field-Effect Transistors (AREA)
JP58214156A 1983-11-16 1983-11-16 半導体装置 Granted JPS60107868A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58214156A JPS60107868A (ja) 1983-11-16 1983-11-16 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58214156A JPS60107868A (ja) 1983-11-16 1983-11-16 半導体装置

Publications (2)

Publication Number Publication Date
JPS60107868A true JPS60107868A (ja) 1985-06-13
JPH0547983B2 JPH0547983B2 (enrdf_load_stackoverflow) 1993-07-20

Family

ID=16651150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58214156A Granted JPS60107868A (ja) 1983-11-16 1983-11-16 半導体装置

Country Status (1)

Country Link
JP (1) JPS60107868A (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6328074A (ja) * 1986-07-21 1988-02-05 Nec Corp マイクロ波電界効果トランジスタ
JPS63186480A (ja) * 1987-01-28 1988-08-02 Nec Corp マイクロ波スイツチ
US6530068B1 (en) * 1999-08-03 2003-03-04 Advanced Micro Devices, Inc. Device modeling and characterization structure with multiplexed pads
WO2016042861A1 (ja) * 2014-09-17 2016-03-24 シャープ株式会社 化合物半導体電界効果トランジスタ

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56112954U (enrdf_load_stackoverflow) * 1980-01-29 1981-08-31

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56112954U (enrdf_load_stackoverflow) * 1980-01-29 1981-08-31

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6328074A (ja) * 1986-07-21 1988-02-05 Nec Corp マイクロ波電界効果トランジスタ
JPS63186480A (ja) * 1987-01-28 1988-08-02 Nec Corp マイクロ波スイツチ
US6530068B1 (en) * 1999-08-03 2003-03-04 Advanced Micro Devices, Inc. Device modeling and characterization structure with multiplexed pads
WO2016042861A1 (ja) * 2014-09-17 2016-03-24 シャープ株式会社 化合物半導体電界効果トランジスタ

Also Published As

Publication number Publication date
JPH0547983B2 (enrdf_load_stackoverflow) 1993-07-20

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