JPS60107868A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60107868A JPS60107868A JP58214156A JP21415683A JPS60107868A JP S60107868 A JPS60107868 A JP S60107868A JP 58214156 A JP58214156 A JP 58214156A JP 21415683 A JP21415683 A JP 21415683A JP S60107868 A JPS60107868 A JP S60107868A
- Authority
- JP
- Japan
- Prior art keywords
- transistors
- bonding pad
- divided
- gate
- unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 239000004020 conductor Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置に関しさらに詳しくは櫛型構造を有
するGaAs FF1T等のマイクロ波トランジスタに
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a microwave transistor such as a GaAs FF1T having a comb-shaped structure.
GaAsPET等のマイクロ波トランジスタではその出
力を増大するために櫛型の構造をもったものが多い。第
1・図(A)に従来の櫛型構造を有するマイクロ波Ga
AsPETのパターンの一例を示す。第1図(A)に於
いて1はゲートボンディング用パッド(入力端子)、2
はドレインボンディング用パッド(出力端子)、3はソ
ースボンディング用パッドを示している。4.5はそれ
ぞれ一個のゲート。Many microwave transistors such as GaAsPET have a comb-shaped structure in order to increase their output. Figure 1 (A) shows microwave Ga with a conventional comb-shaped structure.
An example of an AsPET pattern is shown. In Figure 1 (A), 1 is a gate bonding pad (input terminal), 2 is a pad for gate bonding (input terminal);
3 indicates a drain bonding pad (output terminal), and 3 indicates a source bonding pad. 4.5 is one gate each.
ドレイン、ソースから形成される単位トランジスタA及
びBを示しており個々の単位トランジスタはゲート給電
用導体6.ドレイン給電用導体7及びソース給電用導体
8によって並列接続され更にゲート給電用導体は接続用
導体9によってゲートボンディング用パッド1に接続さ
れている。第1図(B)は第1図(A)に於けるx −
x’断面を示す。第1図(B)に於いて1はゲー)(A
℃)、2はドレイン(AuGe ) 、 3はソース(
AuGe) を示し且っ4はn型Oa Asエピタキシ
ャル層、5は半絶縁性GaAs基板である。Unit transistors A and B formed from a drain and a source are shown, and each unit transistor has a gate power supply conductor 6. A drain power supply conductor 7 and a source power supply conductor 8 are connected in parallel, and the gate power supply conductor is further connected to the gate bonding pad 1 by a connection conductor 9. Figure 1 (B) shows x − in Figure 1 (A).
An x' cross section is shown. In Figure 1 (B), 1 is game) (A
℃), 2 is the drain (AuGe), 3 is the source (
4 is an n-type OaAs epitaxial layer, and 5 is a semi-insulating GaAs substrate.
ところが第1図(A)、(B)に示すごときトランジス
タによってマイクロ波動作を行なわせるとパターン中の
単位トランジスタA(4)、単位トランジスタB(5)
とゲートボンディング用パッド1との距離がそれぞれ異
なるため電気的長さが異なり単位トランジスタAと単位
トランジスタBとの間に位相差が生じ利得あるいは出力
電力において本来量るべき値より小さい値しか得られな
いという欠点がある。However, when microwave operation is performed using the transistors shown in FIGS. 1(A) and 1(B), unit transistor A (4) and unit transistor B (5) in the pattern are
Since the distances between the transistor A and the gate bonding pad 1 are different, the electrical lengths are different, and a phase difference occurs between the unit transistor A and the unit transistor B, resulting in a gain or output power that is smaller than the originally expected value. There is a drawback that there is no
本発明の目的は櫛型構造マイクロ波トランジスタに於い
て単位トランジスタ間の位相差をなくし出力電力、利得
の低下を防止する給電方法を提供することにある。An object of the present invention is to provide a power supply method that eliminates the phase difference between unit transistors in a comb-shaped microwave transistor and prevents a decrease in output power and gain.
本発明は櫛型構造マイクロ波トランジスタに於いてゲー
トあるいはドレインの少なくとも一方の1個のボンディ
ング用パッドから給電される複数個の単位トランジスタ
を複数の群に分割し該ボンディング用パッドからその分
割された各々の群の略中央へ電気的長さが等しい接続用
導体を用いて接続を行ない単位トランジスタ間の位相差
をなくする様にしたものである。The present invention provides a comb-shaped microwave transistor in which a plurality of unit transistors, each of which is supplied with power from one bonding pad at least one of the gate or drain, is divided into a plurality of groups, and the divided transistors are divided from the bonding pad. Connection is made approximately at the center of each group using connection conductors having the same electrical length to eliminate phase differences between unit transistors.
以下本発明にかかる半導体装置の実施例を図面を参照し
つつ詳細に説明する。第2図は本発明にかかる半導体装
置の一実施例を示す。第2図に12個の単位トランジス
タよりなる櫛型構造GaAs PBT lc示す。11
はゲートボンディング用パッド、12はドレインボンデ
ィング用パッド。Embodiments of the semiconductor device according to the present invention will be described in detail below with reference to the drawings. FIG. 2 shows an embodiment of a semiconductor device according to the present invention. FIG. 2 shows a comb-shaped GaAs PBT lc consisting of 12 unit transistors. 11
1 is a pad for gate bonding, and 12 is a pad for drain bonding.
13はソースボンディング用パッドである。本実施例で
は1個のゲートボンディング用パッド11から給電され
る12偶の単位トランジスタがそれぞれ6個の単位トラ
ンジスタよシなる群14a。13 is a source bonding pad. In this embodiment, the group 14a is made up of 12 even unit transistors each of which is supplied with power from one gate bonding pad 11, each consisting of 6 unit transistors.
14bに分割され分割された群の中間の位置から接続用
導体15a、15bによってゲートボンディング用パッ
ドへの接続がなされている。A connection to a gate bonding pad is made by connection conductors 15a and 15b from a middle position of the group divided into 14b.
第2図のごとき構造とすることにより同図における単位
トランジスタA’(16)&単位トランジスタB’ (
17)との位相差を小さくすることができ本来の高周波
特性を容易に引出すことが可能である。By adopting the structure as shown in Fig. 2, unit transistor A' (16) & unit transistor B' (
17), and the original high frequency characteristics can be easily brought out.
他の実施例を第3図に示す。第3図に於いて21はゲー
トボンディング用パッド、22はドレインボンディング
用パッド、23はソースボンディング用パッドである。Another embodiment is shown in FIG. In FIG. 3, 21 is a gate bonding pad, 22 is a drain bonding pad, and 23 is a source bonding pad.
本実施例では並列接続された16個の単位トランジスタ
が8個の領域に分割され1分割されたそれぞれの単位ト
ランジスタ領域24の中間の位置から接続用導体25に
よってゲートボンディング用パッド21への接続がなさ
れている。In this embodiment, 16 unit transistors connected in parallel are divided into 8 regions, and connection to the gate bonding pad 21 is made by the connection conductor 25 from the middle position of each divided unit transistor region 24. being done.
尚、第2図の実施例に於いては並列接続された複数個の
単位トランジスタt−2分割しゲートボンディング用パ
ッド11からの接続を接続用導体15a、15bによっ
て行なったがドレインボンディング用パッドへの接続を
分割して行なっても同様の効果が期待できることは勿論
である。又1分割数も2分割に限定されるものでないこ
とは勿論である。実施例ではゲート及びドレインボンデ
ィング用パッドはそれぞれ1個ずつであるがボンデイン
ク用パッドが複数の場合にも同様の効果が得られること
は明白である。In the embodiment shown in FIG. 2, a plurality of unit transistors connected in parallel are divided into t-2 parts, and the connection from the gate bonding pad 11 is made by connecting conductors 15a and 15b, but the connection to the drain bonding pad is made by connecting conductors 15a and 15b. Of course, the same effect can be expected even if the connection is divided into sections. Also, it goes without saying that the number of divisions into one is not limited to two. In the embodiment, there is one pad each for gate and drain bonding, but it is clear that the same effect can be obtained even if there is a plurality of pads for bonding ink.
以上詳細に説明したごとく2本発明によれば極めて簡単
なパターン構成により、パターン各部における電気的位
相差を小さくすることが可能であ91位相差による利得
あるいは出力電力の減少を避けることができ、とくに櫛
型構造を有するマイクロ波トランジスタにおいて本発明
の効果は頗る大である。As explained in detail above, according to the present invention, it is possible to reduce the electrical phase difference in each part of the pattern by using an extremely simple pattern configuration, and it is possible to avoid a decrease in gain or output power due to the phase difference. The effects of the present invention are particularly significant in microwave transistors having a comb-shaped structure.
第1図は従来構造を有する半導体装置の1例。
第2図は本発明にか\る半導体装置の1実施例。
第3図は本発明にか\る半導体装置の他の実施例を示す
。
図面において11.21はゲートボンディング用パッド
、12.22はドレインボンディング用パッド、13.
23はソースボンディング用パッド、15a、15b、
25は接続用導体、16゜17.24は単位トランジス
タ領域をそれぞれ示す。FIG. 1 shows an example of a semiconductor device having a conventional structure. FIG. 2 shows one embodiment of a semiconductor device according to the present invention. FIG. 3 shows another embodiment of the semiconductor device according to the present invention. In the drawing, 11.21 is a gate bonding pad, 12.22 is a drain bonding pad, and 13.
23 are source bonding pads, 15a, 15b,
Reference numeral 25 indicates a connecting conductor, and reference numerals 16, 17, and 24 indicate unit transistor regions, respectively.
Claims (1)
ら成る単位トランジスタ領域が複数形成され、前記単位
トランジスタ領域が各々ゲート給電用導体、ドレイン給
電用導体、ソース給電用導体によって複敬個並列接続さ
れ且つ前記各給電用導体が接続用導体によってボンディ
ング用パッドに接続された櫛型構造を有し、ゲートおる
いはドレインの少なくとも一方の一個のボンディング用
パッドから給電される複数個の単位トランジスタを複数
群に分割し、該ボンディング用パッドとその分割された
各単位トランジスタ群とのほぼ9央とを電気的長さが寺
しい接続用導体により接続したことを特徴とする半導体
装置。 2.1個のボンディング用パッドから給電される複数個
の単位トランジスタfi−2n群に分割することを特徴
とする特許請求の範囲1項記載の半導体装置。[Claims] 1. A plurality of unit transistor regions each consisting of a drain, a source, and a gate sandwiched therebetween are formed, and each of the unit transistor regions is multiplied by a gate power supply conductor, a drain power supply conductor, and a source power supply conductor. A plurality of power supply conductors connected in parallel in parallel, each having a comb-shaped structure in which each of the power supply conductors is connected to a bonding pad by a connection conductor, and is supplied with power from one bonding pad of at least one of the gate and the drain. A semiconductor device characterized in that the unit transistors are divided into a plurality of groups, and the bonding pad and approximately the center of each of the divided unit transistor groups are connected by a connecting conductor having a short electrical length. . 2. The semiconductor device according to claim 1, wherein the semiconductor device is divided into a plurality of unit transistors fi-2n groups that are supplied with power from one bonding pad.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58214156A JPS60107868A (en) | 1983-11-16 | 1983-11-16 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58214156A JPS60107868A (en) | 1983-11-16 | 1983-11-16 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60107868A true JPS60107868A (en) | 1985-06-13 |
JPH0547983B2 JPH0547983B2 (en) | 1993-07-20 |
Family
ID=16651150
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58214156A Granted JPS60107868A (en) | 1983-11-16 | 1983-11-16 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60107868A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6328074A (en) * | 1986-07-21 | 1988-02-05 | Nec Corp | Microwave field effect transistor |
JPS63186480A (en) * | 1987-01-28 | 1988-08-02 | Nec Corp | Microwave switch |
US6530068B1 (en) * | 1999-08-03 | 2003-03-04 | Advanced Micro Devices, Inc. | Device modeling and characterization structure with multiplexed pads |
WO2016042861A1 (en) * | 2014-09-17 | 2016-03-24 | シャープ株式会社 | Compound semiconductor field effect transistor |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56112954U (en) * | 1980-01-29 | 1981-08-31 |
-
1983
- 1983-11-16 JP JP58214156A patent/JPS60107868A/en active Granted
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS56112954U (en) * | 1980-01-29 | 1981-08-31 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6328074A (en) * | 1986-07-21 | 1988-02-05 | Nec Corp | Microwave field effect transistor |
JPS63186480A (en) * | 1987-01-28 | 1988-08-02 | Nec Corp | Microwave switch |
US6530068B1 (en) * | 1999-08-03 | 2003-03-04 | Advanced Micro Devices, Inc. | Device modeling and characterization structure with multiplexed pads |
WO2016042861A1 (en) * | 2014-09-17 | 2016-03-24 | シャープ株式会社 | Compound semiconductor field effect transistor |
Also Published As
Publication number | Publication date |
---|---|
JPH0547983B2 (en) | 1993-07-20 |
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