JPH0547983B2 - - Google Patents

Info

Publication number
JPH0547983B2
JPH0547983B2 JP58214156A JP21415683A JPH0547983B2 JP H0547983 B2 JPH0547983 B2 JP H0547983B2 JP 58214156 A JP58214156 A JP 58214156A JP 21415683 A JP21415683 A JP 21415683A JP H0547983 B2 JPH0547983 B2 JP H0547983B2
Authority
JP
Japan
Prior art keywords
power supply
conductor
gate
drain
supply conductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58214156A
Other languages
Japanese (ja)
Other versions
JPS60107868A (en
Inventor
Jun Fukaya
Yutaka Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58214156A priority Critical patent/JPS60107868A/en
Publication of JPS60107868A publication Critical patent/JPS60107868A/en
Publication of JPH0547983B2 publication Critical patent/JPH0547983B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]

Description

【発明の詳細な説明】 本発明は櫛型構造を有するGaAs FET等のマ
イクロ波トランジスタに関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microwave transistor such as a GaAs FET having a comb-shaped structure.

GaAs FET等のマイクロ波トランジスタでは
その出力を増大するために櫛型の構造をもつたも
のが多い。第1図Aに従来の櫛型構造を有するマ
イクロ波GaAs FETのパターンの一例を示す。
第1図Aに於いて1はゲートボンデイング用パツ
ド(入力端子)、2はドレインボンデイング用パ
ツド(出力端子)、3はソースボンデイング用パ
ツドを示している。A,Bはそれぞれ一個のゲー
ト、ドレイン、ソースから形成される単位トラン
ジスタを示しており個々の単位トランジスタはゲ
ート給電用導体6、ドレイン給電用導体7及びソ
ース給電用導体8によつて並列接続され更にゲー
ト給電用導体は接続用導体9によつてゲートボン
デイング用パツド1に接続されている。第1図B
は第1図Aに於けるX−X′断面を示す。第1図
Bに於いて1aはゲートA1、2aはドレイン
(AuGe)、3aはソース(AuGe)を示し且つ4
はn型GaAsエピタキシヤル層、5は半絶縁性
GaAs基板である。
Microwave transistors such as GaAs FETs often have a comb-shaped structure to increase their output. FIG. 1A shows an example of a pattern of a conventional microwave GaAs FET having a comb structure.
In FIG. 1A, 1 indicates a gate bonding pad (input terminal), 2 indicates a drain bonding pad (output terminal), and 3 indicates a source bonding pad. A and B each indicate a unit transistor formed from one gate, one drain, and one source, and each unit transistor is connected in parallel by a gate power supply conductor 6, a drain power supply conductor 7, and a source power supply conductor 8. Further, the gate power supply conductor is connected to the gate bonding pad 1 by a connecting conductor 9. Figure 1B
shows a cross section taken along line X-X' in FIG. 1A. In FIG. 1B, 1a represents the gate A1, 2a represents the drain (AuGe), 3a represents the source (AuGe), and 4
is an n-type GaAs epitaxial layer, 5 is a semi-insulating layer
It is a GaAs substrate.

ところが第1図A,Bに示すごときトランジス
タによつてマイクロ波動作を行なわせるとパター
ン中の単位トランジスタA、単位トランジスタB
とゲートボンデイング用パツド1との距離がそれ
ぞれ異なるため電気的長さが異なり単位トランジ
スタAと単位トランジスタBとの間に位相差が生
じ利得あるいは出力電力において本来出るべき値
より小さい値しか得られないという欠点がある。
However, when microwave operation is performed using transistors such as those shown in FIG. 1A and B, unit transistor A and unit transistor B in the pattern are
Since the distances between the gate bonding pad 1 and the gate bonding pad 1 are different, the electrical lengths are different, and a phase difference occurs between the unit transistor A and the unit transistor B, resulting in a gain or output power that is smaller than the originally expected value. There is a drawback.

なお各単位トランジスタ群を分割してゲートボ
ンデイング用パツドと電気的長さの等しい接続用
導体にて接続する技術に関しては実開昭56−
112954号公報に開示されている。該公報に開示さ
れた技術は単位トランジスタ群を複数の群に分割
して各群を長さの等しい接続用導体でボンデイン
グ用パツドに接続しているため群同志による閉回
路が形成されてしまい、低い周波数の自己発振が
発生しやすく出力電力や利得の低下を招くという
欠点がある。
Note that the technique of dividing each unit transistor group and connecting it with a gate bonding pad and a connecting conductor of equal electrical length is described in Utility Model Application No. 56-
It is disclosed in Publication No. 112954. The technique disclosed in this publication divides a unit transistor group into a plurality of groups and connects each group to a bonding pad with a connecting conductor of equal length, so a closed circuit is formed between the groups. The drawback is that low frequency self-oscillation is likely to occur, resulting in a decrease in output power and gain.

本発明の目的は櫛型構造マイクロ波トランジス
タに於いて単位トランジスタ間の位相差をなくし
出力電力、利得の低下を防止する給電方法を提供
することにある。
An object of the present invention is to provide a power supply method that eliminates the phase difference between unit transistors in a comb-shaped microwave transistor and prevents a decrease in output power and gain.

本発明はドレイン電極、ソース電極およびこれ
らに挟まれたゲート電極を有する単位トランジス
タが、前記ソース、ドレインおよびゲート電極の
長手方向とは直角方向に複数個隣接して形成され
ており、該複数個の単位トランジスタのゲート電
極およびドレイン電極およびソース電極がそれぞ
れゲート給電用導体、ドレイン給電用導体、ソー
ス給電用導体によつてボンデイングパツドに接続
されてなる櫛型構造のマイクロ波トランジスタに
おいて、前記単位トランジスタのゲートもしくは
ドレイン電極の少なくとも一方は隣接する電極同
志を共通に接続する共通接続用導体に接続し、前
記共通接続導体に接続される前記ゲート給電用導
体もしくはドレイン給電用導体は、前記ボンデイ
ングパツドに接続される側で1本に収束されると
ともに、前記共通接続導体に接続される側におい
てはその先端が複数本に分割されている分岐を有
することで前記複数の単位トランジスタの各々か
ら前記ボンデイングパツドまでの給電用導体長を
近似した位相差を少なくするようにしたものであ
る。
In the present invention, a plurality of unit transistors having a drain electrode, a source electrode, and a gate electrode sandwiched therebetween are formed adjacent to each other in a direction perpendicular to the longitudinal direction of the source, drain, and gate electrodes, and A microwave transistor having a comb-shaped structure in which a gate electrode, a drain electrode, and a source electrode of a unit transistor are connected to a bonding pad by a gate power supply conductor, a drain power supply conductor, and a source power supply conductor, respectively. At least one of the gate or drain electrodes of the transistor is connected to a common connection conductor that commonly connects adjacent electrodes, and the gate power supply conductor or drain power supply conductor connected to the common connection conductor is connected to the bonding pad. By having a branch whose tip is converged into one on the side connected to the common connection conductor and divided into a plurality of pieces on the side connected to the common connection conductor, the This is designed to reduce the phase difference by approximating the length of the power supply conductor up to the bonding pad.

以下本発明にかかる半導体装置の実施例を示
す。第2図に12個の単位トランジスタよりなる櫛
型構造GaAs FETを示す。11はゲートボンデ
イング用パツド、12はドレインボンデイング用
パツド、13はソースボンデイング用パツドであ
る。
Examples of the semiconductor device according to the present invention will be shown below. Figure 2 shows a comb-shaped GaAs FET consisting of 12 unit transistors. 11 is a pad for gate bonding, 12 is a pad for drain bonding, and 13 is a pad for source bonding.

本実施例では各単位トランジスタ18a,18
b,…181のドレイン電極、ソース1極および
ゲート電極は、その長手方向とは直角に複数個隣
接して形成され、単位トランジスタのゲート電
極、ドレイン電極およびソース電極はそれぞれゲ
ート給電用導体、ドレイン給電用導体、およびソ
ース給電用導体によつてそれぞれのボンデイング
用パツド11,12,13に接続されている。本
実施例においては1個のゲートボンデイングパツ
ド11から給電される12個の単位トランジスタ1
8a,18b,…,181がそれぞれ6個の単位
トランジスタよりなる群14a,14bに分割さ
れ分割された群の接続される共通導体15cの分
割された群に接続される部分の略中間の位置から
接続用導体15a,15bによつてゲートボンデ
イング用パツド11への接続がなされている。
In this embodiment, each unit transistor 18a, 18
A plurality of drain electrodes, source electrodes, and gate electrodes of b,...181 are formed adjacent to each other at right angles to the longitudinal direction, and the gate electrode, drain electrode, and source electrode of the unit transistor are connected to the gate power supply conductor and the drain electrode, respectively. It is connected to each bonding pad 11, 12, 13 by a power supply conductor and a source power supply conductor. In this embodiment, 12 unit transistors 1 are supplied with power from one gate bonding pad 11.
8a, 18b, . Connection to the gate bonding pad 11 is made by connection conductors 15a and 15b.

第2図のごとき構造とすることにより同図にお
ける例えば単位トランジスタ18dと単位トラン
ジスタ18fとの位相差を小さくすることができ
るのみならず給電用導体と電極の接続部は共通接
続用の導体によつて共通に接続されているため単
位トランジスタ間の不要な寄生発振を発生するこ
ともなく本来の高周波特性を容易に引き出すこと
が可能である。
By adopting the structure as shown in Fig. 2, it is possible not only to reduce the phase difference between, for example, the unit transistor 18d and the unit transistor 18f in the same figure, but also to connect the power supply conductor and the electrode to the common connection conductor. Since they are commonly connected, it is possible to easily bring out the original high frequency characteristics without generating unnecessary parasitic oscillation between the unit transistors.

他の実施例を第3図に示す。第3図に於いて2
1はゲートボンデイング用パツド、22はドレイ
ンボンデイング用パツド、23はソースボンデイ
ング用パツドである。本実施例では並列接続され
た共通接続部25cに接続された16個の単位トラ
ンジスタが8個の領域に分割され、分割されたそ
れぞれの単位トランジスタ領域24の共通接続部
の中間の位置から接続用導体25によつてゲート
ボンデイング用パツド21への接続がなされてい
る。
Another embodiment is shown in FIG. In Figure 3, 2
1 is a pad for gate bonding, 22 is a pad for drain bonding, and 23 is a pad for source bonding. In this embodiment, the 16 unit transistors connected to the common connection part 25c connected in parallel are divided into eight regions, and the connection is made from the middle position of the common connection part of each divided unit transistor region 24. Connection to gate bonding pad 21 is made by conductor 25.

尚、第2図の実施例に於いては並列接続された
複数個の単位トランジスタを2分割しゲートボン
デイング用パツド11からの接続を接続用導体1
5a,15bによつて行なつたがドレインボンデ
イング用パツドへの接続を分割して行なつても同
様の効果が期待できることは勿論である。又、分
割数も2分割に限定されるものでないことは勿論
である。実施例ではゲート及びドレインボンデイ
ング用パツドはそれぞれ1個ずつであるがボンデ
イング用パツドが複数の場合にも同様の効果が得
られることは明白である。
In the embodiment shown in FIG. 2, a plurality of unit transistors connected in parallel are divided into two, and the connection from the gate bonding pad 11 is connected to the connection conductor 1.
5a and 15b, but it goes without saying that the same effect can be expected even if the connection to the drain bonding pads is made separately. Furthermore, it goes without saying that the number of divisions is not limited to two. In the embodiment, there is one pad each for gate and drain bonding, but it is clear that the same effect can be obtained even if there are a plurality of pads for bonding.

以上詳細に説明したごとく、本発明によれば極
めて簡単なパターン構成により、パターン各部に
おける電気的位相差を小さくできるのみならず、
単位トランジスタのすべてが共通接続用の導体に
よつて共通接続されているため寄生発振による出
力電力の減少を避けることができるため、櫛型構
造を有するマイクロ波トランジスタにおいて本発
明の効果は頗る大である。
As explained in detail above, according to the present invention, with an extremely simple pattern configuration, it is possible not only to reduce the electrical phase difference in each part of the pattern, but also to
Since all of the unit transistors are commonly connected by a common connection conductor, a decrease in output power due to parasitic oscillation can be avoided, so the effect of the present invention is extremely large in microwave transistors having a comb-shaped structure. be.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来構造を有する半導体装置の1例、
第2図は本発明にかゝる半導体装置の1実施例、
第3図は本発明にかゝる半導体装置の他の実施例
を示す。 図面において11,21はゲートボンデイング
用パツド、12,22はドレインボンデイング用
パツド、13,23はソースボンデイング用パツ
ド、15a,15b,25は接続用導体、16,
17,24は単位トランジスタ領域、15cおよ
び25cは共通接続用導体をそれぞれ示す。
Figure 1 shows an example of a semiconductor device with a conventional structure.
FIG. 2 shows an embodiment of a semiconductor device according to the present invention.
FIG. 3 shows another embodiment of the semiconductor device according to the present invention. In the drawing, 11 and 21 are pads for gate bonding, 12 and 22 are pads for drain bonding, 13 and 23 are pads for source bonding, 15a, 15b, and 25 are connection conductors;
17 and 24 are unit transistor regions, and 15c and 25c are common connection conductors, respectively.

Claims (1)

【特許請求の範囲】 1 ドレイン電極、ソース電極およびこれらに挟
まれたゲート電極を有する単位トランジスタが、
前記ソース、ドレインおよびゲート電極の長手方
向とは直角方向に複数個隣接して形勢されてお
り、該複数個の単位トランジスタのゲート電極、
ドレイン電極およびソース電極がそれぞれゲート
給電用導体、ドレイン給電用導体、ソース給電用
導体によつてボンデイングパツドに接続されてな
る櫛型構造のマイクロ波トランジスタにおいて、 前記単位トランジスタのゲート電極もしくはド
レイン電極の少なくとも一方は隣接する電極同志
を共通に接続する共通接続用導体に接続し、 前記共通接続用導体に接続されるゲート給電用
導体もしくはドレイン給電用導体は、前記ボンデ
イングパツドに接続される側で1本に収束される
とともに、前記共通用導体に接続される側ではそ
の先端が複数本に分割されている分岐を有するこ
とで、前記複数の単位トランジスタの各々から前
記ボンデイングパツド迄の給電用導体長を近似さ
せる樹枝状構造としたことを特徴とするマイクロ
波トランジスタ。 2 前記樹枝状構造の給電用導体は前記1本に収
束された側から派生してその先端が分割される多
岐を多段階に繰り返してなり、該ボンデイングパ
ツドから該複数個の単位トランジスタの各々迄の
導体長を全てについて等しく構成したことを特徴
とする特許請求の範囲第1項記載のマイクロ波ト
ランジスタ。
[Claims] 1. A unit transistor having a drain electrode, a source electrode, and a gate electrode sandwiched therebetween,
A plurality of the source, drain, and gate electrodes are arranged adjacent to each other in a direction perpendicular to the longitudinal direction, and the gate electrodes of the plurality of unit transistors;
In a microwave transistor having a comb-shaped structure in which a drain electrode and a source electrode are connected to a bonding pad by a gate power supply conductor, a drain power supply conductor, and a source power supply conductor, respectively, the gate electrode or the drain electrode of the unit transistor At least one of the electrodes is connected to a common connection conductor that commonly connects adjacent electrodes, and the gate power supply conductor or drain power supply conductor connected to the common connection conductor is connected to the bonding pad. By having a branch whose tip is divided into a plurality of branches on the side connected to the common conductor, the power is supplied from each of the plurality of unit transistors to the bonding pad. A microwave transistor characterized by having a dendritic structure that approximates the length of a conductor. 2. The power supply conductor having the dendritic structure is formed by repeating a multi-step process in which the power supply conductor is derived from the converged side and divided at its tip in multiple stages, and is connected to each of the plurality of unit transistors from the bonding pad. 2. The microwave transistor according to claim 1, wherein all conductor lengths are the same.
JP58214156A 1983-11-16 1983-11-16 Semiconductor device Granted JPS60107868A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58214156A JPS60107868A (en) 1983-11-16 1983-11-16 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58214156A JPS60107868A (en) 1983-11-16 1983-11-16 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS60107868A JPS60107868A (en) 1985-06-13
JPH0547983B2 true JPH0547983B2 (en) 1993-07-20

Family

ID=16651150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58214156A Granted JPS60107868A (en) 1983-11-16 1983-11-16 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS60107868A (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6328074A (en) * 1986-07-21 1988-02-05 Nec Corp Microwave field effect transistor
JPH07120677B2 (en) * 1987-01-28 1995-12-20 日本電気株式会社 Microwave switch
US6530068B1 (en) * 1999-08-03 2003-03-04 Advanced Micro Devices, Inc. Device modeling and characterization structure with multiplexed pads
US20170301766A1 (en) * 2014-09-17 2017-10-19 Sharp Kabushiki Kaisha Compound semiconductor field effect transistor

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6228788Y2 (en) * 1980-01-29 1987-07-23

Also Published As

Publication number Publication date
JPS60107868A (en) 1985-06-13

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