JPS6228788Y2 - - Google Patents

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Publication number
JPS6228788Y2
JPS6228788Y2 JP1980009086U JP908680U JPS6228788Y2 JP S6228788 Y2 JPS6228788 Y2 JP S6228788Y2 JP 1980009086 U JP1980009086 U JP 1980009086U JP 908680 U JP908680 U JP 908680U JP S6228788 Y2 JPS6228788 Y2 JP S6228788Y2
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JP
Japan
Prior art keywords
power supply
electrode
pad
gate
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP1980009086U
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Japanese (ja)
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JPS56112954U (en
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Priority to JP1980009086U priority Critical patent/JPS6228788Y2/ja
Publication of JPS56112954U publication Critical patent/JPS56112954U/ja
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Expired legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【考案の詳細な説明】 本考案は接合ゲート型電界効果トランジスタに
関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a junction gate field effect transistor.

マイクロ波増幅用の電界効果トランジスタ
(FET)としては、シリコン(Si)のような元素
半導体を用いたFET、砒化ガリウム(GaAs)等
の化合物半導体を用いたシヨツトキ接合ゲート型
電界効果トランジスタ(MESFET)等があり、
特に後者は前者に比べてより高い周波数帯で増幅
動作が可能である。このようなGaAs MESFET
ではゲート電極金属の直列抵抗を減少させること
を目的として、第1図に示すように動作層2の上
にソース電極31、ドレイン電極41を交互に配
置し、その間にゲート電極51を配置することが
多い。隣接した一組のソース電極、ゲート電極、
ドレイン電極6は単位素子と呼ばれる。各ゲート
電極はゲート給電母線520に接続され、ゲート
給電パツド53より一括してゲートバイアス電圧
と入力電気信号を給電される。また各ドレイン電
極もゲート電極と同様に、ドレイン給電母線42
0に接続され、ドレイン給電パツド43より一括
してドレインバイアス電圧の給電と、出力電気信
号の取出しが行なわれることが多い。
Field effect transistors (FETs) for microwave amplification include FETs that use elemental semiconductors such as silicon (Si), and Schottky junction field effect transistors (MESFETs) that use compound semiconductors such as gallium arsenide (GaAs). etc.,
In particular, the latter allows amplification operation in a higher frequency band than the former. GaAs MESFET like this
In order to reduce the series resistance of the gate electrode metal, as shown in FIG. 1, source electrodes 31 and drain electrodes 41 are alternately arranged on the active layer 2, and a gate electrode 51 is arranged between them. There are many. a set of adjacent source electrodes, gate electrodes,
The drain electrode 6 is called a unit element. Each gate electrode is connected to a gate power supply bus 520, and is collectively supplied with a gate bias voltage and an input electrical signal from a gate power supply pad 53. In addition, each drain electrode is connected to the drain power supply bus 42 in the same way as the gate electrode.
0, and the drain bias voltage is often supplied and the output electric signal is taken out all at once from the drain power supply pad 43.

かかるGaAs MESFETでは、ゲート給電パツ
ドから各ゲート電極に至るゲート給電路の実効
長、あるいはドレイン給電パツドから各ドレイン
電極に至るドレイン給電路の実効長が、各々の単
位素子により異なるため、マイクロ波帯では各単
位素子は同一位相で均衡して動作できなくなる。
例えば厚さ0.15mmの高抵抗GaAs基板上に形成さ
れた幅20μmのゲート給電母線を伝播する20GHz
の信号の1波長は略4.4mmである。給電パツドに
最も近いゲート電極から給電パツドに至る実効長
と、給電パツドから最も遠いゲート電極から給電
パツドに至る実効長との差が4.4mmに比べて充分
に小さい場合は何等支障はないが、例えばその差
が2.2mmになると、給電パツドに最も近いゲート
電極と、最も遠いゲート電極に加わる信号は完全
に逆位相となり、互いに出力を打ち消し合うこと
になる。各単位素子間の位相差は、単位素子数を
増すほど、あるいは周波数が高くなるほど大きく
なることから、単位素子数を増しても出力電力の
増加が少ない、あるいは周波数が高くなると利
得、出力電力が著しく低下する、等の不都合があ
り、またMESFETの動作が不安定で自己発振を
起こし易くなる欠点があつた。
In such a GaAs MESFET, the effective length of the gate power supply path from the gate power supply pad to each gate electrode, or the effective length of the drain power supply path from the drain power supply pad to each drain electrode, differs for each unit element, so that in the microwave band, each unit element cannot operate in a balanced manner with the same phase.
For example, a 20 GHz wave propagating through a 20 μm wide gate power bus formed on a 0.15 mm thick high resistivity GaAs substrate.
One wavelength of the signal is approximately 4.4 mm. If the difference between the effective length from the gate electrode closest to the feed pad to the feed pad and the effective length from the gate electrode furthest from the feed pad to the feed pad is sufficiently small compared to 4.4 mm, there is no problem. However, if the difference is, for example, 2.2 mm, the signals applied to the gate electrode closest to the feed pad and the gate electrode furthest from the feed pad will be in completely opposite phase, and will cancel each other out. Since the phase difference between each unit element increases as the number of unit elements increases or the frequency increases, there are inconveniences such as little increase in output power even if the number of unit elements is increased, or the gain and output power drop significantly as the frequency increases, and there is also the disadvantage that the operation of the MESFET is unstable and prone to self-oscillation.

本考案の目的は上記従来の欠点をなくした接合
ゲート型電界効果トランジスタを提供することに
ある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a junction gate field effect transistor that eliminates the above-mentioned conventional drawbacks.

本考案によれば複数のソース電極、ドレイン電
極が交互に配置され、該ソース電極とドレイン電
極の間に接合ゲート電極が設けられ、かつ該ソー
ス電極、ドレイン電極、ゲート電極の少なくとも
一種類の電極に対して、外部回路との電気的接続
が行なわれる金属膜からなる給電パツドと該給電
パツドと電極とを連結する金属膜からなる給電母
線とを具えてなる接合ゲート型電界効果トランジ
スタにおいて、前記給電母線の少なくとも一種類
が、給電パツドより派生して2つ以上に分岐され
て第1段給電母線を形成し、該第1段給電母線の
終端から派生して2つ以上に分岐されて第2段給
電母線を形成する該分岐を順次くり返し構成され
た2段以上の樹枝状構造を有し、且つ給電パツド
から各電極に至る給電路の実効長の差が、前記給
電母線を伝送される電気信号の波長に比べて実用
上無視しうる程度に小さいことを特徴とする接合
ゲート型電界効果トランジスタが得られる。
According to the present invention, a plurality of source electrodes and drain electrodes are arranged alternately, a junction gate electrode is provided between the source electrodes and the drain electrodes, and at least one type of electrode of the source electrode, drain electrode, and gate electrode is provided. In contrast, in a junction gate field effect transistor comprising a power supply pad made of a metal film for electrical connection with an external circuit and a power supply bus bar made of a metal film connecting the power supply pad and an electrode, At least one type of feeding bus is derived from a feeding pad and branched into two or more to form a first stage feeding bus, and is derived from an end of the first stage feeding bus and branched into two or more to form a first stage feeding bus. It has a dendritic structure of two or more stages in which the branches forming a two-stage power supply bus are successively repeated, and the difference in the effective length of the power supply path from the power supply pad to each electrode is transmitted through the power supply bus. A junction gate field effect transistor is obtained which is characterized by a wavelength that is practically negligible compared to the wavelength of an electric signal.

以下図面により本考案を説明する。 The present invention will be explained below with reference to the drawings.

第2図は本考案の一実施例を示す図面である。
第2図において1はクロムをドープした高抵抗
GaAs基板、2はその上に成長されたキヤリア密
度1.5×1017cm-3、厚さ約0.27μmのn型GaAsエ
ピタキシヤル動作層である。この動作層の上には
金・ゲルマニウム合金、ニツケル、金をこの順に
積層したソース電極31、ドレイン電極41が、
3μmの間隔をおいて交互に形成され、給電パツ
ドより派生して2つ以上に分岐されて第1段給電
母線を形成し、該第1段給電母線の終端から派生
して2つ以上に分岐されて第2段給電母線を形成
する該分岐を順次くり返し、2分岐3段の樹枝状
構造のドレイン給電母線421,422,42
3、およびドレイン給電パツド43も同時に形成
される。シヨツトキ接合電極51は厚さ0.6μm
のアルミニウム(Al)膜を使用し、ソース電極
とドレイン電極の間に太さ0.7μm、長さ100μm
になるように形成され、2分岐2段、4分岐1段
の樹枝状構造のゲート給電母線523,522,
521およびゲート給電パツド53が同時に形成
される。ゲート電極とゲート電極の間隔は30μm
である。フリツプチツプマウント(flip−tip
mount)による直接接地ができる様に、ソース電
極31は選択的に厚さ12μmの金めつきが施され
る。
FIG. 2 is a drawing showing an embodiment of the present invention.
In Figure 2, 1 is a high resistance doped with chromium.
The GaAs substrate 2 is an n-type GaAs epitaxial active layer with a carrier density of 1.5×10 17 cm −3 and a thickness of about 0.27 μm grown thereon. On this active layer, a source electrode 31 and a drain electrode 41 are formed by laminating gold/germanium alloy, nickel, and gold in this order.
They are formed alternately at intervals of 3 μm, are derived from the power supply pad and branched into two or more to form a first stage power supply bus, and are derived from the terminal end of the first stage power supply bus and branched into two or more. By sequentially repeating the branching to form a second-stage power supply bus, a drain power supply bus 421, 422, 42 having a dendritic structure with two branches and three stages is formed.
3 and drain power supply pad 43 are also formed at the same time. The thickness of the shot junction electrode 51 is 0.6 μm.
An aluminum (Al) film with a thickness of 0.7 μm and a length of 100 μm is used between the source and drain electrodes.
Gate power supply buses 523, 522, which have a dendritic structure with two branches, two stages, and four branches, one stage.
521 and gate feed pad 53 are formed simultaneously. The distance between gate electrodes is 30μm
It is. flip-tip mount
The source electrode 31 is selectively plated with gold to a thickness of 12 μm so that it can be directly grounded by a mount.

このように給電母線を樹枝状構造にすることに
より、給電パツドから各電極に至る給電路の実効
長の差はほとんどなくなり、各単位素子は同一位
相で均衡して動作できる様になつた。この結果
MESFETの動作は極めて安定になり、整合回路
およびバイアス回路の設計、調整が容易となつ
た。また自己発振も防止され、自己発振による
MESFETの破壊もなくなり、信頼性が向上し
た。また18GHzにおいて利得が0.5dB、飽和出力
電力が0.3dBそれぞれ改善された。
By forming the power supply bus into a dendritic structure in this way, there is almost no difference in the effective length of the power supply path from the power supply pad to each electrode, and each unit element can now operate in a balanced manner with the same phase. As a result
MESFET operation has become extremely stable, and matching and bias circuits have become easier to design and adjust. Self-oscillation is also prevented, and self-oscillation
MESFET destruction has also been eliminated, improving reliability. Also, at 18GHz, the gain was improved by 0.5dB and the saturated output power was improved by 0.3dB.

本実施例においては、ドレイン給電母線および
ゲート給電母線の両方が樹枝状構造の場合につい
て説明したが、いずれか一方の給電母線のみを樹
枝状構造としても、従来の欠点をなくしたGaAs
MESFETが得られることは言うまでもない。な
お、本実施例によるGaAs MESFETは18GHzの
信号を増幅するように設計されているので隣接す
るゲート電極同志の間隔を30μmとし、ゲート給
電母線の最終段は4分岐とした。18GHzの信号の
1波長は略4.8mmであるため、4分岐された4本
のゲート電極間の距離の差は30μm、波長の1%
以下と充分に小さく、その影響は実用上無視し得
る。またソース電極に対して同様の構造を適用す
ると、フリツプチツプマウントをしなくとも、帰
還素子として働く接地インピーダンスを均一にで
きる利点がある。またn型GaAsを使用した場合
についてのみ示したがp型GaAs、あるいはGaAs
以外の化合物半導体、またはSiについても同様で
あることは言うまでもない。
In this example, the case where both the drain power supply bus and the gate power supply bus have a dendritic structure has been described, but it is also possible to create a GaAs
Needless to say, MESFET can be obtained. Note that since the GaAs MESFET according to this example is designed to amplify a signal of 18 GHz, the interval between adjacent gate electrodes was set to 30 μm, and the final stage of the gate power supply bus had four branches. One wavelength of an 18GHz signal is approximately 4.8mm, so the difference in distance between the four gate electrodes that are branched into four is 30μm, which is 1% of the wavelength.
It is sufficiently small as below, and its influence can be ignored in practical terms. Further, if a similar structure is applied to the source electrode, there is an advantage that the ground impedance acting as a feedback element can be made uniform without flip-chip mounting. Also, only the case where n-type GaAs is used is shown, but p-type GaAs or GaAs
Needless to say, the same applies to other compound semiconductors or Si.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のシヨツトキ接合ゲート型電界効
果トランジスタを説明するための図面、第2図は
本考案の一実施例を説明するための図面である。
図面において1は高抵抗半導体基板、2は半導体
動作層、31はソース電極、41はドレイン電
極、420〜423はドレイン給電母線、43は
ドレイン給電パツド、51はゲート電極、520
〜523はゲート給電母線、53はゲート給電パ
ツド、6は単位素子を示す。
FIG. 1 is a diagram for explaining a conventional shotgun junction gate field effect transistor, and FIG. 2 is a diagram for explaining an embodiment of the present invention.
In the drawing, 1 is a high resistance semiconductor substrate, 2 is a semiconductor active layer, 31 is a source electrode, 41 is a drain electrode, 420 to 423 are drain power supply buses, 43 is a drain power supply pad, 51 is a gate electrode, 520
523 is a gate power supply bus, 53 is a gate power supply pad, and 6 is a unit element.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のソース電極、ドレイン電極が交互に配置
され、該ソース電極とドレイン電極の間に接合ゲ
ート電極が設けられ、かつ該ソース電極、ドレイ
ン電極、ゲート電極の少なくとも一種類の電極に
対して、外部回路との電気的接続が行なわれる金
属膜からなる給電パツドと、該給電パツドと電極
とを連結する金属膜からなる給電母線とを具えて
なる接合ゲート型電界効果トランジスタにおい
て、前記給電母線の少なくとも一種類が給電パツ
ドより派生して2つ以上に分岐されて第1段給電
母線を形成し、該第1段給電母線の終端から派生
して2つ以上に分岐されて第2段給電母線を形成
する該分岐を順次くり返し構成された2段以上の
樹枝状構造を有し、且つ給電パツドから各電極に
至る給電路の実効長の差が、前記給電母線を伝送
される電気信号の波長に比べて実用上無視しうる
程度に小さいことを特徴とする接合ゲート型電界
効果トランジスタ。
A plurality of source electrodes and drain electrodes are arranged alternately, a junction gate electrode is provided between the source electrodes and the drain electrodes, and an external In a junction gate field effect transistor comprising a power supply pad made of a metal film for electrical connection with a circuit, and a power supply bus bar made of a metal film connecting the power supply pad and an electrode, at least One type is derived from a power supply pad and branches into two or more to form a first stage power supply bus, and one type is derived from the end of the first stage power supply and branched into two or more to form a second stage power supply bus. It has a dendritic structure of two or more stages in which the forming branches are sequentially repeated, and the difference in the effective length of the power supply path from the power supply pad to each electrode corresponds to the wavelength of the electrical signal transmitted through the power supply bus. A junction gate field effect transistor is characterized by being so small that it can be ignored in practical terms.
JP1980009086U 1980-01-29 1980-01-29 Expired JPS6228788Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1980009086U JPS6228788Y2 (en) 1980-01-29 1980-01-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1980009086U JPS6228788Y2 (en) 1980-01-29 1980-01-29

Publications (2)

Publication Number Publication Date
JPS56112954U JPS56112954U (en) 1981-08-31
JPS6228788Y2 true JPS6228788Y2 (en) 1987-07-23

Family

ID=29605739

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1980009086U Expired JPS6228788Y2 (en) 1980-01-29 1980-01-29

Country Status (1)

Country Link
JP (1) JPS6228788Y2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60107868A (en) * 1983-11-16 1985-06-13 Fujitsu Ltd Semiconductor device
JPH0793321B2 (en) * 1985-08-13 1995-10-09 松下電子工業株式会社 Semiconductor device
US9972624B2 (en) 2013-08-23 2018-05-15 Qualcomm Incorporated Layout construction for addressing electromigration
US9786663B2 (en) 2013-08-23 2017-10-10 Qualcomm Incorporated Layout construction for addressing electromigration

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5270731A (en) * 1975-11-27 1977-06-13 Nec Corp High frequency power distribution/composition circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5270731A (en) * 1975-11-27 1977-06-13 Nec Corp High frequency power distribution/composition circuit

Also Published As

Publication number Publication date
JPS56112954U (en) 1981-08-31

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