JPS60105243A - Fully automatic wire bonding equipment for multichip - Google Patents
Fully automatic wire bonding equipment for multichipInfo
- Publication number
- JPS60105243A JPS60105243A JP58213641A JP21364183A JPS60105243A JP S60105243 A JPS60105243 A JP S60105243A JP 58213641 A JP58213641 A JP 58213641A JP 21364183 A JP21364183 A JP 21364183A JP S60105243 A JPS60105243 A JP S60105243A
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- section
- wire bonding
- substrate
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/1016—Shape being a cuboid
- H01L2924/10161—Shape being a cuboid with a rectangular active surface
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は位置検出部とボンディング部とを分離し、マル
チ動作ができるようにしたマルチ・チップ用全自動ワイ
ヤボンディング装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a fully automatic wire bonding apparatus for multi-chip in which a position detection section and a bonding section are separated to enable multiple operations.
従来、混成集積回路等のワイヤボンディングでは多数個
の半導体チップが同一基板上にマウントしておるので半
導体チップおよび基板上パターンの位置検出する回数が
増加するため検出時間がワイヤボンディングする時間に
比較し、かなシ多くなシ検出時間を含めた総合ワイヤボ
ンディング時間の増加および装置の実質の稼動率低下と
いう欠点になっていた。本発明は、このような問題を解
決することを目的とする。Conventionally, in wire bonding for hybrid integrated circuits, etc., a large number of semiconductor chips are mounted on the same substrate, which increases the number of times the positions of the semiconductor chips and patterns on the substrate are detected, so the detection time is shorter than the time required for wire bonding. However, the drawbacks are an increase in the total wire bonding time including the long detection time and a decrease in the actual operating rate of the device. The present invention aims to solve such problems.
本発明によれば基板上にマウントされた多数個の半導体
チップと基板上パターンとを自動的にワイヤボンディン
グにて接続する際、あらかじめグログラムした多数個の
半導体チップと基板上ノくターンとの基準ボンディング
位置に基づき、多数個の半導体チップと基板上パターン
とのボンディング位置ずれ量を検出し記憶する位置検出
部と、基板の位置ずれ量を基板上パターンで検出補正す
る機能を有し、上記位置検出部で記憶したボンディング
位置ずれ量を基準ボンディング位置で補正し多数個の半
導体チップと基板上パターンとのワイヤボンディングを
自動的に行うボンディング部とを分離し、位置検出部と
ボンディング部とのマルチ動作ができることを特徴とし
たマルチチップ用全自動ワイヤボンディング装置が得ら
れる。According to the present invention, when automatically connecting a large number of semiconductor chips mounted on a substrate to a pattern on the substrate by wire bonding, a reference is made between a large number of semiconductor chips that have been programmed in advance and a pattern on the substrate. It has a position detection section that detects and stores the amount of bonding positional deviation between a large number of semiconductor chips and the pattern on the substrate based on the bonding position, and a function to detect and correct the amount of positional deviation of the substrate using the pattern on the substrate. The bonding section that corrects the amount of bonding position deviation memorized by the detection section using the reference bonding position and automatically performs wire bonding between multiple semiconductor chips and patterns on the substrate is separated, and the A fully automatic wire bonding device for multi-chip, which is characterized by its operability, is obtained.
以下図面を用いて詳細に説明をする。A detailed explanation will be given below using the drawings.
第1図は、従来の全自動ワイヤボンディング装置の概略
構成を示したものでボンディング部品4を供給するロー
ダ部1と、上記ボンディング部品のボンディングする基
板上パターン(図示せず)および半導体チップ(図示せ
ず)の基準ボンディング位置からの位置ずれ量を位置検
出部2および位置検出へ、ド5で検出した後、位置検出
部と一体的に動作するボンディング部3およびボンディ
ングヘッド6とにより基板パターンおよび半導体チップ
の位置補正し各ボンディングを行い、その後アンローダ
部4に収納する。例えば混成集積回路等の同一基板上に
多数個の半導体チップがマウントされている場合には、
全ての半導体チップの位置検出を完了するまでワイヤボ
ンディングができない次点があった。FIG. 1 shows a schematic configuration of a conventional fully automatic wire bonding apparatus, which includes a loader section 1 that supplies a bonding component 4, a pattern on a substrate (not shown) to which the bonding component is bonded, and a semiconductor chip (not shown). After the amount of positional deviation from the reference bonding position (not shown) is detected by the position detection unit 2 and the position detection unit 5, the bonding unit 3 and bonding head 6, which operate integrally with the position detection unit, detect the substrate pattern and After correcting the position of the semiconductor chip and performing each bonding, the semiconductor chip is stored in the unloader section 4. For example, when multiple semiconductor chips are mounted on the same substrate such as a hybrid integrated circuit,
There was a runner-up in which wire bonding could not be performed until the position detection of all semiconductor chips was completed.
第2図は、従来のワイヤボンディングに要する時間分析
図を示したもので半導体ペレットの数が多くなるとボン
ディング時間t2 に比較し検出時間【1 の占める割
合が多くなり、総合ボンディング時間T1=tt −1
−tz が増加する欠点があった。FIG. 2 shows an analysis of the time required for conventional wire bonding. As the number of semiconductor pellets increases, the proportion of the detection time [1] increases compared to the bonding time t2, and the total bonding time T1 = tt - 1
There was a drawback that -tz increased.
第3図は、本発明による全自動ワイヤボンディング装置
の概略構成図を示したもので従来の全自動ワイヤボンデ
ィング装置に位置検出部2′をさらに追加しボンディン
グ部3とを分離しマルチ動作ができるようにしたもので
、あらかじめプログラムしたボンディング部品4′の基
板上パターンおよび半導体チップの基準ボンディング位
置を位置検出部2′および位置検出ヘッド5′で検出し
その位置ずれ量をメモリに一時記憶させ、さらに位置検
出部と分離しマルチ動作する位置検出部2および位ット
によるボンディング部品4の位置ずれ量を基板上パター
ンの2箇所で検出補正をし、さらに各ワイヤボンディン
グ点の位置補正を位置検出部で検出したボンディング部
品に相当するずれ量で補正を行いさらにボンディング部
3およびボンディングヘッド6によシワイヤボンディン
グを行う。FIG. 3 shows a schematic configuration diagram of a fully automatic wire bonding device according to the present invention. A position detection section 2' is further added to the conventional fully automatic wire bonding device and is separated from the bonding section 3, allowing multi-operation. The position detecting section 2' and the position detecting head 5' detect the pre-programmed pattern on the board of the bonding component 4' and the reference bonding position of the semiconductor chip, and temporarily store the amount of positional deviation in the memory. Furthermore, the position detection unit 2, which is separated from the position detection unit and performs multiple operations, detects and corrects the amount of positional deviation of the bonding component 4 using the position detection unit at two locations on the pattern on the board, and furthermore, the position detection unit 2 performs multiple operations and detects and corrects the positional deviation of the bonding component 4 at two locations on the pattern on the board. Correction is performed using the amount of deviation corresponding to the bonding part detected by the part, and then the bonding part 3 and the bonding head 6 perform wire bonding.
また第4図は本発明によるワイヤボンディングに要する
時間分析図を示したもので、位置検出部とボンディング
部をマルチ動作させることによシ基板パターンおよび半
導体チップの検出時間t1がボンディング時間t2 と
比較し無視できる。Furthermore, FIG. 4 shows an analysis diagram of the time required for wire bonding according to the present invention, in which the detection time t1 of the substrate pattern and semiconductor chip is compared with the bonding time t2 by operating the position detection section and the bonding section in multiple ways. can be ignored.
さらに位置ずれ量の検出時間t3 はtl に比較し非
常に小さいため、総合ボンディング時間T2=t’3+
t2 でで表わされ従来に比べ装置の稼動率を飛躍的に
向上させることができるマルチ嗜チップ用全自動ワイヤ
ボンディング装置を提供するものである。Furthermore, since the detection time t3 of the amount of positional deviation is very small compared to tl, the total bonding time T2=t'3+
The present invention provides a fully automatic wire bonding device for multi-type chips, which is expressed as t2 and can dramatically improve the operating rate of the device compared to the conventional method.
以上本発明について一実施例をあげて説明したがこの発
明にづ(いての位置検出機能等は上記実施例に限定され
るものでなく、本発明についての特許権は特許請求の範
囲に記す全てに及ぶ。Although the present invention has been described above with reference to one embodiment, the position detection function etc. based on this invention are not limited to the above embodiment, and the patent rights related to the present invention are reserved for all claims. It extends to.
第1図は従来の全自動ワイヤボンディング装置の概略構
成の一実施例図、第2図は従来のワイヤボンディングに
要する時間分析図、第3図は、本発明によるマルチ嗜チ
ップ用全自動ワイヤボンディング装置の概略構成の一実
施例図、第4図は本発明によるマルチ・チップ用全自動
ワイヤボンディングに要する時間分析図である。
1・・・・・・ローダ部、2.i、2 ・・・・・・位
置検出部、・・・ボンディングへ、ド、7・・・・・・
アンローダ部。
箔 l 凹
第3 凶
第4vJFig. 1 is an example of a schematic configuration of a conventional fully automatic wire bonding device, Fig. 2 is an analysis diagram of the time required for conventional wire bonding, and Fig. 3 is a fully automatic wire bonding system for multi-chip chips according to the present invention. FIG. 4, which is an embodiment of the schematic configuration of the apparatus, is an analysis diagram of the time required for fully automatic wire bonding for multi-chip according to the present invention. 1...Loader section, 2. i, 2...Position detection section,...to bonding, C, 7...
Unloader section. foil l concave 3rd 4th vJ
Claims (1)
パターンとを自動的にワイヤボンディングにて接続する
際、あらかじめプログラムした多数個の半導体チップと
基板上パターンとの基準ボンディング位置に基づき、多
数個の半導体チップと基板上パターンとのボンディング
位置ずれ量を検出し記憶する位置検出部と、基板の位置
ずれ量を基板上パターンで検出補正する機能を有し、前
記位置検出部で記憶したボンディング位置ずれ量を基準
ボンディング位置で補正し多数個の半導体チップと基板
上パターンとのワイヤボンディングを自動的に行うボン
ディング部とを分離し、位置検出部とボンディング部と
のマルチ動作ができることを特徴としたマルチチップ用
全自動ワイヤボンディング装置。When automatically wire bonding a large number of semiconductor chips mounted on a board to a pattern on the board, a large number of semiconductor chips mounted on a board are connected based on pre-programmed reference bonding positions between the semiconductor chips and the pattern on the board. It has a position detecting section that detects and stores the amount of bonding positional deviation between the semiconductor chip and the pattern on the substrate, and a function of detecting and correcting the amount of positional deviation of the substrate using the pattern on the substrate, and the bonding position stored in the position detecting section. The bonding section, which automatically wire-bonds multiple semiconductor chips to the patterns on the substrate by correcting the amount of deviation at the reference bonding position, is separated, and is characterized by the ability to perform multiple operations with the position detection section and the bonding section. Fully automatic wire bonding equipment for multi-chip.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58213641A JPS60105243A (en) | 1983-11-14 | 1983-11-14 | Fully automatic wire bonding equipment for multichip |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58213641A JPS60105243A (en) | 1983-11-14 | 1983-11-14 | Fully automatic wire bonding equipment for multichip |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60105243A true JPS60105243A (en) | 1985-06-10 |
Family
ID=16642512
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58213641A Pending JPS60105243A (en) | 1983-11-14 | 1983-11-14 | Fully automatic wire bonding equipment for multichip |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60105243A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100629272B1 (en) | 2005-03-11 | 2006-09-29 | 삼성테크윈 주식회사 | wire bonding method |
-
1983
- 1983-11-14 JP JP58213641A patent/JPS60105243A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100629272B1 (en) | 2005-03-11 | 2006-09-29 | 삼성테크윈 주식회사 | wire bonding method |
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