JPS5999770A - Gate turn off thyristor - Google Patents

Abstract

PURPOSE:To reduce the ratching current during turning on time by a method wherein the distance between each divided cathode emitter of GTO is set up not to exceed the diffusion length of minor carrier in a base layer coming into contact with a cathode emitter. CONSTITUTION:A p type emitter 1, a p type base 3 are provided on both sides of an Si wafer to be an n type base 2 while n type cathode emitters 41, 42... divided into multiple numbers are arranged on the base 3 to provided cathode electrodes 51, 52.... Gate electrodes 6 are provided on the surface of the layer 3 encircling those electrodes while an anode electrode is provided on the p-layer 1. Besides, the arrayal gap W on the layer 4 is set up not to exceed the diffusion length of minor carrier on the p-layer 3. At this time, the minor carrier implanted from the n-layer 4 in case of turning on to be diffused laterally and obliquely reach below the adjoining n-layer 4 before they are recoupled to be extinguished to increase the carrier density in the region making turning on easier to reduce the overall ratching current.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to dirt turn-off side risk (hereinafter referred to as GT
(referred to as O), especially Glo, which has a cathode-emitter structure divided into many parts.

[Technical background of the invention and its problems]

GTO is a four-layer semiconductor device that is triggered into conduction by applying a positive potential to the gate electrode and causing a gate current to flow. However, while a normal Cyrisk is turned off by commutating the main current to the commutation circuit, GTO is turned off by applying a negative potential to the gate electrode and passing a negative current pulse. . For this reason, the cathode emitter of the GTO is generally divided into a plurality of parts so as to be easily turned off, and a cathode structure is adopted in which the area of the unit element is reduced.

Especially when trying to operate GTO at high frequency,
In order to reduce the turn-off time, a more finely divided cathode emitter structure □ is required. On the other hand, make the force sword emitter finer □: The more you divide it, the longer the junction length between the cut and the pace increases, and the recombination at that junction increases, and the lean current increases. Therefore, the effective current′
By reducing the force, the latching current at turn-on increases. Here, even if a positive potential is applied to the dart electrode, a gate-on pulse current is passed between the dart and the cathode, and the gate-on pulse current is turned on, and the dart-on pulse current is removed, the thyristor is the minimum anode current that can maintain continuous conduction. Therefore, when dart controlling the silicate, the smaller the latching current is, the more the main current can be controlled from a small current to a large current, so it can be said that the smaller the latching current is, the better the controllability is. However, since the GTO is a self-extinguishing semiconductor element, it is easier to turn off than a general thyristor, but it is difficult to turn on. for example,
In the case of power devices, the latching current is several times higher than the conventional cyrisk.

This means that the minimum controllable current of a circuit using GTO is high, and controllability is poor.

Therefore, a method that can reduce the latching current without impairing other characteristics has been desired.

Conventionally, carrier recombination was suppressed by limiting the number of cathode emitter divisions, shortening the junction length between the cathode emitter and the base, and increasing the carrier lifetime in the carrier lifetime control process. Well, we have been offering a small GTO in the Chingumi style. but,
Although these methods can reduce the latching current at turn-on, the turn-off time becomes longer, resulting in a decrease in the one-turn-off ability.

[Purpose of the invention]

The present invention has been made to solve the above-mentioned drawbacks, and particularly in a GTO having a cathode emitter divided into many parts.
It is an object of the present invention to provide a GTO that makes it possible to reduce the latching current during turn-on without reducing the turn-off ability.

[Summary of the invention]

The GTO according to the present invention is characterized in that the distance between the divided cathode emitters is set to be equal to or less than the minority carrier diffusion length of the base layer in contact with the cathode emitter.

〔Effect of the invention〕

In conventional GTOs, the carriers injected from the cathode emitter to the base during turn-off are not only diffused vertically and directly contribute to turn-on, but also diffused laterally and diagonally and annihilated by recombination. was there. In the present invention, the spacing between the cathode emitters is such that minority carriers diffusing laterally and diagonally reach below the adjacent cathode emitter before recombining and disappearing. As a result, the carriers that reach the area under the adjacent cathode emitter without disappearing increase the carrier density in the cathode emitter region, making it easier to turn on, thereby reducing the overall tingling flow.

Note that the minority carrier diffusion length can be expressed as L-terminal. Here, D is the diffusion constant of minority carriers, and τ is the lifetime of minority carriers. Normally, the base layer on the cathode emitter side is about τ=10μsec, so D=26(1)2
/ Bee, minority carrier diffusion length L = 160μ
m, the spacing W between the cathode emitters may be 160 μm or less.

FIG. 1 shows the relationship between the minority carrier diffusion length, the cathode-emitter distance W, and the latching current.

The latching current is the value when two cathode emitters are combined. From the figure, it can be seen that the values of the latching and latching currents change rapidly when the ratio of W to L approaches 1.

[Embodiments of the invention]

The present invention will be explained in detail below. Figure 2(a).

(b) is a plan view showing the main parts of one embodiment and its A-A'
FIG. In the figure, 1 is a p-type first emitter layer (anode emitter layer), 2 is an n-type first base layer, and 3 is a p-type first emitter layer (anode emitter layer).
is a p-type second base layer, and a plurality of divided n-type second emitter layers (cathode emitter layers) 4 (41°42, . . . ) are arranged on the second base layer 3. It is formed. Each cathode emitter layer 4 has a cathode electrode 5 (5!
, 52°...), a dart electrode 6 is formed on the surface of the second base layer 3 so as to surround this, and an anode electrode 7 is formed on the entire surface of the anode emitter layer 1. There is.

Here, the arrangement interval W of each cathode emitter layer 4 is the second
It is set below the minority carrier diffusion length of the pace layer 3.

This example will be explained using more specific data. Second
An n-type Si wafer with a thickness of 600 μm and a resistivity of 180 Ω is used as the space layer 2, and p-type impurities are first diffused on both sides of the wafer to a depth of 70 μm at a surface concentration of 5×10 cm to form the first emitter layer 1 and the second emitter layer 2. A paste layer 3 is formed. Next, from the surface of the second paste layer, the surface concentration is 4×10 o
An n-type layer of 18 .mu.m thick was formed by diffusion, and this was divided into island shapes using a fluoronitric acid etching solution to form the cathode emitter layer 4. At this time, the cathode electrode z... quotient distance W of the evening layer t
was set to 150 μm. Next, the cathode electrodes 5 and 6 were formed by vapor deposition of aluminum, and the cathode electrodes were assembled by bonding aluminum wires.

The results of this example are shown in FIG.

The horizontal axis represents the number of aggregated cathode emitters, and the vertical axis represents the latching current per one cathode emitter. As is clear from the figure, when W was set to 150 μm, the latching current for one cathode emitter was about 15 mA, but when 30 pieces were assembled, the latching current for each cathode emitter improved to about 4rnA, which is about Z. Yes, it is.

Although the above embodiment + was carried out using a mesa-type cathode emitter structure, it goes without saying that the present invention can be similarly applied to a planar structure.

Further, the arrangement of the cathode emitters may be radial, two-dimensional matrix, or box-like.

, 4. Brief description of the drawings Figure 1 is a diagram for detailed explanation of the present invention, Figure 2 (a
) I (b) is a plan view showing a GTO according to an embodiment of the present invention and its sectional view taken along line A-A', and FIG. 3 is a diagram for explaining the effects of the embodiment.

DESCRIPTION OF SYMBOLS 1... First emitter layer, 2... First paste layer, 3...
...Second base N,' (41r 42 +...)
...Second emitter layer (cathode emitter layer), 5 (5
1+52,...)...Cathode electrode, 6...Dart electrode, 7...Anode electrode.

Figure 1 05 1 1.5 2 Figure 2

Claims (1)

[Claims] A first emitter layer of a first conductivity type, a first paste layer of a second conductivity type, and a second paste layer of a first conductivity type are laminated in this order, and a plurality of divided emitter layers are stacked on the second paste layer. A dirt turn-off silicon risk formed by arranging second emitter layers of two conductivity types, characterized in that the second emitter layers are arranged with a separation distance equal to or less than the minority carrier diffusion length in the second paste layer. Dirt turn-off Sailisk.