JP2866174B2 - Gate turn-off thyristor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a gate turn-off thyristor (hereinafter referred to as GTO), and more particularly to a GTO having a pnipn structure suitable for use in an anode short-circuit type GTO.

[Prior Art] Generally, a GTO is configured to include at least a pnpn4 semiconductor layer. As a device structure capable of reducing power loss generated in the device, a GTO including an n base layer and a p emitter layer is used. With a so-called pnipn structure, a desired breakdown voltage can be obtained with an n-base layer having a smaller thickness than when no buffer layer is provided by providing an n-type buffer layer having a resistance lower than that of the n-base layer. It has been known.

However, when this structure is applied to an anode short-circuit type GTO, there arises a problem that a short-circuit resistance is reduced by a low-resistance buffer layer, and a gate trigger current is increased.

As a method according to the prior art for solving such a problem, as described in JP-A-63-186473,
A method in which the sheet resistance of the buffer layer is set to a predetermined value such that the trigger gate current is reduced and the breakdown voltage is not deteriorated, or disclosed in JP-A-63-265465,
171272 JP, JP-A-1-225359, JP-A-1-31
As described in Japanese Patent No. 8264 or the like, there is known a method of devising a pattern so as to reduce the area ratio of the short-circuit portion occupying the anode side.

[Problem to be Solved by the Invention] In the conventional technology, in a p-npn-structured GTO, a high-resistance n-type base layer is formed to have an ideal thickness (without a buffer layer).
When it approaches (1/2), the base layer of the pnp transistor part becomes thinner, so that the efficiency of transporting holes injected from the p-emitter layer increases and the current amplification rate increases. There is a problem that the withstand capacity is reduced.

That is, an anode short-circuit type GTO having a pnipn structure is:
By adjusting the sheet resistance of the buffer layer or reducing the area ratio of the short-circuit portion as in each of the conventional techniques described above,
Since the hole transport efficiency and the injection efficiency are increased, there is a problem that the above-mentioned problem becomes more prominent.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned problems of the prior art and to provide an anode short-circuit type GTO having a pnipn structure having a small turn-off loss, a large blocking capability, and a small trigger gate current.

[Means for Solving the Problems] According to the present invention, the object is to form an n-type semiconductor layer having a higher resistance than a buffer layer between a buffer layer and a p-emitter layer in a GTO having a pnipn structure. This is achieved by selectively controlling carrier lifetime of the buffer layer and providing a gate electrode for extracting carriers injected into the buffer layer.

[Operation] The means for achieving the object of the present invention can adjust the current amplification factor of the pnp transistor portion without depending on the sheet resistance of the buffer layer. As a result, the present invention can prevent an increase in turn-off loss, a decrease in cut-off tolerance, and the like even when the trigger resistance is reduced by increasing the sheet resistance.

[Example] Hereinafter, an example of a GTO according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a cathode side plan view of a first embodiment of the present invention,
FIG. 2 is a sectional view taken along the line AA 'showing the structure of the element, FIG.
FIG. 4 is a view for explaining an example of the impurity concentration distribution in the vertical direction in FIG. 1 and 2, 1 is a semiconductor substrate, 2 is an n emitter layer, 3 is a p base layer, 4 is an n base layer, 5 is a buffer layer, 6 is an n ⁻ layer, 7 is a p emitter layer, 8 Is a short-circuit layer, 10 is an anode electrode, 20 is a cathode electrode, and 30 is a cathode-side gate electrode.

The cathode side plan view of the anode short-circuit type GTO having the pnipn structure according to the present invention shown in FIG.
This shows 1/4 of TO.

In the first embodiment of the present invention, a circular semiconductor substrate 1 is provided.
A large number of elongated n-emitter layers 2 are arranged in a triple ring radial pattern, and a gate electrode (not shown in FIG. 1) is provided on the p base layer 3 exposed therearound.

In FIG. 2 showing a cross-sectional view taken along the line AA 'of FIG. 1, a semiconductor substrate 1 includes an n-emitter layer 2, a p-base layer 3, a high-resistance n-base layer 4, an n-type buffer layer 5, and n It comprises an n ⁻ layer 6 having a higher resistance than the buffer layer 5, a p emitter layer 7, and an n-type short-circuit layer 8 provided immediately below the n emitter layer 2. The position of the short-circuit layer 8 is
The position is not limited to the illustrated position, and may be at another position.

Further, an anode electrode 10, a cathode electrode 20, and a gate electrode 30 are provided on the exposed surfaces of the p emitter layer 7, the n emitter layer 2, and the p base layer 3, respectively. Although not shown, a passivation film such as a silicon oxide film, a glass film, or a silicon rubber is formed on a surface where the pn junction is exposed.

In the first embodiment of the present invention having a sectional structure as shown in FIG.
It is shown in the figure.

In FIG. 3, n ⁺ , p, i, n, n ⁻ ,
p ⁺ corresponds to the n emitter layer 2, the p base layer 3, the n base layer 4, the buffer layer 5, the n ⁻ layer 6, and the p emitter layer 7, respectively. Among them, the n ⁻ layer (n ⁻ ) has a substantially uniform concentration distribution.

2 and 3, for example, an n-type buffer layer 5 is formed by drive-in after depositing or ion-implanting phosphorus, and an n ⁻ layer 6 is formed.
It can be manufactured by epitaxially growing (n ⁻ ). For forming the n ⁻ layer 6 (n ⁻ ), a known method of directly bonding a silicon wafer may be used.

FIG. 4 shows another example of the impurity concentration distribution in FIG. 2, showing a case where the concentration distribution of the n-type buffer layer 5 is substantially uniform.

Such a buffer layer 5 and the n ⁻ layer 6 can be continuously formed by appropriately adjusting the concentration of a dopant gas by using, for example, an epitaxial growth method.

According to the first embodiment of the present invention having the above-described structure, the magnitude of the short-circuit resistance can be determined by the sheet resistance of the buffer layer 5, so that if the n ⁻ layer 6 is formed thick, The current amplification factor of the pnp transistor portion formed by the p base layer 3 to the p emitter layer 7 can be reduced independently of the resistance.

Thus, the first embodiment of the present invention is different from the buffer layer 5 according to the first embodiment.
Can be increased as long as the withstand voltage can be ensured, so that the short-circuit resistance can be increased, the gate trigger current can be reduced, and the turn-off loss can be reduced and the withstand voltage can be improved. .

FIG. 5 is a sectional view showing the structure of the second embodiment of the present invention, and the reference numerals in FIG. 5 are the same as those in FIG. In the second embodiment of the present invention, selective carrier lifetime control is performed on the buffer layer 5 indicated by oblique lines in the drawing.

In the second embodiment of the present invention, the carrier lifetime control structure can be formed by accelerating protons, helium ions, etc. to an energy that can penetrate into the buffer layer 5 and irradiating it from the anode side or the cathode side. it can. The buffer layer 5 can be manufactured by a conventional method using thermal diffusion.

According to the second embodiment of the present invention having the above structure, even if the sheet resistance of the buffer layer 5 is increased, the holes injected from the p emitter layer 7 into the buffer layer 5 have a carrier lifetime Since the recombination disappears inside the buffer layer 5 where the control is performed, the current amplification factor of the pnp transistor portion can be reduced, whereby the turn-off loss of the GTO can be reduced and the blocking resistance can be improved. .

In the above-described third embodiment of the present invention, the carrier lifetime control is performed by irradiation with protons, helium ions, or the like. However, this control is performed by electron beam irradiation, gamma ray irradiation, heavy metal doping, or the like. It is also possible to use the control method together.

FIG. 6 is an anode side plan view of a third embodiment of the present invention,
7 and 8 are sectional views taken along the line BB 'and CC' of FIG. 6, and FIG. 9 is a view for explaining the driving method of this embodiment. 6 to 8, reference numeral 9 denotes an n-type resistance layer, reference numeral 40 denotes an anode-side gate electrode, and other reference numerals are the same as those in FIGS.

The anode side plan view of the GTO shown in FIG. 6 is 1/4 of the circular GTO as in the case of FIG.

The third embodiment of the present invention is directed to a semiconductor substrate 1 having a circular shape.
A plurality of p-emitter layers 7 are arranged concentrically, an n-type low-resistance layer 9 is exposed therearound, and a gate electrode (not shown) is provided. The pattern on the cathode side is the same as in FIG. 1, and in FIG. 6, a part of the arrangement of the n-emitter layers 2 is indicated by broken lines.

That is, in the third embodiment of the present invention, as shown in FIG. 6, the size of the p emitter layer 7 is set to such an extent that a plurality of n emitter layers 2 are included. Therefore, the area utilization factor of the p emitter layer 7 in this embodiment is sufficiently larger than that of the n emitter layer 2.

BB 'line and C- line in FIG. 6 shown in FIG. 7 and FIG.
The sectional view taken along the line C ′ is illustrated with the cathode surface facing up.

In the third embodiment of the present invention, as shown in FIGS. 7 and 8, the region where the gate electrode 30 on the cathode side between the n-emitter layers 2 is provided is projected to the region on the anode side. A low resistance layer 9 is formed, and an anode side gate electrode 40 is provided on an exposed portion thereof.

Next, a driving method according to a third embodiment of the present invention configured as described above will be described with reference to FIG.

GTO according to a third embodiment of the present invention, by a cathode-side gate signal S _K and the anode-side gate signal S _A, are switched by the gate signal S _K, to reduce the trigger current by the gate signals S _A, and the turn-off Control is performed to reduce the loss.

That is, in the turn-off period B, by opening the space between the anode-side gate electrode 40 and the anode electrode 10 (hereinafter referred to as G _A -A), a state without anode short-circuit, that is, a device without anode short-circuit Therefore, the gate trigger current can be reduced. In periods C and D, the device operates as an anode short-circuited device. In the tail time E, G _A -A
By reverse biasing between the holes, holes injected from the p emitter layer 7 into the buffer layer 5 become
Since it is extracted by 40, the current amplification factor of the pnp transistor portion can be substantially reduced.

As a result, the third embodiment of the present invention described above can reduce the turn-off loss and improve the blocking resistance.

In other periods other than the above-mentioned period, that is, in the blocking state period A, the on-state period C, and the accumulation time period D, control is performed so that G _A -A is short-circuited. Is to be.

Although the three embodiments have been described above, the present invention can also be configured by using these embodiments in combination.

[Effects of the Invention] As described above, according to the present invention, it is possible to reduce the turn-off loss and improve the withstand voltage without increasing the gate trigger current of the anode short-circuit type GTO having the pnipn structure.

[Brief description of the drawings]

FIG. 1 is a plan view of a cathode side according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view taken along the line AA 'showing the structure of the device, and FIGS. FIG. 5 is a view for explaining an example of impurity concentration distribution, FIG. 5 is a sectional view showing a structure of a second embodiment of the present invention, FIG. 6 is an anode side plan view of a third embodiment of the present invention, FIG. FIG. 8 is a sectional view taken along the line BB 'of FIG.
FIG. 9 is a diagram for explaining a driving method of this embodiment. 1 ... semiconductor substrate, 2 ... n emitter layer, 3 ... p base layer, 4 ... n base layer, 5 ... buffer layer, 6 ... n
Layer 7 P emitter layer 8 Short circuit layer 9 N-type resistance layer 10 Anode electrode 20 Cathode electrode 30
…… Cathode side gate electrode, 40 …… Anode side gate electrode.

──────────────────────────────────────────────────の Continuing from the front page (72) Inventor Hideo Honma 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi, Ltd.Hitachi Research Laboratory Co., Ltd. In-house (72) Inventor Kenji Yanagishita 4026 Kuji-cho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (56) References JP-A-62-235782 (JP, A) JP-A-3-171777 (JP, A) JP-A-4-32263 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/332 H01L 29/74-29/749

Claims (6)

(57) [Claims] 1. A semiconductor substrate having at least two pnpn4 layers having two main surfaces, wherein a buffer having a higher impurity concentration than other portions is formed in a portion of an anode-side base layer adjacent to an anode-side emitter layer, In a gate turn-off thyristor in which the buffer layer or a semiconductor layer connected to the buffer layer is partially exposed on one main surface,
A gate turn-off thyristor, wherein the buffer layer has means for reducing a current amplification factor of a pnp transistor portion. 2. The semiconductor device according to claim 1, wherein an exposed portion on one main surface of said buffer layer or a semiconductor layer connected to said buffer layer is electrically connected to an anode electrode. Gate turn-off thyristor. 3. The means for lowering the current amplification factor is provided in a region provided between the buffer layer and the anode-side emitter layer, wherein the buffer has the same conductivity type as the buffer layer and has a substantially uniform impurity concentration. 3. The gate turn-off thyristor according to claim 1, wherein the gate turn-off thyristor is a semiconductor layer having a lower impurity concentration than the layer. 4. The gate according to claim 1, wherein said means for lowering the current amplification factor is a carrier lifetime killer selectively doped in said buffer layer. Turn-off thyristor. 5. A semiconductor substrate having two main surfaces and comprising at least a pnpn4 layer, a buffer having a higher impurity concentration than other portions is formed in a portion of the anode-side base layer adjacent to the anode-side emitter layer, In a gate turn-off thyristor in which the buffer layer or a semiconductor layer connected to the buffer layer is partially exposed on one main surface,
In the area where the anode side emitter layer is projected to the cathode side,
A plurality of cathode-side emitter layers divided into strips are formed, a low-resistance layer connected to the buffer layer is formed in a region where a region between the cathode and the emitter layer is projected to the anode side, and a pnp transistor portion is formed. A gate turn-off thyristor, wherein a gate electrode is provided on an exposed portion of one main surface of the low-resistance layer to reduce a current amplification factor. 6. The method according to claim 1, wherein a gap between the gate electrode and the anode electrode is
6. The gate turn-off thyristor according to claim 5, wherein the gate turn-off thyristor is driven so as to be short-circuited during an opening, blocking state, on-state and turn-off accumulation time upon trigger, and reverse-biased during a tail time.