JPS59201467A - Gate turn off thyristor - Google Patents

Abstract

PURPOSE:To enable high frequency action without causing the increase of chips in size by a method wherein the penetration regions for the second base region for current control are distributed in matrix form in the second emitter layer serving as a current path during conduction. CONSTITUTION:A P-emitter region 22 is formed on the back surface of an N type semiconductor substrate 20 as the first emitter region, and a P-base region 23 on the surface of the substrate 20 as the second base region, respectively. The N type region of the substrate 20 sandwiched by these P type regions is made as the N-base region 21 serving as the first base region. Next, N-emitter layers 24 are formed in the upper surface of the region 23 as the second emitter region. The titled device of such a construction enables to make the plane area of the layer 24 where a large current flow sufficiently larger than that of the penetration region 23C. Therefore, even when the distribution density of the region 23C is increased for the purpose of high frequency action, the large decrease of controllable current and the increase of chip size are not caused.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a guttane-on thyristor.
In particular, it relates to those requiring high frequency operation.

[Technical background of the invention]

When a conventional dart turn-or-thyristor (hereinafter referred to as GTO) increases the conduction current (anode current) fc in the on state, it does not immediately turn off to the off state even when a negative bias is applied to the gate, causing commutation failure. Start waking up. This means that even if a negative bias voltage is applied to the GTOCI dart, the G
This is because carriers sufficient to keep TO in the on state remain unabsorbed.

For this reason, a GTO having a structure as shown in FIG. 1 and FIG. M2 has been developed for the purpose of increasing the current that can be controlled by dart (maximum controllable current).

In FIG. 1, 11 is an N base region, 12 is a P emitter region which becomes an anode region, and 13 is a P base region which becomes a dirt. Layers 14 are formed at regular intervals, and an anode electrode 15 is deposited on the back surface of the P emitter layer 12. Figure 2 shows an example of the cathode and dirt electrode wiring patterns for the device in Figure 1.
3a is a dart opening where the comb-shaped dart electrode 13b is connected to the P pace region 13 (J), and 14h is a cathode opening where the comb-shaped cathode electrode 14b is connected to the n emitter region 14. In the structure shown in FIGS. 1 and 2, the N emitter layer 14 is provided in a strip shape within the P base region 13, so that carriers in the N emitter layer 14 are removed from the surrounding P base region 13 during turn-off. This is to prevent residual carriers from remaining near the center of the N emitter layer 14.

[Problems with background technology]

In order to shorten the turn-off time in the above-mentioned device, a method is used to narrow the width of the strip of the N emitter layer 14, but there is a manufacturing process limit to narrowing it, and furthermore, the width of the strip of the N emitter layer 14 is limited. Since the layer 14 serves as a current path for the current flowing during turn-on, the area cannot be reduced if a controllable current above a certain level is to be obtained.

Furthermore, when a reverse bias voltage is applied to the P base region 13, the carriers immediately below the center of the N emitter layer 14, indicated by 16 in FIG.
The narrower the width of the N emitter layer 14, the more irregular the distribution of carriers in the length direction of the N emitter layer 14 becomes.

For this reason, there is a drawback that local current concentration tends to occur in areas where the carrier distribution is uneven.

For example, using GTO in the power supply section of a TV, etc., 63kHz
(4 times the fundamental frequency of television, 15.75 kHz) was not possible.

Furthermore, in the N emitter layer structure divided into strips as described above, even if the number of divisions is increased for the purpose of high frequency operation, the area efficiency is poor due to the arrangement of the dart electrodes 13b.
[Objective of the Invention] This invention was made in view of the above points, and it is possible to increase the frequency of, for example, 63 kHz or more without increasing the chip size or reducing the controllable current. The present invention aims to provide a dirt turn-off thyristor capable of high frequency operation.

[Summary of the invention]

That is, in the dirt turn or thyristor according to the present invention, the first emitter region of one conductivity type to which the first electrode is connected is formed on the back side of the semiconductor substrate of the other conductivity type, and the first emitter region of the first conductivity type is formed on the back side of the semiconductor substrate of the other conductivity type. Second base regions of one conductivity type to which the electrodes are connected are respectively formed, and a region of the other conductivity type of the substrate sandwiched between the first emitter region and the second base region is defined as the first base region. Then, by introducing impurities of the other conductivity type onto the second base region using, for example, an island-shaped mask (silicon oxide film) arranged in a matrix, the second electrode is connected to the other conductivity type. A second emitter region is formed, and as a result, the shape of the second base region is such that the second base region has a number of columnar through-holes arranged in a matrix having a common bottom and reaching the upper surface of the second emitter layer. This makes it possible to perform effective dart turn-off in these penetration areas.

[Embodiments of the invention]

An embodiment of Jin's invention will be described below with reference to the drawings. In FIG. 3, like the conventional GTO, an N-type semiconductor substrate 2
P-type impurities are introduced into the semiconductor substrate 20, and a P emitter region 22 is formed as a first emitter region on the back surface of the semiconductor substrate 20, and a P base region 23 is formed as a second base region on the front surface of the semiconductor substrate 20. The N type region of the semiconductor substrate 20 sandwiched between the type regions is defined as an N base region 21 serving as a first base region. Next, as shown at 26 in FIG. 3, a silicon oxide film having a portion where island-shaped silicon oxide films are arranged in a matrix is placed on the upper surface of the P base region 23 on the substrate 200.
Form on the surface. (Normally, a silicon oxide film is also formed on the back surface of the substrate 200 as a mask for preventing impurity diffusion, but this is omitted in ζ.) Next, the N-type impurity is selectively diffused, and as shown in FIG. N as the emitter region of
An emitter layer 24 is formed.

After this, although not shown, the P base region 23 of the substrate 2o and the N
A mother tsusipation film is formed on the PN junction with the base region 20, and an insulating film such as a silicon oxide film having contact holes is formed on the entire surface of the substrate 20 to form the P base region 23 and the N emitter, respectively. A dart electrode and a candor electrode are formed to connect to layer 24. Further, an anode electrode is also formed on the entire back surface of the substrate 2o.

FIG. 5 is a sectional view schematically showing the internal structure of the GTO formed as described above. As shown in the figure, the P base region 23 has columnar through regions arranged in a matrix and connected at the bottom, and the through regions 23c of the P base region 23 extend vertically through the N emitter layer 24. It penetrates through. That is, in the conventional GTO, the N emitter layer is divided into strips, but in this embodiment, the N emitter layer 24 is connected as one piece. Although not shown, the P base region 23 is connected to a dart electrode G, and a cando electrode K is drawn out to the N emitter layer 24 through a contact hole in an insulating film 27 such as a silicon oxide film or a padding film. Emitter layer 2
An anode electrode A is drawn out from 2.

FIG. 6 is a diagram showing the arrangement of the through regions 23C that pass through the N emitter layer 24, as seen from the top surface of the substrate 20. Considering the case where a reverse bias voltage is applied to the P base region 23 of the GTO, carriers in the on state
It is being pulled out from around c. ＠SHIU When looking at the 94 penetration regions 23a as one unit area (unit cell), by appropriately setting the distances between the row direction spacing t1 and the column direction spacing t of the penetration regions 23a, a certain distance can be achieved. Under the dirt negative bias condition, the on region (carrier residual region) of the N emitter 24 disappears.

1 in Figure 6! =1. In this case, the carriers in the N emitter layer 24 can be drawn out most evenly. The circle indicated by the broken line in the figure is one penetration region 23 when the residual carrier in one unit cell is completely extracted.
c indicates the range from which the carrier is pulled out. Among the carriers in the N emitter layer 24 during dart negative bias, those existing near the central point P in one unit cell are extracted last, but when the carriers at point P are extracted, they penetrate through four locations. An electric field acts from region 23c. Therefore, even if the electric field distribution in one penetration region 23c is uneven due to crystal defects, for example, the electric fields from the other three penetration regions 23c act, so that the dispersion of the electric field within the unit cell can be substantially reduced. can be reduced to

FIG. 7 shows a cando electrode 24 connected to the N emitter layer 24.
3 shows an example of a planar arrangement of a dirt electrode 23b connected to the P base region 23 and its contact hole 24a, and a dirt electrode 23b connected to the P base region 23 and its contact hole 23a.

[Effects of the Invention] In the GTO shown in FIG. 4 or FIG. 5, the P base region 230 penetrating regions 23a for current control are distributed in a matrix in the N emitter layer 24, which becomes a current path during energization. The planar area of the N emitter layer 24 through which a large current flows can be made sufficiently larger than that of the through region 23c.

Therefore, even if the distribution density of the through-hole region 23c is increased for the purpose of high-frequency operation, there will be no significant decrease in controllable current and no increase in chip size.
Since there is no need to forcibly make the shape of the emitter layer thinner, the actual design of the canned electrode 24b+dart electrode 23b is also easier than in the conventional case. Furthermore, as described above, by distributing a large number of through regions 23c in the N emitter layer 24, it is possible to reduce electrical variations in the N emitter layer 24 due to crystal defects, etc., so that local current concentration at turn-off can be reduced. can be alleviated.

When a GTO having a matrix-like penetration region 23c equally spaced as shown in FIG. 5 was manufactured in the above manner,
By realizing a GTO that can operate at 63 kHz under the same conditions as a conventional GTO, the power consumption according to the present invention can be reduced. When this flexible GTO is used in a power supply circuit or the like, it is extremely beneficial as it allows the transformer coil to be made more compact and power consumption to be reduced.

In addition, in the above embodiment, the penetrating region 23 of the P base region 23
Although the cross-sectional shape of c is square, it is not limited to square, and may be circular, polygonal, etc., for example. Alternatively, the GTO may be constructed by completely reversing the conductivity type of each region. In this case, the polarity of the current and voltage at each part is opposite to that of the above embodiment.

As described above, according to the present invention, it is possible to provide a dirt turn-off thyristor capable of high frequency operation without increasing the chip size or reducing the controllable current.

[Brief explanation of drawings]

Fig. 1 is a perspective view illustrating the structure of a conventional GTO, Fig. 2 is a plan view showing an example of an electrode pattern of a conventional GTO, and Figs. Perspective view explaining turn-or-sail risk in order of manufacturing process, No. 5
FIG. 6 is a cross-sectional view illustrating the structure of a dirt turn off site according to an embodiment of the present invention, FIG. 6 is a plan view of a partial area of FIG. 5, and FIG. It is a top view which shows an example of the electrode pattern of a risk. 21...N base region, 22...P emitter region,
23...P base region, 23c...penetrating region, 24
-...N emitter region, 26... silicon oxide film.

Claims (1)

[Claims] A first emitter region of one conductivity type with a first electrode formed on the back surface, a first base region of the other conductivity type formed on the first emitter region, and a dart electrode formed on the first paste region. The connected second base region of one conductivity type and the base region have a plurality of column-shaped through regions arranged in a matrix that reach the upper surface of the second emitter region formed thereon. Ri-
Turn-off thyristor.