JPS59201467A - Gate turn off thyristor - Google Patents

Gate turn off thyristor

Info

Publication number
JPS59201467A
JPS59201467A JP7645083A JP7645083A JPS59201467A JP S59201467 A JPS59201467 A JP S59201467A JP 7645083 A JP7645083 A JP 7645083A JP 7645083 A JP7645083 A JP 7645083A JP S59201467 A JPS59201467 A JP S59201467A
Authority
JP
Japan
Prior art keywords
region
base region
emitter
emitter layer
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7645083A
Other languages
Japanese (ja)
Inventor
Minoru Kato
実 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP7645083A priority Critical patent/JPS59201467A/en
Priority to EP84302855A priority patent/EP0130669A1/en
Publication of JPS59201467A publication Critical patent/JPS59201467A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/74Thyristor-type devices, e.g. having four-zone regenerative action

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To enable high frequency action without causing the increase of chips in size by a method wherein the penetration regions for the second base region for current control are distributed in matrix form in the second emitter layer serving as a current path during conduction. CONSTITUTION:A P-emitter region 22 is formed on the back surface of an N type semiconductor substrate 20 as the first emitter region, and a P-base region 23 on the surface of the substrate 20 as the second base region, respectively. The N type region of the substrate 20 sandwiched by these P type regions is made as the N-base region 21 serving as the first base region. Next, N-emitter layers 24 are formed in the upper surface of the region 23 as the second emitter region. The titled device of such a construction enables to make the plane area of the layer 24 where a large current flow sufficiently larger than that of the penetration region 23C. Therefore, even when the distribution density of the region 23C is increased for the purpose of high frequency action, the large decrease of controllable current and the increase of chip size are not caused.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明はグートタンオンサイリスタに関するもので、
特に高周波動作の要求されるものに関する。
[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a guttane-on thyristor.
In particular, it relates to those requiring high frequency operation.

〔発明の技術的背景〕[Technical background of the invention]

従来のダートターンオアサイリスタ(以下GTOと称す
)はオン状態における通電電流(アノード電流)fc大
きくしてゆくと、ゲートに負のバイアスを施しても直ち
にオフ状態にターンオフせず、転流失敗を起こすように
なる。これはGTOCIダートに負のバイアス電圧を印
加してもカソードとなるNエミツタ層の中心領域に、G
TOをオン状態に保持するに足るキャリアが吸収されず
に残留しているためである。
When a conventional dart turn-or-thyristor (hereinafter referred to as GTO) increases the conduction current (anode current) fc in the on state, it does not immediately turn off to the off state even when a negative bias is applied to the gate, causing commutation failure. Start waking up. This means that even if a negative bias voltage is applied to the GTOCI dart, the G
This is because carriers sufficient to keep TO in the on state remain unabsorbed.

このため、ダートによシ制御可能な通電電流(最大可制
御電流)を大きくすることを目的として、第1図および
M2図に示すような構造のGTOが開発されている。
For this reason, a GTO having a structure as shown in FIG. 1 and FIG. M2 has been developed for the purpose of increasing the current that can be controlled by dart (maximum controllable current).

第1図において、11はNベース領域、12はアノード
領域となるPエミッタ領域、13はダートとなるPベー
ス領域で、このPベース領域13内にはカソード領域と
して検数の短冊状のNエミツタ層14が等間隔に形成さ
れ、Pエミッタ層12の裏面にはアノード電極15が蒸
着形成されている。第2図は、第1図の装置のカソード
およびダート電極配線のパターン例を示したもので、1
3aはPペース領域13にくし形のダート電極13bが
接続するダート開口部であJ)、14hはnエミッタ領
域14にくし形のカソード電極14bが接続するカソー
ド開口部を示すものである。上記第1図および第2図に
示すものは、Nエミツタ層14をPベース領域13内に
短冊状に設けることによシ、ターンオフ時にNエミツタ
層14内のキャリアを周囲のPベース領域13から吸収
し、残留キャリアがNエミツタ層14の中央部付近に残
シにくくしようとするものである。
In FIG. 1, 11 is an N base region, 12 is a P emitter region which becomes an anode region, and 13 is a P base region which becomes a dirt. Layers 14 are formed at regular intervals, and an anode electrode 15 is deposited on the back surface of the P emitter layer 12. Figure 2 shows an example of the cathode and dirt electrode wiring patterns for the device in Figure 1.
3a is a dart opening where the comb-shaped dart electrode 13b is connected to the P pace region 13 (J), and 14h is a cathode opening where the comb-shaped cathode electrode 14b is connected to the n emitter region 14. In the structure shown in FIGS. 1 and 2, the N emitter layer 14 is provided in a strip shape within the P base region 13, so that carriers in the N emitter layer 14 are removed from the surrounding P base region 13 during turn-off. This is to prevent residual carriers from remaining near the center of the N emitter layer 14.

〔背景技術の問題点〕[Problems with background technology]

上記のような装置でターンオフ時間を短縮するためには
Nエミツタ層14の短冊の幅を狭くする手法がとられる
が、狭くするにも製造ノロセス上の限界があシ、さらに
、Nエミ、り層14はターンオン時には通電電流の電流
路となるため、ある一定以上の可制御電流を得ようとす
る場合には面積を小さくすることができない。
In order to shorten the turn-off time in the above-mentioned device, a method is used to narrow the width of the strip of the N emitter layer 14, but there is a manufacturing process limit to narrowing it, and furthermore, the width of the strip of the N emitter layer 14 is limited. Since the layer 14 serves as a current path for the current flowing during turn-on, the area cannot be reduced if a controllable current above a certain level is to be obtained.

しかも、Pベース領域13に逆バイアス電圧を印加した
場合第1図の16で示すNエミツタ層14の中央部の真
下のキャリアが最後に吸収されるが、Nエミツタ層14
の幅を狭くする程、逆バイアス時のNエミツタ層14内
のその長さ方向に存在するキャリアの分布が不揃いにな
る。
Furthermore, when a reverse bias voltage is applied to the P base region 13, the carriers immediately below the center of the N emitter layer 14, indicated by 16 in FIG.
The narrower the width of the N emitter layer 14, the more irregular the distribution of carriers in the length direction of the N emitter layer 14 becomes.

このため、キャリア分布の不揃いな部分で極部的な電流
集中が生じやすくなる欠点があった。
For this reason, there is a drawback that local current concentration tends to occur in areas where the carrier distribution is uneven.

例えばテレビの電源部等にGTOを用い、63kHz 
(テレビの基本周波数的15.75 kHzの4倍)で
動作させることは不可能であった。
For example, using GTO in the power supply section of a TV, etc., 63kHz
(4 times the fundamental frequency of television, 15.75 kHz) was not possible.

また、上記のような短冊状の分割されたNエミツタ層構
造では、高周波動作を目的として分割数を増してゆくに
も、ダート電極13bの配置の関係上面積効率が悪く、
チップサイズが大きくなる欠点があった◎ 〔発明の目的〕 この発明は上記のような点に鑑みなされたもので、チッ
プサイズの大型化や可制御電流の低下を招くことなく例
えば63 kHz以上の高周波動作が可能なダートター
ンオフサイリスタを提供しようとするものである。
Furthermore, in the N emitter layer structure divided into strips as described above, even if the number of divisions is increased for the purpose of high frequency operation, the area efficiency is poor due to the arrangement of the dart electrodes 13b.
[Objective of the Invention] This invention was made in view of the above points, and it is possible to increase the frequency of, for example, 63 kHz or more without increasing the chip size or reducing the controllable current. The present invention aims to provide a dirt turn-off thyristor capable of high frequency operation.

〔発明の概要〕[Summary of the invention]

すなわちこの発明に係るダートターンオアサイリスタで
は、第1電極の接続される一方導電型の第1エミツタ領
域を他方導電型の半導体基板の裏面側に形成し、上記半
導体基板の表面側にr−)電極の接続される一方導電型
の第2ベース領域をそれぞれ形成し、これらの第1エミ
ツタ領域および第2ベース領域で挾まれた基板の他方導
電型領域を第1ベース領域とする。そして引き続き上記
第2ベース領域上に例えばマトリクス状忙配列した島状
のマスク(シリコン酸化膜)を用いて他方導電型の不純
物を導入することによシ第2電極が接続される他方導電
型の第2エミツタ領域を形成し、その結果上記第2ベー
ス領域の形状を、底部が共通で上記第2エミッタ層の上
表面にまで達するマトリクス状に配列した柱状の戸数の
貫通領域を有するようなものとし、これら貫通領域によ
シ効果的なダートターンオフを行なえるようにしたもの
である。
That is, in the dirt turn or thyristor according to the present invention, the first emitter region of one conductivity type to which the first electrode is connected is formed on the back side of the semiconductor substrate of the other conductivity type, and the first emitter region of the first conductivity type is formed on the back side of the semiconductor substrate of the other conductivity type. Second base regions of one conductivity type to which the electrodes are connected are respectively formed, and a region of the other conductivity type of the substrate sandwiched between the first emitter region and the second base region is defined as the first base region. Then, by introducing impurities of the other conductivity type onto the second base region using, for example, an island-shaped mask (silicon oxide film) arranged in a matrix, the second electrode is connected to the other conductivity type. A second emitter region is formed, and as a result, the shape of the second base region is such that the second base region has a number of columnar through-holes arranged in a matrix having a common bottom and reaching the upper surface of the second emitter layer. This makes it possible to perform effective dart turn-off in these penetration areas.

〔発明の実施例〕[Embodiments of the invention]

以下図面を参照して仁の発明の一実施物を説明する。第
3図において従来のGTOと同様にN型の半導体基板2
0にP型の不純物を導入し、半導体基板20の裏面に第
1エミツタ領域としてPエミッタ領域22、半導体基板
20の表面に第2ベース領域としでPベース領域23を
それぞれ形成し、これらのP型領域で挾まれた半導体基
板20のN型領域を第1ベース領域となるNベース領域
21とする。次に第3図の26で示すよう々、Pベース
領域23の上面に島状のシリコン酸化膜がマトリクス状
に配列した部分を有するシリコン酸化膜を、基板200
表面に形成する。(なお、通常は基板200裏面にも不
純物拡散防止用のマスクとしてシリコン酸化膜が形成さ
れるがとζでは省略する。)次いでN型不純物を選択拡
散し、第4図に示すように第2のエミッタ領域としてN
エミツタ層24を形成する。
An embodiment of Jin's invention will be described below with reference to the drawings. In FIG. 3, like the conventional GTO, an N-type semiconductor substrate 2
P-type impurities are introduced into the semiconductor substrate 20, and a P emitter region 22 is formed as a first emitter region on the back surface of the semiconductor substrate 20, and a P base region 23 is formed as a second base region on the front surface of the semiconductor substrate 20. The N type region of the semiconductor substrate 20 sandwiched between the type regions is defined as an N base region 21 serving as a first base region. Next, as shown at 26 in FIG. 3, a silicon oxide film having a portion where island-shaped silicon oxide films are arranged in a matrix is placed on the upper surface of the P base region 23 on the substrate 200.
Form on the surface. (Normally, a silicon oxide film is also formed on the back surface of the substrate 200 as a mask for preventing impurity diffusion, but this is omitted in ζ.) Next, the N-type impurity is selectively diffused, and as shown in FIG. N as the emitter region of
An emitter layer 24 is formed.

この後、図示しないが基板2oのPベース領域23とN
ベース領域2ノとのPN接合部上に・母ツシペーション
膜を形成するとともに、基板20上の全面にコンタクト
ホールを有するシリコン酸化膜などの絶縁膜を形成して
、それぞれPベース領域23およびNエミツタ層24に
接続するダート電極およびカンード電極を形成する。ま
た、基板2oの裏面にもアノード電極を全面に形成する
After this, although not shown, the P base region 23 of the substrate 2o and the N
A mother tsusipation film is formed on the PN junction with the base region 20, and an insulating film such as a silicon oxide film having contact holes is formed on the entire surface of the substrate 20 to form the P base region 23 and the N emitter, respectively. A dart electrode and a candor electrode are formed to connect to layer 24. Further, an anode electrode is also formed on the entire back surface of the substrate 2o.

第5図は以上のようにして形成されたGTOの内部構造
を模式的に示す断面図である。図のように、Pベース領
域23は、結果としてマトリクス状に配列し底部におい
て連結した柱状の貫通領域を有しておシ、このPベース
領域23の貫通領域23cがNエミツタ層24を垂直方
向に貫ぬいている。すなわち、従来のGTOではNエミ
ツタ層が短冊状に分割されていたが本実施例のものでは
、Nエミツタ層24が一体に連結した構造となる。上記
のPベース領域23は図示しないがダート電極Gが接続
され、Nエミツタ層24にはシリコン酸化膜やパッジベ
ージ目ン膜などの絶縁膜27におけるコンタクトホール
を介してカンード電極Kが引き出され、Pエミッタ層2
2からはアノード電極Aが引き出される。
FIG. 5 is a sectional view schematically showing the internal structure of the GTO formed as described above. As shown in the figure, the P base region 23 has columnar through regions arranged in a matrix and connected at the bottom, and the through regions 23c of the P base region 23 extend vertically through the N emitter layer 24. It penetrates through. That is, in the conventional GTO, the N emitter layer is divided into strips, but in this embodiment, the N emitter layer 24 is connected as one piece. Although not shown, the P base region 23 is connected to a dart electrode G, and a cando electrode K is drawn out to the N emitter layer 24 through a contact hole in an insulating film 27 such as a silicon oxide film or a padding film. Emitter layer 2
An anode electrode A is drawn out from 2.

第6図はNエミツタ層24を貰ぬく貫通領域23Cの配
列状態を基板20上面よp見た図である。GTOのPベ
ース領域23に逆バイアス電圧が印加された場合につい
て考えると、オン状態にあるキャリアは各貫通領域23
cの周囲から引き抜かれてゆく。@シ合94個の貫通領
域23aを一単位の領域(単位胞)として見ると、貫通
領域23aの行方向の間隔t1 と列方向の間隔t、の
距離を適当に設定することにより、一定のダート負バイ
アス条件でNエミッタ24のオン領域(キャリア残留領
域)が消失する。
FIG. 6 is a diagram showing the arrangement of the through regions 23C that pass through the N emitter layer 24, as seen from the top surface of the substrate 20. Considering the case where a reverse bias voltage is applied to the P base region 23 of the GTO, carriers in the on state
It is being pulled out from around c. @SHIU When looking at the 94 penetration regions 23a as one unit area (unit cell), by appropriately setting the distances between the row direction spacing t1 and the column direction spacing t of the penetration regions 23a, a certain distance can be achieved. Under the dirt negative bias condition, the on region (carrier residual region) of the N emitter 24 disappears.

第6図では1! =1.の場合を示しであるが、この場
合には最も均等にNエミツタ層24内のキャリアを引き
抜くことができる。図の破線に示す円は一単位胞内の残
留キャリアを完全に引き抜く際の、1つの貫通領域23
cがキャリアを引き抜く範囲を示したものである。ダー
ト負バイアス時のNエミツタ層24内のキャリアは一単
位胞内の中央部P点付近に存在するものが最後に引き抜
かれることになるが、P点のキャリアが引き抜かれる際
は4ケ所の貫通領域23cから電界が作用する。従って
結晶欠陥などによシ例えばある1つの貫通領域23cの
電界分布が不揃いであったとしても他の3ケ所の貫通領
域23cからの電界が作用するため、単位胞内の電界の
ばらつきを実質的に低減させることができる。
1 in Figure 6! =1. In this case, the carriers in the N emitter layer 24 can be drawn out most evenly. The circle indicated by the broken line in the figure is one penetration region 23 when the residual carrier in one unit cell is completely extracted.
c indicates the range from which the carrier is pulled out. Among the carriers in the N emitter layer 24 during dart negative bias, those existing near the central point P in one unit cell are extracted last, but when the carriers at point P are extracted, they penetrate through four locations. An electric field acts from region 23c. Therefore, even if the electric field distribution in one penetration region 23c is uneven due to crystal defects, for example, the electric fields from the other three penetration regions 23c act, so that the dispersion of the electric field within the unit cell can be substantially reduced. can be reduced to

第7図はNエミツタ層24に接続するカンード電極24
bおよびそのコンタクトホール24aと、Pベース領域
23に接続するダート電極23bおよびそのコンタクト
ホール23aの平面配置例を示したものである。
FIG. 7 shows a cando electrode 24 connected to the N emitter layer 24.
3 shows an example of a planar arrangement of a dirt electrode 23b connected to the P base region 23 and its contact hole 24a, and a dirt electrode 23b connected to the P base region 23 and its contact hole 23a.

〔発明の効果〕 第4図或いは第5図に示すGTOでは、通電時の電流路
となるNエミツタ層24にマトリクス状に電流制御用の
Pベース領域230貫通領域23aが分布しているため
、本来大電流の流れるNエミツタ層24の平面面積を貫
通領域23cに比らべ充分に大きくすることができる。
[Effects of the Invention] In the GTO shown in FIG. 4 or FIG. 5, the P base region 230 penetrating regions 23a for current control are distributed in a matrix in the N emitter layer 24, which becomes a current path during energization. The planar area of the N emitter layer 24 through which a large current flows can be made sufficiently larger than that of the through region 23c.

従って、高周波動作を目的として貫通領域23cの分布
密度を上げても可制御電流の大幅な低下およびチップサ
イズの大型化を招くこともなく、加えて従来のようにN
エミツタ層の形状を無理に細くする必要がないため、実
際上のカンード電極24b+ダート電極23bの設計も
従来のものよりも容易となった。さらに、前述したよう
に多数の貫通領域23cをNエミツタ層24内に分布さ
せることによシ結晶欠陥などによるNエミツタ層24内
の電気的ばらつきを低減できるため、ターンオフ時の極
部的電流集中を緩和できる。
Therefore, even if the distribution density of the through-hole region 23c is increased for the purpose of high-frequency operation, there will be no significant decrease in controllable current and no increase in chip size.
Since there is no need to forcibly make the shape of the emitter layer thinner, the actual design of the canned electrode 24b+dart electrode 23b is also easier than in the conventional case. Furthermore, as described above, by distributing a large number of through regions 23c in the N emitter layer 24, it is possible to reduce electrical variations in the N emitter layer 24 due to crystal defects, etc., so that local current concentration at turn-off can be reduced. can be alleviated.

以上のようにして、第5図のような等間隔のマトリクス
状の貫通領域23cを有するGTOを製造したところ、
従来のGTOと同一条件下で63 ’kHzで動作可能
なGTOを実現することかでン 消費電力     −゛、本発明によるものでは駄酢蕃
妾捉低減させることができた。このよりなGTOを電源
回路等に使用した場合にはトランスコイルのコンパクト
化および消費電力の低減が可能となシ極めて有益なもの
である。
When a GTO having a matrix-like penetration region 23c equally spaced as shown in FIG. 5 was manufactured in the above manner,
By realizing a GTO that can operate at 63 kHz under the same conditions as a conventional GTO, the power consumption according to the present invention can be reduced. When this flexible GTO is used in a power supply circuit or the like, it is extremely beneficial as it allows the transformer coil to be made more compact and power consumption to be reduced.

なお、上記実施例ではPベース領域23の貫通領域23
cの断面形状を正方形としたが、これは正方形に限らず
例えば円形、多角形などでもよい。また各領域の導電型
を全く逆にしてGTOを構成してもよい。との場合の各
部の電流電圧の極性は上記実施例のものとそれぞれ逆に
なる。
In addition, in the above embodiment, the penetrating region 23 of the P base region 23
Although the cross-sectional shape of c is square, it is not limited to square, and may be circular, polygonal, etc., for example. Alternatively, the GTO may be constructed by completely reversing the conductivity type of each region. In this case, the polarity of the current and voltage at each part is opposite to that of the above embodiment.

以上のように本発明によればチップサイズの大型化や可
制御電流の低下を招くことなく高周波動作が可能なダー
トターンオフサイリスタを提供することができる。
As described above, according to the present invention, it is possible to provide a dirt turn-off thyristor capable of high frequency operation without increasing the chip size or reducing the controllable current.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のGTOの構造を説明する斜視図、第2図
は従来のGTOの電極パターン例を示す平面図、第3図
および第4図は本う6明の一実施例に係わるダートター
ンオアサイリスクを製造過程順に説明する斜視図、第5
図は本発明の一実施例に係るダートターンオアサイリス
クの構造を説明する断面図、第6図は第5図の一部領域
の平面図、第7図は本発明によるりゞ−トターンオフサ
イリスクの電極パターンの一例を示す平面図である。 21・・・Nベース領域、22・・・Pエミッタ領域、
23・・・Pベース領域、23c・・・貫通領域、24
−・・Nエミッタ領域、26・・・シリコン酸化膜。
Fig. 1 is a perspective view illustrating the structure of a conventional GTO, Fig. 2 is a plan view showing an example of an electrode pattern of a conventional GTO, and Figs. Perspective view explaining turn-or-sail risk in order of manufacturing process, No. 5
FIG. 6 is a cross-sectional view illustrating the structure of a dirt turn off site according to an embodiment of the present invention, FIG. 6 is a plan view of a partial area of FIG. 5, and FIG. It is a top view which shows an example of the electrode pattern of a risk. 21...N base region, 22...P emitter region,
23...P base region, 23c...penetrating region, 24
-...N emitter region, 26... silicon oxide film.

Claims (1)

【特許請求の範囲】[Claims] 裏面に第1電極の形成された一方導電型の第1エミツタ
領域と、この第1エミツタ領域上に形成された他方導電
型の第1ベース領域と、この第1ペース領域上に形成さ
れダート電極の接続された一方導電型の第2ベース領域
と、上記−ス領域は、その上部に形成された第2エミツ
タ領域の上表面にまで達するマトリクス状に配置された
柱状の複数の貫通領域を有することを特徴とするり゛−
トターンオフサイリスタ。
A first emitter region of one conductivity type with a first electrode formed on the back surface, a first base region of the other conductivity type formed on the first emitter region, and a dart electrode formed on the first paste region. The connected second base region of one conductivity type and the base region have a plurality of column-shaped through regions arranged in a matrix that reach the upper surface of the second emitter region formed thereon. Ri-
Turn-off thyristor.
JP7645083A 1983-04-30 1983-04-30 Gate turn off thyristor Pending JPS59201467A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP7645083A JPS59201467A (en) 1983-04-30 1983-04-30 Gate turn off thyristor
EP84302855A EP0130669A1 (en) 1983-04-30 1984-04-27 Gate turn off thyristor with mesh cathode structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7645083A JPS59201467A (en) 1983-04-30 1983-04-30 Gate turn off thyristor

Publications (1)

Publication Number Publication Date
JPS59201467A true JPS59201467A (en) 1984-11-15

Family

ID=13605485

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7645083A Pending JPS59201467A (en) 1983-04-30 1983-04-30 Gate turn off thyristor

Country Status (1)

Country Link
JP (1) JPS59201467A (en)

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