JPS63209167A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS63209167A JPS63209167A JP4152487A JP4152487A JPS63209167A JP S63209167 A JPS63209167 A JP S63209167A JP 4152487 A JP4152487 A JP 4152487A JP 4152487 A JP4152487 A JP 4152487A JP S63209167 A JPS63209167 A JP S63209167A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- emitter layer
- type
- emitter
- concentration impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 20
- 239000012535 impurity Substances 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000009792 diffusion process Methods 0.000 abstract description 20
- 238000000034 method Methods 0.000 abstract description 11
- 238000005530 etching Methods 0.000 abstract description 3
- 239000008188 pellet Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ゲートターンオフサイリスタ（以下ＧＴＯサ
イリスタという）の製造方法に係り１％に、製造工程数
を少なくしたＧＴＯサイリスタの製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a gate turn-off thyristor (hereinafter referred to as a GTO thyristor), and relates to a method for manufacturing a GTO thyristor in which the number of manufacturing steps is reduced by 1%.
ＧＴＯサイリスタの構造に関する従来技術として例えば
、特開昭５５−３９６１９号公報、特開昭５７−２０１
０７８号公報等に記載された技術が知られている。As prior art related to the structure of the GTO thyristor, for example, Japanese Patent Application Laid-Open No. 55-39619, Japanese Patent Application Laid-Open No. 57-201
A technique described in Publication No. 078 and the like is known.
これらの従来技術によるＧＴＯサイリスタホ、ゲート端
子が低抵抗接触されていないペース層内の同じ導電、型
の半導体による高濃度不純物層を隣接するエミッタ層よ
り厚く形成することにより、このベース層をアノード端
子に低抵抗接触させるようにしたものであり、また、ゲ
ート端子を一方のベース層に低抵抗接触させるために、
このペース層に同じ導電型の半導体による高濃度不純物
層を形成したものである。In these prior art GTO thyristor stacks, the gate terminal is not connected to a low resistance by forming a highly concentrated impurity layer made of a semiconductor of the same conductivity and type in the paste layer to be thicker than the adjacent emitter layer, so that this base layer can be used as an anode. In order to make low resistance contact with the terminal, and also make low resistance contact of the gate terminal with one of the base layers,
A high concentration impurity layer made of a semiconductor of the same conductivity type is formed on this paste layer.
以下、このような従来技術によるＧＴＯサイリスクの構
造と製造方法を図面により説明する。Hereinafter, the structure and manufacturing method of GTO Cyrisk according to the prior art will be explained with reference to the drawings.
第２図（ａｔ〜（ｄｌは従来技術による製造方法を説明
する単位ＧＴＯサイリスタの断面図、第３図、第４図は
従来技術及び本発明によるＧＴＯサイリスタの平面図及
び単位ＧＴＯサイリスタの断面図である。第２図〜第４
図において、１はペレット。FIG. 2 (at to (dl) is a sectional view of a unit GTO thyristor explaining a manufacturing method according to the prior art, FIGS. 3 and 4 are a plan view of a GTO thyristor according to the prior art and the present invention, and a sectional view of a unit GTO thyristor. Figures 2 to 4
In the figure, 1 is a pellet.
２は単位ＧＴＯサイリスタ、３はｎ型高濃度不純物層、
３］はｎ型半導体基板、４はｐベース層、５はｐエミッ
タ層、６はｎエミッタ層、７はｐ型高濃度不純物層、８
はカソード電極、９はアノード電極、１０はゲート電極
である。2 is a unit GTO thyristor, 3 is an n-type high concentration impurity layer,
3] is an n-type semiconductor substrate, 4 is a p-base layer, 5 is a p-emitter layer, 6 is an n-emitter layer, 7 is a p-type high concentration impurity layer, 8
9 is a cathode electrode, 9 is an anode electrode, and 10 is a gate electrode.
短絡エミッタ構造のＧ Ｔ Ｏサイリスタは、第３図に
示すように、ペレット１内に多数の単位ＧＴＯサイリス
タ２が配列されて構成されている。各ＧＴＯサイリスタ
２は、第４図に示すような断面構造を有している。この
断面は、第３図における１−１断面である。単位Ｇ Ｔ
Ｏサイリスタ２は。The short-circuit emitter structure GTO thyristor is constructed by arranging a large number of unit GTO thyristors 2 within a pellet 1, as shown in FIG. Each GTO thyristor 2 has a cross-sectional structure as shown in FIG. This cross section is the 1-1 cross section in FIG. Unit GT
O thyristor 2.
ｎエミッタ層６．ｐベース層４．ｎベース層となるｎ型
半導体基板３１及びｐエミッタ層５が順次積み重ねられ
て構成されており、ｎエミッタ層６にカソード電極８が
、ｐベース層４にｐｍ高濃度不純物層７を介してゲート
電極１０が低抵抗に接続されている。また、ｐエミッタ
層５とｎベース層であるｎ型半導体基板３１は、アノー
ド電極９に接続される。その際、アノード電極９とｎ型
半導体基板３１とを低抵抗接触させるため、ｐエミッタ
層５に隣接する位置に、ｎ型半導体基板３１と同一の導
電型の高濃度ｎ型不純物層が、ｐエミッタ層５より厚（
形成される。n emitter layer 6. p base layer 4. An n-type semiconductor substrate 31 serving as an n-base layer and a p-emitter layer 5 are stacked one after another, and a cathode electrode 8 is connected to the n-emitter layer 6, and a gate is connected to the p-base layer 4 via a pm high-concentration impurity layer 7. Electrode 10 is connected with low resistance. Furthermore, the p-emitter layer 5 and the n-type semiconductor substrate 31, which is an n-base layer, are connected to the anode electrode 9. At this time, in order to bring the anode electrode 9 and the n-type semiconductor substrate 31 into low-resistance contact, a high concentration n-type impurity layer of the same conductivity type as the n-type semiconductor substrate 31 is placed adjacent to the p-emitter layer 5. Thicker than emitter layer 5 (
It is formed.
このような構成のＧＴＯサイリスタの従来技術による製
造方法を単位ＧＴＯサイリスタ２０部分のみの断面図に
よりその製造工程を示す第２図（ａ）〜［ｄ）により説
明する。A conventional manufacturing method for a GTO thyristor having such a configuration will be explained with reference to FIGS. 2(a) to 2(d), which show the manufacturing process using cross-sectional views of only the unit GTO thyristor 20 portion.
（１）ｎ型半導体基板３１を用意し、公知の選択拡散法
によって、このｎ型半導体基板３１内にｎ型高濃度不純
物層３を形成する〔第２図（ａ）〕。(1) An n-type semiconductor substrate 31 is prepared, and an n-type high concentration impurity layer 3 is formed in this n-type semiconductor substrate 31 by a known selective diffusion method [FIG. 2(a)].
（２） 次に、この半導体基板３１０両主面からｐ型
不純物１例えば、Ｇａを全面拡散し、ｐベース層４及び
ｐエミッタ層５を形成する〔第２図（ａ）〕。(2) Next, a p-type impurity 1, for example, Ga, is diffused over the entire surface from both main surfaces of the semiconductor substrate 310 to form a p base layer 4 and a p emitter layer 5 [FIG. 2(a)].
（３）更に、公知の選択拡散法によって、ｐベース層４
０表面にｎエミッタ層６を形成する〔第２図（Ｃ）〕。(3) Furthermore, the p base layer 4 is
An n emitter layer 6 is formed on the 0 surface [FIG. 2(C)].
（４） を後に、ｎエミッタ層６０両側をエツチング
により段差形成し、特開昭５７−２０１０７８号公報等
に示された公知の方法でｐ型高濃度不純物層７を形成す
る〔第２図（ｄ）〕。(4) After that, steps are formed on both sides of the n emitter layer 60 by etching, and a p-type high concentration impurity layer 7 is formed by a known method disclosed in Japanese Patent Application Laid-Open No. 57-201078 (see Fig. 2). d)].
これらの工程は、ペレット１上に構成される全ての単位
ＧＴＯサイリスタ２が同時形成されるように行われ、そ
の際、ｎ型高濃度不純物層３の深さがｐエミッタ層５の
深さより大きくなるようにその拡散が制御される。また
、これらの工程の終了後、カソード電極８．アノード電
極９及びゲート電極ｌＯの取付けが行われる。These steps are performed so that all the unit GTO thyristors 2 configured on the pellet 1 are formed at the same time, and at this time, the depth of the n-type high concentration impurity layer 3 is greater than the depth of the p emitter layer 5. Its diffusion is controlled so that Further, after these steps are completed, the cathode electrode 8. Attachment of the anode electrode 9 and gate electrode IO is performed.
前記従来技術は、ベース電極が低抵抗接触されていない
ｎベース層となる基板３１とアノード電極９とを低抵抗
接触させるため、隣接するｐエミッタ層５より味いｎ型
高濃度不純物層３の形成のため［１工程を要しており、
素子製造原価低減の障害となっている。すなわち、前記
従来技術は、単位ＧＴＯサイリスタ２をペレット１内に
製造するために、４回の拡散工程を必要とし、製品コス
トの高いＧＴＯサイリスタしか製造できないという問題
点を有している。In the prior art, in order to bring the anode electrode 9 into low-resistance contact with the substrate 31, which is an n-base layer with which the base electrode is not in low-resistance contact, the n-type high-concentration impurity layer 3 is more concentrated than the adjacent p-emitter layer 5. For formation [1 process is required,
This is an obstacle to reducing device manufacturing costs. That is, the prior art requires four diffusion steps in order to manufacture the unit GTO thyristor 2 in the pellet 1, and has the problem that only GTO thyristors with high product costs can be manufactured.
本発明の目的は、前記従来技術の問題点を解決し、単位
ＧＴＯサイリスタ２をペレット１内に作り込むために必
要な拡散工程数を削減し、従来技術の場合と同一の接合
構造を持つＧＴＯサイリスタを安価に製造することので
きるこの種半導体装置の製造方法を提供することにある
。It is an object of the present invention to solve the problems of the prior art, reduce the number of diffusion steps required to form a unit GTO thyristor 2 into a pellet 1, and provide a GTO thyristor having the same bonding structure as the prior art. It is an object of the present invention to provide a method for manufacturing a semiconductor device of this type, which allows thyristors to be manufactured at low cost.
本発明によれば、前記目的は、従来技術におけるｎ型高
濃度不純物層３とｎエミッタ層６の形成を１回の拡散工
程で行い、さらに、ｐ型高濃度不純物層７とｐエミッタ
層５の形成を１回の拡散工程で行うことにより達成され
る。According to the present invention, the above object is to perform the formation of the n-type high concentration impurity layer 3 and the n emitter layer 6 in the prior art in one diffusion step, and further, to form the p-type high concentration impurity layer 7 and the p emitter layer 5 in one diffusion process. This is achieved by performing the formation in one diffusion step.
ｎ型高濃度不純物層３とｎエミッタ層６を形成する拡散
と、ｐ型高濃度不純物層７とｎエミッタ層５を形成する
拡散とを夫々１回の工程で行うことにより１本発明は、
３回の拡散工程で、ペレット内１にＧＴＯサイリスタを
作り込むことができる。By performing the diffusion to form the n-type high-concentration impurity layer 3 and the n-emitter layer 6 and the diffusion to form the p-type high-concentration impurity layer 7 and the n-emitter layer 5 in one process, the present invention can
A GTO thyristor can be built into the pellet 1 through three diffusion steps.
以下１本発明による半導体装置の製造方法の一実施例を
図面により詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the drawings.
第１図（ａ）、 （ｂ）、 （ｃ）は本発明の一実施例
の製造方法を説明する単位ＧＴＯサイリスタ２の断面図
である。第１図（ａ）〜（ｃ）において１図面の符号は
第２図〜第４図の場合と同一である。FIGS. 1(a), 1(b), and 1(c) are cross-sectional views of a unit GTO thyristor 2 for explaining a manufacturing method according to an embodiment of the present invention. In FIGS. 1(a) to 1(c), the reference numerals in one drawing are the same as those in FIGS. 2 to 4.
（１） ｎ型半導体基板３１を用意し、このｎ型半導
体基板に対してその両生面からｐ型不純物１例えばＧａ
を全面拡散し、形成された片側のｐ型不純物層をラップ
等によって除去し、ｎベース層４を形成する〔第１図（
ａ）〕。(1) Prepare an n-type semiconductor substrate 31, and apply a p-type impurity 1, for example, Ga, to the n-type semiconductor substrate from both sides.
is diffused over the entire surface, and the formed p-type impurity layer on one side is removed by lapping or the like to form an n-base layer 4 [Figure 1 (
a)].
（２）次に、公知の選択拡散法によって１両主面にｎ型
不純物１例えばｐを拡散し、ｎ型高濃度不純物層３及び
ｎエミッタ層６を形成する。この工程で形成されるｎ型
高濃度不純物層３及びｎエミッタ層６は、同一条件で拡
散処理が行われるのでほぼ同一の深さとなる〔第１図（
ｂ）〕。(2) Next, an n-type impurity 1, eg, p, is diffused onto both main surfaces by a known selective diffusion method to form an n-type high concentration impurity layer 3 and an n emitter layer 6. The n-type high-concentration impurity layer 3 and the n-emitter layer 6 formed in this step have almost the same depth because the diffusion treatment is performed under the same conditions [Fig.
b)].
（３） 次に、ｎエミッタ層６０両側をエツチングに
より段差形成し、その後、ｎエミッタ層６側の主面から
公知のセルフアライメント方式によって。(3) Next, steps are formed on both sides of the n emitter layer 60 by etching, and then from the main surface on the n emitter layer 6 side by a known self-alignment method.
また反対側主面から全面拡散法によって、同時にｐ型不
純物を拡散し、ｐ型高濃度不純物層７及びｎエミッタ層
５を形成する。この工程によって形成されるｐ型高濃度
不純物層７及びｎエミッタ層５は、同一条件で拡散処理
が行われるので、はぼ同一の深さになる。また、この工
程は、ｎ型高濃度不純物層３の深さより、ｎエミッタ層
５の深さが小さくなるようにその拡散が制御される〔第
１図（Ｃ）〕。Further, p-type impurities are simultaneously diffused from the opposite main surface by a full-surface diffusion method to form a p-type high concentration impurity layer 7 and an n emitter layer 5. Since the p-type high concentration impurity layer 7 and the n emitter layer 5 formed by this step are diffused under the same conditions, they have approximately the same depth. Further, in this step, the diffusion is controlled so that the depth of the n-emitter layer 5 is smaller than the depth of the n-type high concentration impurity layer 3 [FIG. 1(C)].
これらの工程が、ベレット１上に構成される全ての単位
ＧＴＯサイリスタ２を同時に形成するように行われる点
及び、これらの工程の終了後、カソード電極８．アノー
ド電極９．ゲート電極１０を取付ける点は、従来技術の
場合と同様である、前述した本発明の一実施例の製造方
法により得られたＧＴＯサイリスタは、ｎベース層４に
ゲート電極ｌＯを低抵抗接触させるためのｐｍ高濃度不
純物層７を有し、ゲート電極１０が低抵抗接触されてい
ないｎベース層に、アノード電極９を低抵抗接触させる
ための、隣接するｎエミッタ層５の深さより深いｎ型高
濃度不純物層３を有する。第３゜４図に示した従来技術
によると同様な構造を有するものとなる。従って１本発
明の実施例によれば。These steps are performed to simultaneously form all the unit GTO thyristors 2 formed on the pellet 1, and after these steps are completed, the cathode electrodes 8. Anode electrode9. The GTO thyristor obtained by the manufacturing method according to the embodiment of the present invention, in which the gate electrode 10 is attached in the same manner as in the prior art, has a structure in which the gate electrode 10 is brought into low-resistance contact with the n-base layer 4. In order to bring the anode electrode 9 into low-resistance contact with the n-base layer, which has a pm high-concentration impurity layer 7 and to which the gate electrode 10 is not in low-resistance contact, an n-type height layer deeper than the depth of the adjacent n-emitter layer 5 is formed. It has a high concentration impurity layer 3 . The conventional technique shown in FIG. 3-4 has a similar structure. Therefore, according to one embodiment of the present invention.
単位ＧＴＯサイリスタ２をペレツ）ｌ内に製造するため
に、従来技術より少ない３回の拡散工程を必要とするの
みで、従来技術と同様な構造を有するＧＴＯサイリスタ
を安価に製造し、提供することができる。To manufacture and provide a GTO thyristor having a structure similar to that of the prior art at low cost by requiring only three diffusion steps, fewer than the prior art, in order to manufacture a unit GTO thyristor 2 in a pellet. Can be done.
以上説明したように１本発明によれば、単位ＧＴＯサイ
リスタを３回の不純物拡散工程でペレット内に作り込む
ことができ、従来技術の場合と同一の性能を有するＧＴ
Ｏサイリスタを安価に製造。As explained above, according to the present invention, a unit GTO thyristor can be built into a pellet through three impurity diffusion steps, and the GT thyristor can have the same performance as the conventional technology.
Manufacture O-thyristors at low cost.
提供することができる。can be provided.
第１図（ａｔ、 （ｂ）、 Ｉｃ）は本発明の一実施例
の製造方法を説明する単位ＧＴＯサイリスタの断面図、
第２図（ａｌ、 （ｂＬ （ｃｌ、 （ｄｉは従来技術
による製造方法を説明する単位ＧＴＯサイリスタの断面
図、第３図。
第４図は従来技術及び本発明によるＧＴＯサイリスタの
平面図及び単位ＧＴＯサイリスタの断面図である。
ｌ・・・・・・ペレット、２・・・・・・単位ＧＴＯサ
イリスタ。
３・・・・・・ｎ型高濃度不純物層、３１・・・・・・
ｎ型半導体基板、４・・・・・・ｎベース層、５・・・
・・・ｎエミッタ層、６・・・・・・ｎエミッタ層、７
・・・・・・ｐ型高濃度不純物層。
８・・・・・・カソード電極、９・・・・・・アノード
電極、１０・・・・・・ゲート電極。
第１図 第２図
７ Ｐ５！高濃崖千此ｋＷＪ局
３１−ｎ！！半導々４−反
１３図
第４図FIG. 1 (at, (b), Ic) is a cross-sectional view of a unit GTO thyristor for explaining a manufacturing method according to an embodiment of the present invention;
2 (al, (bL cl, (di) is a sectional view of a unit GTO thyristor explaining the manufacturing method according to the prior art, and FIG. 3 is a sectional view of the unit GTO thyristor. It is a sectional view of a GTO thyristor. 1... Pellet, 2... Unit GTO thyristor. 3... N-type high concentration impurity layer, 31...
n-type semiconductor substrate, 4...n base layer, 5...
...n emitter layer, 6...n emitter layer, 7
・・・・・・P-type high concentration impurity layer. 8... Cathode electrode, 9... Anode electrode, 10... Gate electrode. Figure 1 Figure 2 7 P5! Takanogai Senko kWJ station 31-n! ! Semiconductor 4-13 Figure 4
Claims (1)
間でその導電型が異なる中央の２つのベース層とその両
側のエミッタ層とによるｐｎｐｎ接合が形成され、前記
半導体基板の一方の主表面に、一方のエミッタ層と該一
方のエミッタ層に隣接する一方のベース層の高濃度不純
物層が露出し、前記半導体基板の他方の主表面に、他方
のエミッタ層と該他方のエミッタ層に隣接する他方のベ
ース層の高濃度不純物層が露出し、前記一方のエミッタ
層にカソード、前記一方のベース層にゲート、前記他方
のエミッタ層と前記他方のベース層にアノードをそれぞ
れ低抵抗接触させて構成される半導体装置において、前
記一方のエミッタ層と前記他方のエミッタ層に隣接する
他方のベース層の高濃度不純物層とを同時に形成し、ま
た、前記他方のエミッタ層と前記一方のエミッタ層に隣
接する一方のベース層の高濃度不純物層とを同時に形成
することを特徴とする半導体装置の製造方法。1. A pnpn junction is formed in a semiconductor substrate having a pair of main surfaces by two central base layers whose conductivity types differ between adjacent ones and emitter layers on both sides thereof, and one main surface of the semiconductor substrate The high concentration impurity layer of one emitter layer and one base layer adjacent to the one emitter layer is exposed, and the other emitter layer and the high concentration impurity layer adjacent to the other emitter layer are exposed on the other main surface of the semiconductor substrate. A high concentration impurity layer of the other base layer is exposed, a cathode is in low resistance contact with the one emitter layer, a gate is in contact with the one base layer, and an anode is in low resistance contact with the other emitter layer and the other base layer. In the semiconductor device configured, the one emitter layer and the high concentration impurity layer of the other base layer adjacent to the other emitter layer are formed simultaneously, and the other emitter layer and the one emitter layer are formed with a high concentration impurity layer. 1. A method of manufacturing a semiconductor device, comprising simultaneously forming a high concentration impurity layer of one adjacent base layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4152487A JPS63209167A (en) | 1987-02-26 | 1987-02-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4152487A JPS63209167A (en) | 1987-02-26 | 1987-02-26 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63209167A true JPS63209167A (en) | 1988-08-30 |
| JPH0560667B2 JPH0560667B2 (en) | 1993-09-02 |
Family
ID=12610777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4152487A Granted JPS63209167A (en) | 1987-02-26 | 1987-02-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63209167A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0366916A2 (en) * | 1988-10-04 | 1990-05-09 | Kabushiki Kaisha Toshiba | Shorted-anode semiconductor device and methods of making the same |
| JPH0282052U (en) * | 1988-12-13 | 1990-06-25 | ||
| US5248622A (en) * | 1988-10-04 | 1993-09-28 | Kabushiki Kashiba Toshiba | Finely controlled semiconductor device and method of manufacturing the same |
-
1987
- 1987-02-26 JP JP4152487A patent/JPS63209167A/en active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0366916A2 (en) * | 1988-10-04 | 1990-05-09 | Kabushiki Kaisha Toshiba | Shorted-anode semiconductor device and methods of making the same |
| US5148254A (en) * | 1988-10-04 | 1992-09-15 | Kabushiki Kaisha Toshiba | Finely controlled semiconductor device |
| US5248622A (en) * | 1988-10-04 | 1993-09-28 | Kabushiki Kashiba Toshiba | Finely controlled semiconductor device and method of manufacturing the same |
| JPH0282052U (en) * | 1988-12-13 | 1990-06-25 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0560667B2 (en) | 1993-09-02 |
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