JP2692366B2 - Gate turn-off thyristor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of use] The present invention has a four-layer structure of pnpn, and one main electrode is formed in contact with a portion of a strip-shaped upper surface protruding from an adjacent base layer. Gate turn-off (hereinafter referred to as GTO) provided in the emitter layer and the gate electrode provided in the adjacent base layer.
Thyristor).

[Conventional technology]

A GTO thyristor is a semiconductor device for power that can be turned on and off with a date, and in terms of characteristics, whether or not the maximum turn-off current is large is directly reflected in the quality of the device. Therefore, various methods have been tried to improve the maximum turn-off current. The most effective method among them is to reduce the gate impedance and to reduce the variation in the gate impedance.

For this reason, in general, in various GTO thyristors, it has been attempted to reduce the sheet resistance of the p-base layer where the gate is provided as much as possible and to appropriately control the etchdown of the gate portion to reduce the variation in etching depth. Came.

Fig. 2 shows a typical conventional GT with a segment structure.
It shows an O thyristor and has a four-layer structure including a p-emitter layer 1, an n-base layer 2, a p-base layer 3 and an n-emitter layer 4. Then, gate etching is performed from the n emitter layer 4 side to the p base layer 3 to form a cathode segment composed of a strip-shaped n emitter layer region. The cathode electrode 5 is deposited on the top surface of the cathode segment, and the gate electrode 6 is deposited on the exposed p base layer 3.

The gate impedance Z of the GTO thyristor is the sum of Z ₁ and Z ₂ shown in FIG.

That is, Z = Z ₁ + Z ₂ (1) Z ₁ is the impedance from directly below the center of the cathode electrode 5 of the p base layer 3 to the side surface of the cathode segment, and Z ₂ is between the p base layer 3 and the n emitter layer 4.
It is the impedance from below the pn junction to below the edge of the gate electrode 6.

[Problems to be solved by the invention]

In equation (1), Z ₁ is the width of the cathode segment and
It is an amount determined by the impurity concentration directly under the pn junction between the p base layer 3 and the n emitter layer 4, and may be considered constant if the size of the cathode segment is constant. Therefore, what affects the magnitude or variation of the gate impedance is
Z is _2, the value of Z ₂ is highly dependent on the gate groove depth d and dimensional accuracy of the gate electrode 6 is formed in the gate etching. Therefore, in order to reduce Z, it is better to make the gate etching depth d as shallow as possible. However, when it becomes 25 μm or less, this time, in the case of a large current GTO thyristor that generally adopts a pressure contact structure, the gate electrode 6 and cathode electrode 5
There is a risk that a short circuit will occur between the two, and it is generally said that a groove depth of about 30 μm to 35 μm is desirable.

However, such gate etching of 30 to 35 μm, for example, GTO that handles a large current of Si plate diameter of 75 mm or more
When applied to a thyristor, it was unavoidable that the etching depth d varied at least about 5 μm in the diameter direction. For GTO thyristors, it is experimentally known that the variation of only about 5 μm has a great influence on the gate impedance, and the variation rate is 40% or more. Since this 40% variation in gate impedance is an obstacle for improving the maximum turn-off current of the GTO thyristor, it is the most important issue to suppress the variation in gate impedance.

An object of the present invention is to solve the above-mentioned problems and to provide a GTO thyristor in which the variation of the gate impedance is small even if the gate etching depth varies and the maximum turn-off current is improved.

[Means for solving the problem]

In order to achieve the above object, the present invention has a four-layer structure including a first conductivity type emitter layer, a second conductivity type base layer, a first conductivity type base layer and a second conductivity type emitter layer. The main electrode of the second conductivity type is in contact with the surface of the first conductivity type emitter layer formed on the protruding portion of the second conductivity type base layer, and the second conductivity type base layer is of the first conductivity type emitter layer. The impurity concentration is highest toward the first conductivity type base layer with the highest impurity concentration at the peripheral edge, and the gate electrode is formed on the surface of the second conductivity type base layer other than the protruding second conductivity type base layer. In contact, the second conductivity type base layer and the first conductivity type emitter layer have a mesa structure, and the bonding surface of the first conductivity type emitter layer and the second conductivity type base layer is another bonding surface. To the central portion parallel to the first conductivity type emitter layer side It consists curved peripheral portion that is, the first than the central portion of the joint surface and having a bonding surface and spacing the intersection of the side surface of the projecting portion the joint surfaces
It is assumed that a low resistance layer of the second conductivity type is formed on the surface of the second conductivity type base layer from the side surface position on the conductivity type emitter side to the position where the gate electrode contacts. As a manufacturing method, a step of diffusing and forming a second conductivity type emitter layer on one surface of the first conductivity type semiconductor substrate and a step of diffusing and forming a second conductivity type base layer on the other surface of the semiconductor substrate. And a plurality of first electrodes selectively on the surface of the second conductivity type base layer.
Forming a conductive type emitter layer by diffusion, forming a mask selectively on the first conductive type emitter layer, and the second conductive type base layer and the first conductive type emitter layer forming a mesa structure. And etching the second conductivity type base layer and the first conductivity type emitter layer to a depth smaller than the depth of the first conductivity type emitter layer, and the first conductivity type emitter layer surface and the first conductivity type emitter layer on the periphery thereof. Forming a mask on the second conductivity type base layer and further etching the second conductivity type base layer deeper than the bottom of the first conductivity type emitter layer; and the second layer formed by this etching.
A step of diffusing and forming a second conductivity type low resistance layer from a side surface of the protruding portion of the conductivity type base layer on a side closer to the emitter than a bottom portion of the first conductivity type emitter layer to a surface of the recess; and a step of forming a gate electrode on the recess. Shall have.

[Action]

By forming a low resistance layer having the same conductivity type as the base layer on the surface from the position where the gate electrode of the base layer contacts to the vicinity of the interface with the emitter layer, Z ₂ of the gate impedance Z is set to the depth of the gate groove. It becomes irrelevant, and even if the gate groove depth varies, the variation in gate impedance is eliminated. Further, since the base layer left between the low resistance layer and the pn junction between the emitter layer and the base layer is the portion having the highest impurity concentration in the base layer, the absolute value of Z ₂ itself also becomes small.
Since the pn junction surface between the emitter layer and the base layer is formed as a concave surface to leave such a portion having a high impurity concentration adjacent to the low resistance layer, the characteristics of the thyristor are that of the concave surface that determines the thinnest thickness of the base layer. Since it is dominated by the lower central part, the thyristor characteristics are not affected.

〔Example〕

FIG. 1 is a cross-sectional view of one segment of a GTO thyristor according to an embodiment of the present invention, and the same parts as those in FIG. 2 are designated by the same reference numerals. The difference from the case of FIG. 2 is that first, the p base layer 3 and the n emitter layer 4 of the cathode segment are used.
The pn junction surface 34 between them is formed as a concave surface, secondly the side surface of the cathode segment has two steps, and thirdly, the gate electrode 6 is adhered from the peripheral edge of the upper step surface. That is, the P ⁺⁺ low resistance layer 7 having a high impurity concentration is formed over the flat surface.

Such a GTO thyristor is shown in Fig. 3 (a) to (e).
It is made by a process as shown in FIG. First, impurities are diffused into an n-type silicon substrate to form a p-emitter layer 1, an n-base layer 2 and a p-base layer 3 (FIG. A). p emitter layer 1, p base layer 3
Has a surface impurity concentration of 3 × 10 ¹⁷ / cm ³ . Next, the selective diffusion technique is used to disperse and form the n emitter regions 4 (FIG. B). In order to make the n-emitter region 4 thus formed into a stepped cathode segment, an oxide film is deposited, and a pattern of an oxide film mask is formed by photolithography. Gate etching is performed (Fig. C). Further, again, by forming an oxide film and patterning, a mask that is 10 μm larger on one side than the first mask is formed, and the second gate etching is combined with the first etching depth to a depth of 35 to 40 μm. Perform to the depth (Fig. D). After that, impurity diffusion is performed using the oxide film mask during the second gate etching,
A P ⁺⁺ layer 7 having a surface impurity concentration of 10 ¹⁹ to ²⁰ / cm ³ is provided (Fig. E). This process is a so-called self-alignment process. In this case, since the shoulder portion having a width of 10 μm or more is formed in the p base layer 3 in the first gate etching, the P ⁺⁺ layer 7 having a depth of about 5 μm does not reach the pn junction surface 34.

FIG. 4 shows the impurity concentration profile of the GTO thyristor made in this way, corresponding to the cross-sectional structure. As can be seen from this figure, the P ⁺⁺ layer 7 reaches a portion having a higher impurity concentration as indicated by the dotted line 41 than the pn junction surface between the p base layer 3 and the n emitter layer 4. Therefore, the absolute value of Z _{2 in} the gate impedance becomes small.

FIG. 5 is a GTO thyristor of an embodiment in which the gate etching is performed only once without performing the gate etching in two stages as shown in FIGS. In this embodiment, the n emitter layer 4 is formed so as to project from the flat surface of the p base layer 3. Therefore, the end of the P ⁺⁺ low resistance layer 7 ends at the flat surface of the p base layer 4. In this case, if the diffusion depth t ₂ of the P ⁺⁺ layer 7 is shallow, a portion deeper than that of the p base layer 3 affects the gate impedance, so that the gate impedance strongly depends on the etching depth. Therefore, it is desirable to make t ₂ larger than the depth t ₁ from the bottom surface of the gate groove to the pn junction surface 34.

Although the above embodiments describe the GTO thyristor in which the gate electrode is provided in the p base layer, the present invention can also be implemented in a GTO thyristor in which the gate electrode is provided in the n base layer and the anode segment is formed.

〔The invention's effect〕

According to the present invention, a high impurity concentration portion is left in the peripheral portion of the emitter layer adjacent to the base layer provided with the gate electrode,
By forming a low resistance layer reaching the portion from the contacting portion of the gate electrode on the surface of the base layer, even if there is a variation in the gate etching depth, the variation in the gate impedance is completely eliminated from the structure.
For GTO thyristors that operate GTO segments in parallel, current concentration at turn-off is reduced. Then, since the absolute value of the gate impedance also becomes small, the maximum turn-off current is dramatically improved. As a result, the maximum turn-off current is about 1.5 times that of the conventional structural device.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a segment of a GTO thyristor according to an embodiment of the present invention, FIG. 2 is a sectional view of a segment of a conventional GTO thyristor, and FIG. 3 is a GTO thyristor of FIG. 4A to 4E are sectional views showing the manufacturing steps in the order of (a) to (e), FIG. 4 is a comparison diagram of the impurity concentration profile and the sectional structure of the GTO thyristor of FIG. 1, and FIG. 5 is another embodiment of the present invention. FIG. 3 is a sectional view of a segment of the GTO thyristor. 1 ... p emitter layer, 2 ... n base layer, 3 ... p base layer, 4 ... n emitter layer, 5 ... cathode electrode, 6 ...
… Gate electrode, 7… P ⁺⁺ Low resistance layer.

Claims (3)

(57) [Claims] 1. A four-layer structure comprising a first conductivity type emitter layer, a second conductivity type base layer, a first conductivity type base layer and a second conductivity type emitter layer, one main electrode of which is the second conductivity type. Contacting the surface of the first conductivity type emitter layer formed on the protruding portion of the second conductivity type base layer, the second conductivity type base layer having the highest impurity concentration at the peripheral portion of the first conductivity type emitter layer. Then, the impurity concentration decreases toward the first-conductivity-type base layer, and the gate electrode contacts the surface of the second-conductivity-type base layer other than the protruding second-conductivity-type base layer. The conductivity type base layer and the first conductivity type emitter layer have a mesa structure, and the bonding surface between the first conductivity type emitter layer and the second conductivity type base layer is the central portion parallel to another bonding surface and the first bonding surface. 1 Conduction type Is it a curved peripheral edge that is bent toward the emitter layer side? The second contact surface has a space between the second contact surface and the contact surface where the projecting portion crosses, and the second surface extends from the side surface position closer to the first conductivity type emitter than the central portion of the second contact surface to the contact position of the gate electrode. A gate turn-off thyristor having a low-resistance layer of a second conductivity type formed on the surface of a conductivity type base layer. 2. A second conductivity type semiconductor substrate having a second surface on one surface thereof.
Diffusing and forming a conductivity type emitter layer, diffusing and forming a second conductivity type base layer on the other surface of the semiconductor substrate, and selectively forming a plurality of first conductivity on the surface of the second conductivity type base layer. Forming a diffusion type emitter layer, forming a mask selectively on the first conductivity type emitter layer, and forming a second mask
The second conductivity type base layer and the first conductivity type emitter layer are formed so that the conductivity type base layer and the first conductivity type emitter layer form a mesa structure and are shallower than the depth of the first conductivity type emitter layer. A step of etching, forming a mask on the surface of the first conductivity type emitter layer and on the second conductivity type base layer around the emitter layer, and forming the second conductivity type base layer deeper than the bottom of the first conductivity type emitter layer; A step of further etching, and a second step from the side surface on the emitter side of the bottom portion of the first conductivity type emitter layer of the protruding portion of the second conductivity type base layer formed by this etching to the recess surface.
A method of manufacturing a gate turn-off thyristor, comprising: forming a conductive low resistance layer by diffusion; and forming a gate electrode on the recess. 3. A second conductivity type is provided on one surface of the semiconductor substrate of the first conductivity type.
Diffusing and forming a conductivity type emitter layer, diffusing and forming a second conductivity type base layer on the other surface of the semiconductor substrate, and selectively forming a plurality of first conductivity on the surface of the second conductivity type base layer. Forming a diffused emitter layer, and selectively forming a mask on the emitter layer so that the second conductivity type base layer and the first emitter layer form a mesa structure.
And a step of etching shallower than the depth of the first conductivity type emitter layer, and a second resistance type low resistance having a distance from the surface of the etched base layer to the emitter layer and deeper than the depth of the emitter layer. A step of forming a diffusion layer,
A step of forming a gate electrode on the low resistance layer, the method of manufacturing a gate turn-off thyristor.