JP2596126B2 - Epitaxial gate turn-off thyristor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] In the present invention, an amitter layer of a first conductivity type dispersed and arranged on a base layer of a second conductivity type provided with a gate electrode uses an epitaxial technique. The present invention relates to an epitaxial gate turn-off (GTO) thyristor formed through a low impurity concentration second conductivity type layer.

[Conventional technology]

It is desired that the GTO thyristor has a large maximum control current. Generally, in order to improve the maximum control current of the GTO thyristor, a method of reducing the gate impedance or a method of increasing the reverse withstand voltage between the gate and the cathode so that the reverse bias voltage applied between the gate and the cathode at the time of turn-off can be increased is considered. Have been. In a GTO thyristor that forms an n emitter and a p base by the diffusion method,
There is a conflicting relationship between the reverse withstand voltage between the gate and the cathode and the gate impedance. That is, in order to reduce the gate impedance, the concentration of the p base layer in the gate portion must be high. However, in order to increase the reverse breakdown voltage between the gate and the cathode, the concentration of the p base layer must be low. In order to solve these contradictory characteristics, an epitaxial GTO thyristor in which a low-concentration p ⁻ layer is formed between a p base layer and an n emitter layer by an epitaxial technique has been devised.

Hereinafter, the structure of the epitaxial GTO thyristor will be described with reference to the drawings. A conventional epitaxial GTO thyristor has a cross-sectional structure as shown in FIG. 2, and a silicon substrate has a p emitter layer 1, an n base layer 2, a p ⁺ base layer 3, a p ⁻ epitaxial base layer 4, and an n emitter layer 5, The n emitter layer 5 and the p ⁻ epitaxial base layer 4 are formed as a number of island-shaped segments surrounded by the p ⁺ base layer 3.
An anode electrode 6 and a cathode electrode 7 are attached to the p emitter layer 1 and the n emitter layer 5, respectively, and are connected to the main terminals via, for example, a pressure contact electrode body. Further, a gate electrode 8 is adhered to the p ⁺ base layer 3. The side surfaces of the island-shaped segments are covered with an oxide film 9 as a protective film.

Such an epitaxial GTO thyristor shifts from an off state to an on state when a current is applied to the gate electrode 8 between the cathode electrode 7 and the gate electrode 8 when the voltage of the anode electrode 6 is positive with respect to the cathode electrode 7. Conversely, when a current is drawn from the gate electrode 8, the state changes from the on state to the off state.

[Problems to be solved by the invention]

In the epitaxial GTO thyristor, such as described above, p ^-
Since the n-emitter layer 5 is provided on the epitaxial base layer 4, the impurity concentration at the junction between the gate and the cathode is low, and the reverse breakdown voltage is reduced from about 20 to 30V to about 100 to 150V.
Can be improved by a factor of two. This means that the reverse bias applied between the gate and the cathode can be increased to about five times that of the conventional device, and therefore, the ability to pull out from the gate is improved to five times. However, since the concentration of the p ⁻ base layer 4 immediately below the n emitter layer 5 is lower than the concentration of the p base layer of the conventional device, the impedance at that portion becomes larger than that of the conventional device. Therefore, it is necessary to draw a current from the gate at the time of turn-off through the p ⁺ diffusion base layer 3 having a high concentration. The p ⁺ diffusion base layer 3 has an impurity concentration distribution due to diffusion, and the vicinity of the boundary with the p ⁻ epitaxial base layer 4 has a high impurity concentration. Therefore, if the portion of the p ⁺ layer 3 where the impurity concentration is high is not uniformly etched during the gate etching, the gate impedance varies and the maximum turn-off current is significantly impaired. In the conventional gate etching technique, when etching 30 μm, a variation of about 5 μm occurs on a 4-inch wafer, causing a variation in gate impedance or leaving the p ⁻ low-concentration epitaxial layer 4 entirely without etching. It was in a state where I couldn't help. In particular, there is a problem that the gate impedance is extremely increased when the p ^- epitaxial layer 4 remains.

An object of the present invention is to provide an epitaxial GTO thyristor capable of solving the above-mentioned problem and forming a small gate pull-out resistance required for improving a maximum turn-off current without variation.

[Means for solving the problem]

In order to achieve the above-described object, the present invention provides a method for forming a gate electrode on one surface and forming a base layer of a first conductivity type on the other surface. A selectively low-impurity-concentration second-conductivity-type epitaxial layer is formed selectively, and an emitter layer of the first-conductivity-type is selectively formed on the surface of the epitaxial layer. It is assumed that a high impurity concentration first conductivity type layer is formed continuously between one surface and the gate electrode and on the side surface of the convex epitaxial layer.

[Action]

The high impurity concentration second conductivity type layer formed continuously between one surface of the second conductivity type base layer and the gate electrode and on the side surface of the convex epitaxial layer serves as a path for the gate pull-out current, even if the recess is etched. Low gate impedance can be ensured even if the depth varies. On the other hand, the pn junction between the base of the second conductivity type and the emitter of the first conductivity type is between the low impurity concentration second conductivity type epitaxial layer and the first conductivity type emitter layer selectively formed on the surface thereof. Therefore, a high reverse withstand voltage can be sufficiently ensured.

〔Example〕

FIG. 1 shows a cross-sectional structure of an epitaxial GTO thyristor according to one embodiment of the present invention, and portions common to FIG. 2 are denoted by the same reference numerals. Also in this case, similarly to the thyristor shown in FIG. 2, the p ⁻ epitaxial base layer 4 is formed as a large number of island-shaped segments surrounded by the p ⁺ base layer 3, and the n emitter layer 5 is selectively provided on the surface thereof. Have been. Therefore, n emitter layer 5 is surrounded by p ⁻ epitaxial base layer 4, and the pn junction generated between them has a high reverse breakdown voltage.
The difference from the thyristor shown in FIG. 2 is that a p ⁺⁺ diffusion layer 10 indicated by oblique lines is provided on the surface of the base layer 3 formed by etching and the side surface of the epitaxial layer 4. This p ⁺⁺ diffusion layer is formed by a well-known self-alignment type selective diffusion using an oxide film mask protecting the cathode segment portion as it is when the recess around the island-shaped cathode segment is dug down by etching. . Even if there is a variation in the depth etching for forming the recess and the surface impurity concentration of the p ⁺ base layer on the bottom of the recess varies, or the p ^- epitaxial layer remains, the diffusion of this p ^{+ +} layer As a result, a path for a gate extraction current having a high impurity concentration is formed, and a low gate impedance is ensured. In the above embodiment, the GTO thyristor in which the gate electrode is provided in the p base layer has been described. However, the present invention can be similarly applied to the epitaxial layer GTO thyristor in which the gate electrode is provided in the n base layer.

〔The invention's effect〕

According to the present invention, a reverse breakdown voltage between a gate electrode and an adjacent main electrode is conventionally reduced by interposing a low impurity concentration epitaxial base layer between a second conductivity type base layer and a first conductivity type emitter layer. A high impurity concentration layer of the second conductivity type is provided continuously on the surface of the second conductivity type base layer of the epitaxial GTO thyristor and the side surface of the convex epitaxial layer, which is about five times as large as the device, so that the extraction current to the gate electrode can be reduced. Because of the path, it was possible to obtain an epitaxial GTO thyristor with a maximum turn-off current and approximately three times the capacity of the conventional device.

[Brief description of the drawings]

FIG. 1 is a sectional view of an epitaxial GTO thyristor according to one embodiment of the present invention, and FIG. 2 is a sectional view of a conventional epitaxial GTO thyristor. 1: p emitter layer, 2: n base layer, 3: p ⁺ base layer, 4: p ^- epitaxial base layer, 5: n emitter layer, 6: anode electrode, 7: cathode electrode, 8: gate electrode, 10: p ⁺⁺ diffusion layer.

Claims (1)

(57) [Claims] A first conductive type base layer having a gate electrode formed on one surface and a first conductive type base layer formed on the other surface; A second conductivity type epitaxial layer is formed, and an emitter layer of the first conductivity type is selectively formed on a surface portion of the epitaxial layer. An epitaxial gate turn-off thyristor, wherein a high impurity concentration second conductivity type layer is continuously formed on a side surface of the convex epitaxial layer.