JPH0267764A - Gate turnoff thyristor - Google Patents

Abstract

PURPOSE:To avoid a local concentration of an electric current and to enhance a current cutoff capacity by a method wherein a high-concentration impurity region is formed in a part coming into contact with a gate electrode on the surface of a p-base layer and in its neighborhood in order to reduce a contact resistance with respect to the gate electrode. CONSTITUTION:A p-base layer 3 is etched down; a gate electrode 7 is formed in a flat part of its exposed face. A high-concentration impurity region 5 whose conductivity type is identical to that of the p-base layer 3 is formed so as to be stretched to the side of a p-n junction between an n-emitter layer 4 and the p-base layer 3 around a region where the gate electrode 7 for the p-base layer 3 is formed and by exceeding this region. Thereby, a contact resistance is reduced; a local concentration of an electric current during a gate turnoff is avoided; a current cutoff capacity is enhanced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a gate turn-off thyristor whose gate-cathode junction has a mesa-type structure, and which is particularly suitable for improving the performance of interrupting current flowing between the anode and the cathode. Regarding structure.

[Conventional technology]

A conventional gate-cathode structure having a mesa type junction is shown in FIG. The gate electrode 7 formed on the surface of the p base layer 3 adjacent to the etched-down n emitter layer 4 has a high contact resistance because it is formed directly on the etched-down surface. When trying to extract the flowing current from the gate electrode 7, there is a risk that current concentration may occur locally and the current interrupting ability may be reduced. Note that this type of device is published, for example, in the 1981 IEE National Conference Material "Gate Turn Off (GT○) Thyristor" and Japanese Patent Application Laid-Open No. 51-50678.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, no consideration is given to reducing the contact resistance of the gate electrode, which is one of the factors that reduce the current interrupting ability, and current concentration occurs locally during turn-off operation, resulting in a decrease in the current interrupting ability. There was a problem.

SUMMARY OF THE INVENTION An object of the present invention is to provide a gate turn-off thyristor in which the contact resistance of the gate electrode is reduced, local current concentration is avoided, and current interrupting ability is improved.

[Means to solve the problem]

The above object is achieved by forming a region of the same conductivity type as the p-base layer and having a higher impurity concentration than that of the p-base layer at a location where the gate electrode is contacted on the surface of the etched-down p-base layer and in the vicinity thereof. This high impurity concentration region is formed extending from the gate electrode to the pn junction side between the n emitter layer and the p base layer.

[Effect]

The high impurity concentration region formed at and near the location where the gate electrode is in contact can reduce the gate resistance between the n-emitter layer and the gate electrode. By reducing the gate resistance, local current concentration that occurs during gate turn-off is eliminated, so current interrupting ability is improved. Furthermore, when a reverse voltage is applied between the gate electrode and the cathode electrode, the pn
The expansion of the depletion layer formed at the junction toward the gate electrode can be suppressed in the high impurity concentration region, and as a result, compared to the conventional structure in which a low resistance layer (high concentration layer) is not formed in the gate region, Reverse leakage current between gate and cathode is reduced,
The gate-cathode breakdown voltage can be increased.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. The semiconductor substrate 1 has a P emitter layer, an n base layer 2+P base layer 3, and an n emitter layer 4 between a pair of main surfaces, at least a P emitter layer on one main surface and an n emitter layer on the other main surface.
The emitter layer 4 and the p base layer 3 are exposed. The n-emitter layer 4 has a large number of elongated strip-shaped regions, and a cathode electrode 6 having substantially the same shape is fixed and formed on the surface thereof. A p base layer 3 is formed adjacent to the n emitter layer 4 so as to surround each strip-shaped region of the n emitter layer 4. This p base layer 3 is exposed on the etched down surface, and a gate electrode 7 is fixed and formed on the flat part of the exposed surface.

The upper surface of the gate electrode 7 is the n emitter y! It is designed so that it does not reach the top surface of j4. This is to prevent the cathode electrode and the gate electrode from coming into contact when the pressure contact type is used. Therefore, the p base J in the region where the gate electrode 7 is formed
The thickness of l13 is thinner than the area directly under the n emitter layer,
The impurity concentration on the surface becomes low. 5 is p base layer 3
A high-conductor layer of the same conductivity type as the p-base layer 3 is formed centering on the region where the gate electrode 7 is formed, and extending beyond this region to the p-n junction side between the n-emitter layer 4 and the p-base layer 3. This is an impurity concentration region. 6 is a cathode electrode, and 8 is a passivation film. According to this embodiment, by forming the high impurity concentration region 5, the contact resistance of the gate electrode is reduced, local current concentration at the time of gate turn-off can be avoided, and the current interrupting ability can be improved.

In addition, the high impurity concentration region formed in the gate region is
By forming the N emitter layer 4 separated by a predetermined distance from the N emitter layer 4 having a different conductivity type, when a reverse overvoltage is applied between the gate and the cathode, the p
The depletion layer that spreads to the n-junction acts as a channel stopper, and has the effect of reducing leakage current. Note that the high impurity concentration region has a depth of 1 to 20 μm,
The surface concentration is I x 10111-10”atoms/
cm2, so as not to impair the device characteristics during conduction.

〔Effect of the invention〕

According to the present invention, since a high impurity concentration region is formed where the gate electrode is contacted in the p base layer and extends from there to the n emitter layer side, the contact resistance of the gate electrode can be reduced, and as a result, the contact resistance of the gate electrode can be reduced. This prevents serious current concentration, prevents damage to the semiconductor substrate, and improves current interrupting ability. Furthermore, it has the effect of suppressing unnecessary expansion of the depletion layer toward the n-base layer, which occurs when the pn junction between the n-emitter layer and the n-base layer is reverse biased.

[Brief explanation of the drawing]

FIG. 1 is a schematic vertical cross-sectional view of the main parts showing an embodiment of the present invention, and FIG. 2 is a vertical cross-sectional view showing a conventional structure. DESCRIPTION OF SYMBOLS 1...Semiconductor base, 2...N base layer, 3...N base layer, 4...N emitter layer, 5...High impurity concentration region. 6... Cathode electrode, 7... Gate electrode.

Claims (1)

[Claims] 1. A pair of main surfaces has four consecutive layers of alternately different conductivity types, one outer layer is composed of a large number of strip-shaped regions, and each strip-shaped region is etched down. a semiconductor substrate surrounded by a flat surface and with one intermediate layer adjacent to one outer layer exposed on the etched-down surface; a main electrode provided on one outer layer of the semiconductor substrate; a control electrode provided on one of the intermediate layers on the etched-down surface of the semiconductor substrate, at a location where the control electrode contacts the etched-down surface of the semiconductor substrate and at a location extending from the control electrode toward the one outer layer side; A gate turn-off thyristor characterized in that a region with higher impurity than a p base layer is provided. 2. In claim 1, the high impurity concentration region has a surface concentration of 1×10^1^8 to 20^2^0a.
toms/cm^2 and has a depth of 1 to 20 μm.