JPH0766433A - Semiconductor rectifier element - Google Patents

Abstract

PURPOSE:To prevent the decrease of barrier height and keep a leak current small, by constituting a second conductivity type high impurity concentration semiconductor region, a first conductivity type semiconductor ground layer, and a first conductivity type high impurity concentration semiconductor layer, by using semiconductor materials different in the band gap. CONSTITUTION:A P<+> type semiconductor region 3 and a P<+> type second semiconductor region 6 are constituted of silicon material. An N-type semiconductor ground layer 1 and an N<+> type semiconductor layer 2 are constituted of semiconductor material, e.g. silicon carbide, whose band gap is larger than that of silicon. Thereby the junction potential of a PN junction becomes large to be about 2V, so that the build-up of the PN junction can be prevented as far as a range wherein a conduction current becomes large, and the injection of minority carrier in the first conductivity type semiconductor ground layer can be prevented. Hence the decrease of barrier height can be prevented, and a leak current can be kept small.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor rectifying device, and more particularly to reducing a leak current as compared with conventional devices.
The present invention relates to a semiconductor rectifier element that can be turned off at high speed even when a large current flows.

[0002]

2. Description of the Related Art Up to now, Schottky diodes and pn diodes have been known as typical semiconductor rectifying devices. By the way, the Schottky diode has an advantage that a forward voltage drop is small during conduction as compared with a pn diode, but has a disadvantage that it is difficult to increase breakdown voltage and a reverse leak current is large. have.

In order to improve this disadvantage, some means have already been proposed for the Schottky diode to reduce the leak current in the reverse direction, and examples thereof include Japanese Patent Publication No. 59-35183. No. 59-115566, or JP-A-60-7458.
The means disclosed in No. 2 can be mentioned.

In all of these means, a plurality of semiconductor regions having a conductivity type different from the conductivity type of the semiconductor forming the semiconductor substrate region are provided adjacent to the Schottky junction portion at a predetermined interval to form a Schottky diode. When a reverse voltage is applied, a depletion layer is expanded in the semiconductor substrate region by reverse biasing a pn junction between the semiconductor substrate region and the plurality of semiconductor regions of different conductivity types. Thus, the plurality of semiconductor regions of different conductivity types are pinched off from each other.

[0005]

However, in the above-disclosed means, when a reverse voltage is applied to the Schottky diode, the semiconductor substrate region and the plurality of semiconductor regions of different conductivity types are separated from each other. Since the depletion layer is expanded from the pn junction into the semiconductor substrate region and the plurality of semiconductor regions of different conductivity types are pinched off from each other, a forward voltage is applied to the Schottky diode, which causes a large current flow. Flow, the pn junction formed in the Schottky diode is in a forward biased state to cause buildup, and as a result, majority carriers in the semiconductor having a high impurity concentration are injected.

Therefore, according to the above-described means, when the Schottky diode is turned off, the residual carriers that become the recovery current increase, and the turn-off time significantly increases, so that a Schottky diode that can operate at high speed cannot be realized. I have a problem.

Further, in the means disclosed above, in order to reduce the leakage current, it is necessary to make the interval between the adjacent pn junctions sufficiently small to reduce the electric field strength in the vicinity of the Schottky junction. If the structure that satisfies the above requirements is adopted, the forward current path is narrowed and the forward voltage drop in that portion becomes large. Therefore, in an actual Schottky diode, the interval between adjacent pn junctions is sufficiently small. However, there is a problem that the leak current cannot be sufficiently reduced.

The present invention eliminates the above-mentioned problems and provides a semiconductor rectifying device which is turned off at a high speed even at a large current and has a small leak current at the time of off, as compared with the conventional devices. To provide.

[0009]

To achieve the above object, the present invention provides a first conductivity type semiconductor base layer and a first conductivity type high impurity which is bonded to one surface of the semiconductor base layer. One or more second-conductivity-type high-concentration semiconductor layers having a concentration and one surface at the same level as the other surface of the semiconductor substrate layer and the other surface reaching the inside of the semiconductor substrate layer. And a first main electrode that is in Schottky contact with the exposed portion of the other surface of the semiconductor base layer and is in ohmic contact with one surface of the second-conductivity-type high impurity concentration semiconductor region. A second main electrode in ohmic contact with the first conductivity type high impurity concentration semiconductor layer, and a pn junction is formed between the second conductivity type high impurity concentration semiconductor region and the semiconductor base layer. In the semiconductor rectifier to be formed, A second said conductive-type high impurity concentration semiconductor region of the semiconductor substrate layer and a semiconductor layer having a high impurity concentration of said first conductivity type, comprising means are composed of a semiconductor material having a band gap different from each other.

[0010]

According to the above-mentioned means, the semiconductor rectifying device according to the present invention comprises the second conductivity type high impurity concentration semiconductor region, the first conductivity type semiconductor base layer, and the first conductivity type high impurity concentration semiconductor layer. Are made of semiconductor materials having different band gaps.

In this case, if the first conductivity type semiconductor base layer is made of a semiconductor having a wide band gap such as silicon carbide (SiC), a known structure of a composite of a Schottky junction and a pn junction is known. In the semiconductor rectifying device, the junction potential of the pn junction is about 0.7 to 0.9 V when it is a silicon (Si) semiconductor, whereas in the semiconductor rectifying device according to the present invention, the pn junction is Since the junction potential of the junction increases to about 2 V, the semiconductor rectifying device according to the present invention can prevent buildup of the pn junction to the extent that the flow current increases.
Injection of minority carriers into the first conductivity type semiconductor substrate layer can be prevented.

Therefore, the semiconductor rectifying device according to the present invention can perform turn-off at a high speed without increasing residual carriers that are the basis of recovery current at turn-off.

Further, in the above case, when the second conductivity type semiconductor region having a high impurity concentration is formed of a semiconductor having a wide band gap like silicon carbide (SiC),
By keeping the potential barrier at the time of majority carrier injection equal to that of a known silicon (Si) semiconductor rectifier, the impurities of the second conductivity type semiconductor region having a high impurity concentration are maintained while maintaining the high-speed characteristics at turn-off. The concentration can be higher than known.

Therefore, in the semiconductor rectifying device according to the present invention, the spread of the depletion layer to the semiconductor substrate layer of the first conductivity type is increased when a bias is applied, and the electric field strength of the Schottky junction sandwiched by the pn junctions is increased. As a result, the barrier height is prevented from lowering when the reverse bias is applied, and the leak current can be kept small.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a perspective view showing the structure of the essential part of a first embodiment of a semiconductor rectifying device according to the present invention.

In FIG. 1, 1 is an n-type semiconductor substrate layer (first conductivity type semiconductor substrate layer), 2 is an n + type semiconductor layer (first conductivity type high impurity concentration semiconductor layer), and 3 is P +. Type semiconductor region (second conductivity type semiconductor region of high impurity concentration), 4 is an anode electrode (first main electrode), 5 is a cathode electrode (second main electrode), 6 is a P + type second semiconductor Region (second conductivity type second semiconductor region having high impurity concentration),
Reference numeral 7 is an insulating layer. In this case, the P + type semiconductor region 3 and the P + type second semiconductor region 6 are each made of a silicon (Si) material, and the n type semiconductor base layer 1 is formed.
And the n + type semiconductor layer 2 are formed of the silicon (S
i) A semiconductor material having a wider band gap than that of i), for example, silicon carbide (SiC).

Then, one surface of the n + type semiconductor layer 2 is bonded to one surface of the n type semiconductor substrate layer 1, and the cathode electrode 5 is ohmic bonded to the other surface of the n + type semiconductor layer 2. . On the other surface of the n-type semiconductor base layer 1, one surface is at the same level as the other surface of the n-type semiconductor base layer 1, and the other surface reaches the inside of the n-type semiconductor base layer 1. A plurality of band-shaped P + type semiconductor regions 3 are provided, and these band-shaped P + type semiconductor regions 3 are arranged so as to form a stripe shape on the other surface of the n type semiconductor base layer 1. In addition, the other surface of the n-type semiconductor base layer 1 has one surface at the same level as the other surface of the n-type semiconductor base layer 1 and the other surface of the n-type semiconductor base layer 1. 1 strip-shaped P + -type second semiconductor region 6 which is bent in a substantially L-shape along the adjacent peripheral edge of the n-type semiconductor base layer 1 to reach the inside of the second semiconductor region 6. Is provided. On the substantially L-shaped P + type second semiconductor region 6, along _one of the substantially L-shaped strip-shaped portions 6 ₁ and the strip-shaped portion 6 ₁
The insulating layer 7 is arranged so as to cover substantially half of the exposed surface. An anode electrode 4 is bonded on each exposed portion of the n-type semiconductor base layer 1, the plurality of strip-shaped P + type semiconductor regions 3, one strip-shaped P + type second semiconductor region 6 and the insulating layer 7. The anode electrode 4 is in Schottky contact with the exposed portion of the n-type semiconductor base layer 1, and each of the plurality of strip-shaped P + -type semiconductor regions 3 and one strip-shaped P + -type second semiconductor region 6 is exposed. It is in ohmic contact with the part. The plurality of strip-shaped P + type semiconductor regions 3 and one strip-shaped P + type second semiconductor region 6 and the n-type semiconductor base layer 1 respectively form a pn junction.

Next, FIG. 2 is an enlarged constitutional view of the unit portion shown in FIG. 1 and an explanatory view showing the state of the energy band in the unit portion, wherein (a) is a line aa 'portion. 2B is an enlarged configuration diagram, and FIG. 3C is an energy band state of the line bb '.

In FIG. 2, the same components as those shown in FIG. 1 are designated by the same reference numerals. Note that FIG.
In (a) and (c), the horizontal axis represents the energy level and the vertical axis represents the depth from the exposed surface.

FIG. 3 is an operation characteristic diagram showing a recovery current state when the semiconductor rectifying device is turned off. The horizontal axis represents time and the vertical axis represents anode current.
The solid line is the characteristic of the first embodiment of the present invention, and the dotted line is the characteristic of the known one.

The operation of the first embodiment of the present invention will be described with reference to FIGS.

The feature of the first embodiment is that the pn junction consisting of the P + type semiconductor region 3 and the n type semiconductor base layer 1 is made of a semiconductor having a different band gap, and in particular, a P + type semiconductor. The region 3 is made of silicon (Si), and the n-type semiconductor substrate layer 1 is made of silicon carbide (SiC) having a wider band gap than silicon (Si).

In this case, a known semiconductor rectifying device, FIG.
As shown by a dotted line portion in (c), the pn junction is formed of a semiconductor having substantially the same bandgap, for example, both the P + type semiconductor region 3 and the n type semiconductor base layer 1 are made of silicon (S).
In the semiconductor rectifying device constituted by i), the energy barrier g ₀ to the n-type semiconductor substrate layer 1 for holes in the P + -type semiconductor region 3 is relatively small. Due to the injection of minority carriers (holes) into the semiconductor substrate layer 1 of the positive type, the residual carriers when the semiconductor rectifying element is turned off cannot be significantly reduced, and as shown by the dotted line in FIG. It was difficult to realize high-speed turn-off of the semiconductor rectifier due to the recovery current generated during turn-off.

On the other hand, the semiconductor rectifying device of the first embodiment has the following structure as shown by the solid line in FIG.
The pn junction is a semiconductor having a different band gap, specifically, the P + type semiconductor region 3 is made of silicon (Si), and the n type semiconductor base layer 1 is a silicon carbide having a band gap wider than silicon (Si). Since it is made of (SiC), the built-in potential at the pn junction becomes larger than the built-in potential of a known semiconductor rectifier, and P
The energy barrier g ₁ to the n-type semiconductor substrate layer 1 for holes in the + type semiconductor region 3 is considerably larger than the same energy barrier g ₀ of the known semiconductor rectifier. Therefore, the semiconductor rectifying device of the first embodiment is
Injection of minority carriers (holes) into the n-type semiconductor substrate layer 1 is significantly suppressed, and residual carriers when the semiconductor rectifying element is turned off can be significantly reduced, and as a result, the solid line in FIG. As shown in, the generation of the recovery current at the turn-off of the semiconductor rectifier can be significantly reduced as compared with the known semiconductor rectifier, and the turn-off of the semiconductor rectifier can be realized at a high speed. .

Next, FIG. 4 is a perspective view showing the essential structure of a second embodiment of the semiconductor rectifying device according to the present invention.

[0027] In FIG. 4, 3 ₁ is a P + type semiconductor connection region (semiconductor junction of the high impurity concentration of the second conductivity type), other, identical to the same components as those shown in FIG. 1 It is marked.

The P + type semiconductor connecting region 3 ₁ is
One surface is at the same level as the other surface of the n-type semiconductor substrate layer 1 and the other surface is a strip-shaped one reaching the inside of the n-type semiconductor substrate layer 1, The semiconductor regions 3 are arranged and connected to each other at one end thereof.

By the way, this second embodiment and the above-mentioned first embodiment
The third embodiment is different from the first embodiment in the arrangement configuration of the P + type semiconductor region 3 in the first embodiment, which is composed of a plurality of independent strips, which are arranged in the other side of the n type semiconductor base layer 1. In the second embodiment, a plurality of strips are connected by a P + type semiconductor connecting region 3 ₁ at one end, while they are arranged so as to form a stripe in the plane. The point that it is composed of a comb-like thing as a whole,
Regarding the P + type second semiconductor region 6, the first embodiment includes the second semiconductor region 6, while the second embodiment includes the second semiconductor region 6. In addition, there is no structural difference between the second embodiment and the first embodiment. Therefore, further description of the configuration of the second embodiment will be omitted.

Looking at the operation of the second embodiment, the configuration of the unit portion shown in FIG. 4 is exactly the same as that of the unit portion of the first embodiment described above. The operation of the unit portion of the second embodiment is almost the same as the operation of the same unit portion of the first embodiment described above, and the operational effects obtained in the second embodiment are the same as those of the first embodiment described above. Since the operation and effect obtained in the example are almost the same, detailed description of the operation of the second embodiment will be omitted.

However, in this second embodiment, n
Since the polygonal shape formed by the contact portion between the n-type semiconductor substrate layer 1 and the anode electrode 4 does not have an obtuse angle portion as an internal angle when viewed from the one main surface side of the n-type semiconductor substrate layer 1,
Compared with the first embodiment, the depletion layer formed when a reverse bias is applied at the pn junction at the corner portion is more likely to spread on the semiconductor base layer 1 side, which has the advantage of increasing the breakdown voltage of the semiconductor rectifying element.

Next, FIG. 5 is a perspective view showing the structure of the main part of a third embodiment of the semiconductor rectifying device according to the present invention.

In FIG. 5, the same components as those shown in FIG. 1 are designated by the same reference numerals.

The difference between the third embodiment and the above-described first embodiment is that the first embodiment includes a P + type semiconductor region 3 and a P + type second semiconductor region 6, respectively. It is made of a silicon (Si) material, and the n-type semiconductor base layer 1 and the n + -type semiconductor layer 2 are respectively made of a silicon carbide (SiC) material having a wider band gap than the silicon (Si). On the other hand, in the third embodiment, the n-type semiconductor base layer 1 and the n + -type semiconductor layer 2 are each made of a silicon (Si) material,
P + type semiconductor region 3 and P + type second semiconductor region 6
Is made of a silicon carbide (SiC) material having a band gap wider than that of silicon (Si), respectively. In addition, the third embodiment and the first embodiment
There is no difference in configuration from the embodiment of FIG. Therefore, the third
Further description of the configuration of the embodiment will be omitted.

FIG. 6 is an enlarged configuration diagram of the unit portion shown in FIG. 5 and an explanatory view showing the state of the energy band in the unit portion. FIG. 6A is a portion of line aa ′. The state of the energy band, (b) is an enlarged configuration diagram, and (c) is the state of the energy band of the line bb '.

In FIG. 6, the same components as those shown in FIG. 5 are designated by the same reference numerals. Note that FIG.
In (a) and (c), the horizontal axis represents the energy level and the vertical axis represents the depth from the exposed surface.

Further, FIG. 7 shows that in the third embodiment, P
FIG. 6 is an operation explanatory diagram showing the expansion of a depletion layer in a pn junction between a + type semiconductor region 3 and an n type semiconductor base layer 1.

In FIG. 7, the same components as those shown in FIG. 5 are designated by the same reference numerals.

Now, referring to FIG. 6 and FIG. 7, this third
The operation of this embodiment will be described.

The characteristic of the third embodiment is that a pn junction consisting of a P + type semiconductor region 3 and an n type semiconductor base layer 1 is provided on the contrary to the first embodiment. 1 is made of silicon (Si), and the P + type semiconductor region 3 is made of silicon carbide (SiC) having a bandgap wider than that of silicon (Si).

In this case, in the third embodiment, as shown in FIG.
As shown in (c), the energy barrier g2 for holes in the P + type semiconductor region 3 is kept equal to the energy barrier of a known silicon (Si) diode, and at the time of turn-off. When the high speed operation characteristic (turn-off characteristic) is kept equal to that of a known silicon (Si) diode, the relative position of the Fermi level Ef in the band gap is shown by the dashed line in FIG. 6 (c). As described above, the third embodiment uses silicon carbide (SiC) in the P + type semiconductor region 3 as compared with the case where a known silicon (Si) diode is used. As an example, the impurity concentration of the P + type semiconductor region 3 can be made higher than that of a known silicon (Si) diode using silicon (Si) for the P + type semiconductor region 3. Therefore, in the third embodiment, when the reverse bias voltage is applied, as shown in FIG. 7, the expansion h ₁ of the depletion layer into the P + type semiconductor region 3 is changed to a known silicon (Si) diode. Same P + type semiconductor region 3
The expansion of the depletion layer into the inside can be made smaller than h ₂ , while the expansion of the depletion layer into the n-type semiconductor substrate layer 1 h
₃ can be greater than the depletion layer spread h ₄ into the same n-type semiconductor body layer 1 of a known silicon (Si) diode. As a result, in the third embodiment,
Since the electric field strength of the Schottky junction portion sandwiched by the pn junctions is weakened and the barrier height of the Schottky junction is prevented from decreasing, the leak current at turn-off can be reduced.

Next, FIG. 8 is a sectional view showing the structure of the essential part of the fourth embodiment of the semiconductor rectifying device according to the present invention.

In FIG. 8, reference numeral 8 denotes an n + type second semiconductor layer (first conductivity type second semiconductor layer having a high impurity concentration), and other components are the same as those shown in FIG. Have the same sign.

The n + type second semiconductor layer 8 is disposed between the n type semiconductor base layer 1 and the anode electrode 4, and the n + type second semiconductor layer 8 and the anode electrode 4 are interposed therebetween. I try to make ohmic contact.

The difference between the fourth embodiment and the first embodiment described above is that the fourth embodiment has an n + type second layer between the n type semiconductor substrate layer 1 and the anode electrode 4. In contrast to the semiconductor layer 8 being interposed, the first embodiment is only that the n + type second semiconductor layer 8 is not interposed,
Besides, there is no structural difference between the fourth embodiment and the first embodiment. Therefore, further description of the configuration of the fourth embodiment will be omitted.

According to the fourth embodiment, silicon (S
i) Silicon carbide (Si) having a wider band gap than
On the other surface of the n-type semiconductor substrate layer 1 using C),
An n + type second semiconductor layer 8 having an impurity concentration higher than that of the n type semiconductor base layer 1 is arranged, and the n + type second semiconductor layer 8 is arranged.
Since ohmic contact is made between the anode electrode 4 and the anode electrode 4, in the fourth embodiment, in addition to the high-speed turn-off characteristic exhibited in the first embodiment, the forward voltage drop at turn-on is reduced. It has the advantage of being able to.

Next, FIG. 9 is a sectional view showing the structure of the essential part of a fifth embodiment of a semiconductor rectifying device according to the present invention.

In FIG. 9, reference numeral 9 is an n-type semiconductor layer (first conductivity type semiconductor layer having a low impurity concentration), and
The same components as those shown in FIG. 1 are designated by the same reference numerals.

The n-type semiconductor layer 9 is disposed between the n-type semiconductor substrate layer 1 and the anode electrode 4,
The thickness of the n− type semiconductor layer 9 is configured to be slightly smaller than the thickness of the p + type semiconductor region 3.

The difference between the fifth embodiment and the above-mentioned fourth embodiment is that the fourth embodiment has an n + -type second layer between the n-type semiconductor substrate layer 1 and the anode electrode 4. The fifth embodiment is different from the fifth embodiment in that the semiconductor layer 8 is interposed, and the n-type semiconductor layer 9 is interposed in the fifth embodiment. There is no difference in configuration from the embodiment. Therefore, further description of the configuration of the fifth embodiment will be omitted.

According to the fifth embodiment, the depletion layer of the n--type semiconductor layer 9 spreads more easily than that of the n-type semiconductor substrate layer 1. There is an advantage that the leak current at the time of applying the bias can be further reduced.

Next, FIG. 10 is a sectional view showing the structure of the essential part of a sixth embodiment of a semiconductor rectifying device according to the present invention.

In FIG. 10, reference numeral 10 denotes a thin metal layer made of a material different from the constituent material of the anode electrode 4 (thin layer of a metal material having a different barrier height), which is the same as the constituent elements shown in FIG. The components are given the same reference numerals.

The metal thin layer 10 is disposed between each p + type semiconductor region 3 and the anode electrode 4, and between the metal thin layer 10 and the p + type semiconductor region 3 and the anode electrode 4. Are configured to be in ohmic contact with each other.

The difference between the sixth embodiment and the first embodiment described above is that in the sixth embodiment, a thin metal layer 10 is arranged between the p + type semiconductor region 3 and the anode electrode 4. Whereas the first embodiment is such a thin metal layer 10
In addition, there is no structural difference between the sixth embodiment and the first embodiment. Therefore, further description of the configuration of the sixth embodiment will be omitted.

According to the sixth embodiment, the thin metal layer 10 made of a material different from that of the anode electrode 4 is interposed between the p + type semiconductor region 3 and the anode electrode 4, so that the sixth embodiment is provided. In the embodiment, the metal material of the portion forming the ohmic junction and the Schottky junction, that is, the material of the anode electrode 4 and the material of the thin metal layer 10 can be independently selected, and the barrier height of the Schottky junction can be selected. There is an advantage that the characteristics suitable for the application of the semiconductor rectifier can be selected by appropriately selecting.

Next, FIGS. 11A to 11D are pattern diagrams showing the essential structure of each of the seventh to tenth embodiments of the semiconductor rectifying device according to the present invention, which is an n-type semiconductor substrate. It is seen from the other side of layer 1.

In FIGS. 11A to 11D, the same components as those shown in FIG. 1 are designated by the same reference numerals.

Then, the seventh shown in FIG.
In this embodiment, a plurality of p <+>-type semiconductor regions 3 each having a substantially square shape and regularly arranged in an island shape are exposed and formed in the exposed surface of the n-type semiconductor substrate layer 1. 11
In the eighth embodiment shown in (b), a plurality of substantially circular p + -type semiconductor regions 3 regularly arranged in an island shape are exposed in the exposed surface of the n-type semiconductor base layer 1. The pattern shape is formed. On the other hand, in the ninth embodiment shown in FIG. 11 (c), a plurality of substantially square n-shaped elements arranged regularly in an island shape are arranged in the exposed surface of one p + type semiconductor region 3.
Type semiconductor substrate layer 1 is exposed, that is, in the exposed surface of the n type semiconductor substrate layer 1, a plurality of substantially square p + type semiconductor regions 3 are arranged regularly in an island shape. In the tenth embodiment shown in FIG. 11 (d), which has a pattern shape in which the missing portion is exposed and formed, one p
A pattern shape in which a plurality of substantially round n-type semiconductor base layers 1 regularly arranged in an island shape are exposed in the exposed surface of the + type semiconductor region 3, that is, an n-type semiconductor base layer In the exposed surface of 1, a plurality of substantially round p + s arranged regularly in an island shape
The pattern shape is such that a missing portion of the semiconductor region 3 of the mold is exposed. In addition, in any of the seventh to eighth embodiments, the configuration of the portion excluding the pattern shapes is the same as that of the first embodiment.

According to the seventh to tenth embodiments, n
In comparison with the first embodiment in which the exposed surface of the p + type semiconductor region 3 has a stripe shape in the exposed surface of the semiconductor substrate layer 1 of the positive type, the flow area of the forward current of the semiconductor rectifying element is wider. Since the current flowing per unit area can be reduced, the voltage drop inside the semiconductor rectifying element can be reduced, and a semiconductor rectifying element with a low on-voltage can be obtained.

According to the ninth and tenth embodiments,
Compared to the seventh and eighth embodiments, the shape of the missing portion of the p + type semiconductor region 3 is a polygonal shape without an obtuse angle or a shape that is convex outward, so that semiconductor rectification is performed. When a reverse bias voltage is applied to the device, the depletion layer easily expands on the side of the semiconductor substrate, which is the missing portion, and the electric field strength at this portion is significantly relaxed, suppressing an increase in leakage current at the Schottky junction. At the same time, there is an advantage that the breakdown voltage of the semiconductor rectifying device at the pn junction can be increased.

In each of the above embodiments, p
When a pn junction is formed by two semiconductors including the + type semiconductor region 3 and the n type semiconductor base layer 1, silicon (Si) is selected as the material of one semiconductor and silicon carbide ( Although an example of selecting (SiC) has been described, the present invention is not limited to the case of selecting the above-mentioned semiconductor material, and for example, silicon carbide (Si
Instead of selecting C), another semiconductor material having a bandgap wider than silicon (Si) may be selected.

[0063]

As described above, in the semiconductor rectifying device according to the present invention, the p + type semiconductor region 3 and the n type semiconductor base layer 1 forming the pn junction have different band gaps. It is composed of semiconductor materials.

In this case, the p + type semiconductor region 3 is made of silicon (Si), and the n type semiconductor base layer 1 has a wider band gap than silicon (Si) like silicon carbide (SiC). If it is made of a semiconductor, the built-in potential of the pn junction is increased, build-up of the pn junction can be prevented and injection of minority carriers into the n-type semiconductor base layer 1 can be prevented to the extent that the flow current increases. The turn-off can be performed at high speed without increasing the recovery current at the turn-off of the semiconductor rectifier.

On the other hand, the n-type semiconductor base layer 1 is made of silicon (Si), the p + -type semiconductor region 3 is a second conductivity type semiconductor region having a high impurity concentration, like silicon carbide (SiC). By using a semiconductor having a bandgap wider than that of silicon (Si), it is possible to increase the impurity concentration of the p + type semiconductor region 3, and a depletion layer of the depletion layer to the n type semiconductor base layer 1 is applied when a bias is applied. Since the expansion h ₃ becomes large and the electric field strength of the Schottky junction sandwiched by the pn junctions is weakened, it is possible to prevent the barrier height from being lowered when the reverse bias is applied to the semiconductor rectifying element and to reduce the leak current.

As described above, according to the semiconductor rectifying device of the present invention, the leak current can be reduced as compared with the known semiconductor rectifying device, or at a high speed even when a large current flows. The effect is that it can be turned off.

[Brief description of drawings]

FIG. 1 is a perspective view showing a configuration of a main part of a first embodiment of a semiconductor rectifier according to the present invention.

FIG. 2 is an enlarged configuration diagram of a unit portion shown in FIG. 1 and an explanatory diagram showing a state of an energy band in the unit portion.

FIG. 3 is an operating characteristic diagram showing a state of a recovery current when the semiconductor rectifying element is turned off.

FIG. 4 is a perspective view showing a main part configuration of a second embodiment of a semiconductor rectifying device according to the present invention.

FIG. 5 is a perspective view showing a configuration of a main part of a third embodiment of a semiconductor rectifying device according to the present invention.

6 is an enlarged configuration diagram of a unit portion shown in FIG. 5 and an explanatory diagram showing a state of an energy band in the unit portion.

7 is an operation explanatory diagram showing the expansion of a depletion layer in a pn junction between a P + type semiconductor region 3 and an n type semiconductor base layer 1 in the embodiment shown in FIG.

FIG. 8 is a cross-sectional view showing the main configuration of a semiconductor rectifying device according to a fourth embodiment of the present invention.

FIG. 9 is a cross-sectional view showing a main part configuration of a fifth embodiment of a semiconductor rectifier according to the present invention.

FIG. 10 is a sectional view showing the configuration of the main part of a sixth embodiment of a semiconductor rectifying device according to the present invention.

FIG. 11 is a seventh to first semiconductor rectifying device according to the present invention.
It is a pattern diagram which shows the principal part structure of the Example of 0.

[Explanation of symbols]

1 n-type semiconductor base layer (first conductivity type semiconductor base layer) 2 n + type semiconductor layer (first conductivity type high impurity concentration semiconductor layer) 3 P + type semiconductor region (second conductivity type high Impurity concentration semiconductor region) 4 Anode electrode (first main electrode) 5 Cathode electrode (second main electrode) 6 P + type second semiconductor region (second conductivity type high impurity concentration second semiconductor region) 7 Insulating Layer 8 n + -type Second Semiconductor Layer (First Conduction Type High Impurity Concentration Second Semiconductor Layer) 9 n− Type Semiconductor Layer (First Conduction Type Low Impurity Concentration Semiconductor Layer) 10 Metal Thin Layer (thin layer of metal material with different barrier height)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location 7376-4M H01L 29/48 G 29/91 C

Claims (9)

[Claims] 1. A semiconductor substrate layer of a first conductivity type, a semiconductor layer of a high impurity concentration of the first conductivity type, which is joined to one surface of the semiconductor substrate layer, and one surface of which is the other of the semiconductor substrate layer. And one or more second-conductivity-type high-impurity-concentration semiconductor regions that reach the inside of the semiconductor substrate layer and are exposed at the other surface of the semiconductor substrate layer. And a first main electrode which is in Schottky contact with the first conductivity type and is in ohmic contact with one surface of the second-conductivity-type high-impurity-concentration semiconductor region, and the first-conductivity-type high-impurity-concentration semiconductor layer A second main electrode, which forms a pn junction between the second conductive type high impurity concentration semiconductor region and the semiconductor base layer. Semiconductor region and the semiconductor A semiconductor rectifying device, characterized in that the base layer and the first-conductivity-type high-impurity-concentration semiconductor layer are made of semiconductor materials having different band gaps. 2. The semiconductor rectifying device according to claim 1, wherein the second-conductivity-type semiconductor region having a high impurity concentration is composed of a plurality of semiconductor regions arranged in a stripe shape. 3. The semiconductor rectifying device according to claim 1, wherein the second-conductivity-type high-impurity-concentration semiconductor region is composed of a plurality of semiconductor regions arranged regularly in an island shape. 4. The semiconductor region according to claim 1, wherein the second-conductivity-type high-impurity-concentration semiconductor region comprises one semiconductor region having a plurality of island-shaped regular cutouts. Rectifying element. 5. The semiconductor base layer has one surface at the same level as the other surface of the semiconductor base layer along the peripheral portion of at least a part of the semiconductor base layer on the other surface, and the other side. 4. The semiconductor rectifying device according to claim 1, wherein the surface of the semiconductor rectifying element has one strip-shaped second semiconductor region of a high impurity concentration of the second conductivity type that reaches the inside of the semiconductor base layer. 6. The semiconductor device according to claim 2, wherein each of the semiconductor regions arranged in a stripe shape has a second conductivity type semiconductor connection part having a high impurity concentration and interconnecting one end part. Rectifying element. 7. A second semiconductor layer having a high impurity concentration of the first conductivity type is interposed between the exposed portion of the other surface of the semiconductor base layer and the first main electrode. 7. The semiconductor rectifying device according to claim 1. 8. A third semiconductor having a low impurity concentration of the first conductivity type, which is slightly thinner than the thickness of each semiconductor region, between the exposed portion of the other surface of the semiconductor base layer and the first main electrode. The semiconductor rectifying device according to claim 1, wherein layers are interposed. 9. A thin layer of a metal material having a barrier height different from that of the first main electrode is interposed between each of the semiconductor regions and the first main electrode. The semiconductor rectifier according to any one of 1.