JPH0347592B2 - - Google Patents
Info
- Publication number
- JPH0347592B2 JPH0347592B2 JP60058950A JP5895085A JPH0347592B2 JP H0347592 B2 JPH0347592 B2 JP H0347592B2 JP 60058950 A JP60058950 A JP 60058950A JP 5895085 A JP5895085 A JP 5895085A JP H0347592 B2 JPH0347592 B2 JP H0347592B2
- Authority
- JP
- Japan
- Prior art keywords
- main surface
- layer
- impurity concentration
- semiconductor substrate
- main
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 230000007423 decrease Effects 0.000 claims 3
- 238000009792 diffusion process Methods 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は高速動作を行い、かつ高電圧に耐え得
る半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device that operates at high speed and can withstand high voltage.
半導体基体中での正孔、電子の再結合を早め、
高速動作を行わせる手法として、半導体基体中に
金等のライフタイムキラーを添加することが特公
昭36−7828号公報で紹介された。しかしながら、
ライフタイムキラーを添加すると漏洩電流、特に
高温下で漏洩電流が増加し、高耐圧が確保できな
い問題があつた。
Accelerates the recombination of holes and electrons in the semiconductor substrate,
Japanese Patent Publication No. 7828/1984 introduced the addition of a lifetime killer such as gold into a semiconductor substrate as a method for achieving high-speed operation. however,
When a lifetime killer is added, the leakage current increases, especially at high temperatures, and there is a problem that a high withstand voltage cannot be ensured.
ゲートターンオフサイリスタ等、特定のもので
は、特開昭57−178369号公報に示されるように、
pn接合構造を改良して、高速化しているものも
あるが、やはり高耐圧化が達成されていない。 For specific products such as gate turn-off thyristors, as shown in Japanese Patent Application Laid-open No. 178369/1983,
Although some devices have improved speed by improving the pn junction structure, high voltage resistance has not yet been achieved.
また、各種の半導体装置に適用できる技術は今
まで紹介されていなかつた。 Furthermore, no technology that can be applied to various semiconductor devices has been introduced until now.
本発明の目的は、高耐圧でかつ高速動作が可能
な半導体装置を提供するにある。
An object of the present invention is to provide a semiconductor device that has high breakdown voltage and can operate at high speed.
本発明の特徴とするところは、pn接合を形成
するｐ層に主動作領域で半導体基体の主表面と平
行な方向で不純物濃度勾配を与え、pn層の上記
主表面と平行な部分を不純物濃度勾配が与えられ
たｐ層部分より狭くしたことにある。
A feature of the present invention is that an impurity concentration gradient is given to the p-layer forming the p-n junction in a direction parallel to the main surface of the semiconductor substrate in the main operating region, and the impurity concentration gradient is applied to the part of the p-n layer parallel to the main surface. The reason is that it is narrower than the p-layer portion where the slope is given.
第１図は本発明をゲートターンオフサイリスタ
（以下GTOと略記）に適用した一実施例を示し、
ａはカソード側平面、ｂはａの−切断線に沿
つた縦断面、ｃはａの−切断線に沿つた横断
面である。
FIG. 1 shows an embodiment in which the present invention is applied to a gate turn-off thyristor (hereinafter abbreviated as GTO).
a is a plane on the cathode side, b is a vertical cross section along the -cutting line of a, and c is a cross section along the -cutting line of a.
１はシリコン基体で、相互に導電型が異なる４
枚の半導体層、即ち、下側主表面から上側主表面
に向つて順にｐエミツタ層２、ｎベース層３、ｐ
ベース層４そしてｎエミツタ層５を有している。
ｎエミツタ層５は短冊状に分割され、ｐベース層
４で取囲まれている。ｐエミツタ層２にはアノー
ド電極６、ｐベース層４にはｎエミツタ層５をほ
ぼ取囲むようにゲート電極８、そして、ｎエミツ
タ層５にはカソード電極７が低抵抗接触されてい
る。９は上側主表面に設けられたシリコン酸化膜
で中央接合J2、カソード側エミツタ接合J3の表面
安定化膜である。第１図ａではこのシリコン酸化
膜は省略されている。カソード電極７の一部７ａ
はシリコン酸化膜９上にあつて、指状部７ｂを橋
絡している。ｐエミツタ層２はｎエミツタ層５の
幅方向中央直下で厚さが最も薄くなつている。 1 is a silicon substrate, and 4 has mutually different conductivity types.
In order from the lower main surface to the upper main surface, the p emitter layer 2, the n base layer 3, the p
It has a base layer 4 and an n-emitter layer 5.
The n emitter layer 5 is divided into strips and surrounded by the p base layer 4. An anode electrode 6 is connected to the p emitter layer 2, a gate electrode 8 is connected to the p base layer 4 so as to substantially surround the n emitter layer 5, and a cathode electrode 7 is connected to the n emitter layer 5 with low resistance. 9 is a silicon oxide film provided on the upper main surface and is a surface stabilizing film for the central junction J 2 and the cathode side emitter junction J 3 . In FIG. 1a, this silicon oxide film is omitted. Part 7a of cathode electrode 7
is on the silicon oxide film 9 and bridges the finger-like portions 7b. The p emitter layer 2 is thinnest just below the center of the n emitter layer 5 in the width direction.
第２図は第１図ｃの右側半分の構造を示してお
り、計算により設計したモデルGTOの寸法およ
び半導体基体１内、特に、ｐエミツタ層２、ｐベ
ース層４における不純物濃度分布を示している。
モデルGTOの半分の幅l1は50μｍ、ｎエミツタ層
５の半分の幅l2は10μｍ、ｐエミツタ層２を選択
拡散で形成する時のボロンのデポジシヨン領域の
幅l3は5μｍ、それによつてできるｐエミツタ層２
の最大深さl4は60μｍ、ｐベース層４の拡散深さl6
は60μｍ、ｎベース層３の最小厚さl5は280μｍで
ある。 FIG. 2 shows the structure of the right half of FIG. There is.
The half width l1 of the model GTO is 50 μm, the half width l2 of the n emitter layer 5 is 10 μm, and the width l3 of the boron deposition region when forming the p emitter layer 2 by selective diffusion is 5 μm. p emitter layer 2
The maximum depth l 4 is 60 μm, the diffusion depth l 6 of the p base layer 4
is 60 μm, and the minimum thickness l 5 of the n-base layer 3 is 280 μm.
ｐエミツタ層２、ｐベース層４の表面最大不純
物濃度を７×1017atoms／cm3とし、ボロンの横方
向拡散は縦方向拡散の80％まで生ずるものとし
た。又、ボロンをデポジシヨンしない幅をチヤネ
ル幅Xch The maximum surface impurity concentration of the p emitter layer 2 and the p base layer 4 was set to 7×10 17 atoms/cm 3 , and the horizontal diffusion of boron was assumed to be 80% of the vertical diffusion. Also, the width without boron deposition is channel width x ch
Claims (1)
とそれに隣接するＮ層とを有する半導体基板と、
半導体基板の一方の主表面においてＰ層に接触す
る一方の主電極と、半導体基体の他方の主表面に
設けた他方の主電極とを備えるものにおいて、Ｐ
層は一方の主表面において不純物濃度勾配を有す
る第１の部分とその両側に位置し厚さが均一で一
方の主表面における不純物濃度が第１の部分のそ
れより高くかつ均一な第２の部分とを有し、第１
の部分は厚さ及び一方の主表面における不純物濃
度が第２の部分から離れるに従つて減少しその略
中央部で最低になつており、一方の主表面におけ
る第１の部分の面積が第２の部分のそれより大き
いことを特徴とする半導体装置。 ２ 上記Ｐ層が、上記一方の主表面において上記
第２の部分とそれを包囲する上記第１の部分とを
最小単位とし、これを並設することによつて形成
されていることを特徴とする特許請求の範囲第１
項記載の半導体装置。[Claims] 1. A semiconductor substrate having a pair of main surfaces, a P layer adjacent to one main surface, and an N layer adjacent thereto;
A device comprising one main electrode in contact with the P layer on one main surface of the semiconductor substrate, and the other main electrode provided on the other main surface of the semiconductor substrate,
The layer includes a first part having an impurity concentration gradient on one main surface, and a second part located on both sides of the first part having a uniform thickness and having an impurity concentration on one main surface higher than that of the first part and uniform. and the first
The thickness of the part and the impurity concentration on one main surface decrease as the distance from the second part decreases, and the area of the first part on one main surface decreases to the minimum at approximately the center. A semiconductor device characterized in that it is larger than that of a part of. 2. The P layer is formed by arranging the second portion and the first portion surrounding the second portion in parallel on the one main surface. Claim 1
1. Semiconductor device described in Section 1.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5895085A JPS61218171A (en) | 1985-03-23 | 1985-03-23 | Semiconductor device |
| EP85112805A EP0178582A3 (en) | 1984-10-15 | 1985-10-09 | Reverse blocking type semiconductor device |
| US06/787,116 US4713679A (en) | 1984-10-15 | 1985-10-15 | Reverse blocking type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5895085A JPS61218171A (en) | 1985-03-23 | 1985-03-23 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61218171A JPS61218171A (en) | 1986-09-27 |
| JPH0347592B2 true JPH0347592B2 (en) | 1991-07-19 |
Family
ID=13099105
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5895085A Granted JPS61218171A (en) | 1984-10-15 | 1985-03-23 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61218171A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63202967A (en) * | 1987-02-19 | 1988-08-22 | Hitachi Ltd | Semiconductor device |
| JP5460247B2 (en) * | 2009-11-10 | 2014-04-02 | 新電元工業株式会社 | Thyristor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57178369A (en) * | 1981-04-28 | 1982-11-02 | Meidensha Electric Mfg Co Ltd | Gate turnoff thyristor |
-
1985
- 1985-03-23 JP JP5895085A patent/JPS61218171A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57178369A (en) * | 1981-04-28 | 1982-11-02 | Meidensha Electric Mfg Co Ltd | Gate turnoff thyristor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS61218171A (en) | 1986-09-27 |
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