JPS62290179A - Gate turn-off thyristor - Google Patents

Abstract

PURPOSE:To contrive the improvement of a turn-off dielectric strength while keeping a low on-voltage, by using a wafer having a bonding boundary in a predetermined position in a D-base layer and utllizing a direct bonding technique. CONSTITUTION:By using a wafer made of two semiconductor substrates bonded directly, a direct bonding boundary 16 exists in first conductivity type base layers 13 and 15 and a distance between this boundary and a second conductivity emitter layer 17 is made 30mum or shorter. In such structure, a maximum impurity concentration part of the first conductivity type base layers 13 and 13 can be arranged in the position distant from a bonding plane between the second conductivity emitter layer 17 and the first conductivity base layer 15. As a result, although a lateral-direction resistance of the first conductivity base layers 13 and 15 which is to be a passage of a gate current is virtually reduced, an impurity concentration of a bonding part between the first conductivity type base layer 15 and the second conductivity type emitter layer 17 is low and a breakdown voltage in the bonding part is high. Also, an emitter injection efficiency can be made high and an on-voltage is low and a turn-off breakdown strength is high.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Purpose of the Invention (Industrial Field of Application) The present invention uses a wafer obtained by bonding two semiconductor substrates by direct bonding technology. This invention relates to a gate turn-off switch (hereinafter referred to as GTO).

(Prior Art) In general, GTOs enable turn-on and turn-off by applying a positive or negative bias to the gate electrode, so a rectifier circuit is not required, and the switching time is short, so GTOs can operate at high frequencies. It has the advantage of - 10,000 GTOs cause thermal breakdown when the power loss at turn-off reaches a certain value, so there is a limit to the anode current that can flow, and that value is about 200 OA at most, which has a lower current capacity than a normal thyristor. The drawback is that it cannot be made larger. The reason for this is that local current concentration occurs when the GTO is turned off. In order to alleviate this phenomenon, a multi-emitter structure is usually used, that is, a structure in which the cathode region is divided and a plurality of small GTOs (referred to as GTO elements) are connected in parallel. As a result, the current concentration points are dispersed, so that the current capacity can be increased to some extent.

However, even if the above-mentioned improvements are made, the above-mentioned current concentration occurs in each GTO element, so the essential problem cannot be solved. During turn-off, the balance of anode current between each GTO element is disrupted, and at the end of the turn-off process, current concentration occurs in one or several GTO elements, destroying them. One of the reasons for this is that with current process technology, it is difficult to uniformly diffuse impurities over the entire surface of a wafer with a diameter of 40 m or more and to achieve a uniform lifetime. The second reason is that the turn-off breakdown resistance of each GTO element is insufficient.

In order to solve this problem, it has been proposed to reduce the sheet resistance of the p-based GTO and increase the junction breakdown voltage between the n-emitter layer and the n-base layer (Japanese Patent Laid-Open No. 1983-1973-1).
110386). It has also been proposed to form the n-base layer by an epitaxial method in order to make it a low-resistance, uniform impurity concentration layer (Japanese Unexamined Patent Publication No. 52-1026
Publication No. 87).

By the way, in order to make the sheet resistance of the n-base layer sufficiently small, its width needs to be about 30 μm or more.

Further, the width of the n emitter layer formed by diffusion in the n base layer needs to be about 20 μm or more in order to obtain sufficient injection efficiency. In this case, in order to form the n-base layer by epitaxial growth, the epitaxial growth layer needs to have a thickness of 50 μm or more. However, since epitaxial growth is performed at a high temperature of about 1300° C., defects are formed in the n-base layer of the substrate during this step, which leads to a reduction in lifetime and an increase in the on-state voltage of the GTO. Furthermore, when an epitaxially grown layer of 40 μm or more is formed, many defects are generated within the grown layer, which also reduces the lifetime of the n-base layer, which also causes an increase in the on-state voltage of the GTO.

(Problems to be Solved by the Invention) As described above, in the conventional GTO, when an attempt is made to increase the turn-off breakdown strength using the epitaxial method, there is a problem in that the on-voltage increases.

The present invention solves these problems and
It is an object of the present invention to provide a GTO with high ff1 and low on-voltage.

[Configuration of the Invention (Means for Solving Problems) The GTO according to the present invention is constructed using a wafer obtained by directly bonding two semiconductor substrates, and includes a first conductivity type emitter layer, a first conductivity type emitter layer, and a first conductivity type emitter layer. 2 conductivity type base layer.

It has a first conductivity type base layer and a second Q conductivity type emitter layer divided into a plurality of parts in the first conductivity type base layer, and has a direct adhesive interface in the first conductivity type base layer. and the distance between this interface and the second conductivity type emitter layer is 30 μm or less.

(Function) In such a GTO structure, the first conductivity type emitter layer is located away from the junction surface between the second conductivity type emitter layer and the first conductivity type base layer.
A portion of maximum impurity concentration of the conductivity type base layer can be provided. This is because it is possible to easily make the direct bonding interface the maximum impurity concentration portion. As a result, even though the lateral resistance of the first conductivity type base layer through which the gate current passes is substantially reduced, the junction between the first conductivity type base layer and the second conductivity type emitter layer The impurity concentration of is low, the breakdown voltage at this junction can be made high, and the emitter injection efficiency can be made high.

Therefore, with this structure, a GTO with low on-voltage and high turn-off breakdown resistance is realized.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing a GTO according to an embodiment. This structure will be explained in the order of steps with reference to step-by-step cross-sectional views shown in FIGS. 2(a) to 2(C). In this embodiment, n type is used as the first conductivity type, and n type is used as the second conductivity type.

First, as shown in Figure 2 (a), two high-resistance n-type S
Prepare i-boards 11 and 14. The surfaces of these substrates to be bonded to each other are mirror polished to a surface roughness of 500 or less. One of the n-type S1 substrates 11 is used as an n-base layer, and a p-type impurity such as boron or gallium is diffused into the surface to be bonded to a thickness of 10 to 10 cm to form a part of the n-base layer. A first n base layer 13 of 100 μm is formed. Further, on the surface opposite to the surface to be bonded, an n emitter layer 12 having a thickness of 30 to 150 μm is formed by diffusion. On the surface of the other n-type 3i substrate 14 to be bonded, a second n base layer 15 with a thickness of 10 to 100 μm is diffused and formed. Depending on the surface condition of these two substrates, H2O2 + H2SO4 → HF → rare HF
Degreasing and stain film removal are performed in the pretreatment process. Next, each substrate is washed with clean water for several minutes and dried on a spinner at room temperature. In this step, excess moisture is removed while leaving any moisture that seems to be adsorbed on the surface of the substrate to be bonded.

Therefore, avoid heating and drying at temperatures above 100°C, where most of the adsorbed moisture will evaporate.

Two substrates that have undergone such treatment are placed in a clean atmosphere of class 1 or lower, for example, and the polished surfaces are aligned with each other as shown in Figure 2 (b), with no foreign matter present on each mirror-polished surface. contact. Then, the adhered substrates are heat-treated at 200° C. or higher, preferably 1000 to 1200° C., to obtain directly bonded substrates. 16 is a direct adhesive interface.

Note that the thickness of the n-type Si substrate 11 is determined by the thickness of the high-resistance n base layer, and is, for example, about 800 μm for a 4.5 KV breakdown voltage device. Further, the thickness of the n-type 3i substrate 14 is set to be approximately 300 μm or more in consideration of ease of bonding work.

The n-type 3i substrate 14 of the adhesive substrate formed in this way
The thickness on the adhesive interface 16 is set to about 50 μm by polishing the side, and then, as shown in FIG.
An emitter layer 17 is formed. As a result, the actual second
A pnpn wafer is obtained in which the width W of the n base layer 15 (that is, the distance from the adhesive interface 16 to the bonding surface of the n emitter layer 17) is 30 μm or less.

Thereafter, the n-emitter layer 17 is etched and divided into a plurality of layers by a known method, and the cathode electrode 17 is divided into a plurality of layers as shown in FIG.
8. Gate electrode 19. Anode electrode 20 and protective film 21
etc., and the GTO is completed.

FIG. 3 shows the impurity concentration distribution of GTO according to this example. As is clear from the figure, the n-base layer is formed between the first p-base@13 and the second n-base layer 15, that is, at the adhesive interface 16.
There is a region of maximum impurity concentration nearby. The p-type impurity concentration decreases from the adhesive interface 16 toward the n emitter layer 17, and the n emitter layer 17 is formed at a distance of W-30 um or less from the adhesive interface 16.

In this embodiment, the sheet resistance ρ8PB of the n-base layer is less than 5 oΩ/unit, and a sufficiently high turn-off breakdown strength can be obtained. Furthermore, the impurity content in the portion behind the n-base layer and near the n-emitter layer is sufficiently low, and the injection efficiency from the n-emitter layer is high.

This, combined with the fact that W is 30 μm or less,
With this GTO, a sufficiently large αnpn can be obtained and a low on-voltage can be obtained. It is already known that there is a relationship between αnpn and on-voltage, in which the larger αII p 11 is, the lower the on-voltage becomes (for example, F, E, Gentry.

“Sem1conductor Controller
dRectifiers”, Prentice
-Hall, rNC.

[:nglewood Cl! ffs, New
Jersey, 1964゜pp, 103-108
).

FIG. 4 shows the results of measuring αnpn in a GTO made by changing the final width W of the second n base layer 15 and using its sheet resistance as a parameter in the above embodiment.

The broken line represents data obtained by the conventional method in which the n-base layer was formed by diffusion from the surface of the wafer. As is clear from the figure, when W exceeds 30 μm, αnpn decreases rapidly.

This is the junction (J3) between the n emitter layer and the p base layer
Because the nearby p-type impurity concentration is lower than the p-type impurity concentration at the adhesive interface, if ~V is too large, the drift electric field for electrons injected from the n-emitter layer becomes small, and the electron transport efficiency decreases. It is. If W is 30 μm or less, there is no such decrease in αnpn, and therefore a sufficiently low on-voltage can be obtained.

Note that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, by using a wafer using direct bonding technology that has an adhesive interface at a predetermined position in the p base layer, turn-off breakdown resistance can be increased while maintaining a low on-voltage. You can get rid of the improved GTO by 1.

[Brief explanation of drawings]

Fig. 1 is a sectional view showing a GTO according to an embodiment of the present invention;
Figures (a) to (C) are cross-sectional views of the GTO manufacturing process.
The figure also shows the impurity concentration distribution of the GTO.
The figure shows the p base layer width and αn for detailed explanation of the present invention.
It is a figure which shows the relationship of pn. 11-n-type 3i substrate (n-base 1il), 12-...
n emitter layer, 13...first p base layer, 14...
・n-type S; substrate, 15... second p base layer, 16
...adhesive interface, 17:...n emitter layer, 18...
Cathode electrode, 19... Gate electrode, 20... Anode electrode, 21... Protective film. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 3 Figure 'Attack 2 Darkness

Claims (1)

[Claims] It is constructed using a wafer obtained by bonding two semiconductor substrates using a direct bonding technique, and includes a first conductivity type emitter layer,
In the gate turn-off thyristor, the gate turn-off thyristor includes a second conductivity type base layer, a first conductivity type base layer, and a second conductivity type emitter layer divided into a plurality of parts in the first conductivity type base layer. A gate turn-off thyristor having a direct adhesive interface in the base layer, and a distance between the adhesive interface and the second conductivity type emitter layer is 30 μm or less.