JPS60198778A - Switching element - Google Patents

Switching element

Info

Publication number
JPS60198778A
JPS60198778A JP5417484A JP5417484A JPS60198778A JP S60198778 A JPS60198778 A JP S60198778A JP 5417484 A JP5417484 A JP 5417484A JP 5417484 A JP5417484 A JP 5417484A JP S60198778 A JPS60198778 A JP S60198778A
Authority
JP
Japan
Prior art keywords
lifetime
base
region
junction
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5417484A
Other languages
Japanese (ja)
Other versions
JPH0640581B2 (en
Inventor
Junko Akagi
赤木 順子
Mamoru Kurata
倉田 衛
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP59054174A priority Critical patent/JPH0640581B2/en
Publication of JPS60198778A publication Critical patent/JPS60198778A/en
Publication of JPH0640581B2 publication Critical patent/JPH0640581B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1012Base regions of thyristors
    • H01L29/1016Anode base regions of thyristors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thyristors (AREA)

Abstract

PURPOSE:To reduce Qrr by softening the reverse recovery characteristic by a method wherein the lifetime is made ununiform in the region with lower impurity concentration of two regions of different conductivity which form P-N junctions where most of reverse voltage is impressed at the time of turn-off operation. CONSTITUTION:An N type Si is put into the P-N-P three layer structure with a P-emitter 12, an N-base 11, and a P-base 13 by diffusing a P type impurity from both surfaces. Next, an N-emitter 14 is formed on the base 13 by diffusion of POCl3, etc. At the time of diffusing a lifetime killer, the lifetime killer is enabled to reach only part of the base by controlling the time and the diffusion temperature; then, only a region in the base 11 close to the emitter 12 is provided with a region where the lifetime decreases. Such a manner causes less accumulation of carriers at the time of on-operation, and they are swiftly exhausted. As a result, the reverse recovery characteristic is softened without deteriorating the ON-characteristic; further, Qrr can be reduced.

Description

【発明の詳細な説明】 〔発明の嬌する技術分野〕 本発明はサイリスタ、ダイオード等のスイッチング素子
の改良に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to improvements in switching elements such as thyristors and diodes.

〔従来技術とその問題点〕[Prior art and its problems]

高耐圧のサイリスタやダイオードなどは各種の電力変換
装置に使用されている。しかし、それらの素子が高耐圧
になればなる程装置内におけるそれら素子に対する保護
回路が大きくなり、装置の大型化あるいはコストアップ
につながる。また回路内のりアクタンスによる逆起電力
に対する安全性のために必要以上の高耐圧素子を使うこ
とが要求される場合もでてくる。
High-voltage thyristors and diodes are used in various power conversion devices. However, the higher the voltage resistance of these elements, the larger the protection circuit for those elements within the device becomes, leading to an increase in the size and cost of the device. In addition, there are cases where it is necessary to use a higher voltage element than necessary for safety against back electromotive force caused by actance in the circuit.

以上のことをさけるためKは素子のターンオフ特性の改
良、4!!F K (13、逆回復特性のソフト化、(
2)。
To avoid the above, K is improvement of the turn-off characteristics of the element, 4! ! F K (13, Softening of reverse recovery characteristics, (
2).

逆回復電荷Qrrのばらりきを小さくするの2点が重要
である。(2)のQrrのばらつきを小さくすることは
・Qrrの値そのものを小さくすることで達成できると
考える。これらの特性は素子の内部の構成によりきまる
ことが多い。逆回復特性は低不純物層をより高抵抗化し
、その厚みを増すことによりややソフト化の傾向がある
ことが知られている。
Two points are important: reducing the dispersion of the reverse recovery charge Qrr. We believe that reducing the variation in Qrr in (2) can be achieved by reducing the value of Qrr itself. These characteristics are often determined by the internal structure of the element. It is known that the reverse recovery characteristics tend to become slightly softer by making the low impurity layer higher in resistance and increasing its thickness.

しかしながらこれはオン電圧の大巾な上昇を招きそのた
め高耐圧素子においては低抵抗層の不純物濃度及び厚み
は設計上の余裕がなく、前記方法は現実には使うのが困
難である。
However, this causes a large increase in the on-voltage, and therefore, in high voltage devices, there is no margin in the design of the impurity concentration and thickness of the low resistance layer, making it difficult to use the above method in reality.

〔発明の目的〕[Purpose of the invention]

本発明は上記欠点に鑑みなされたもので、他の特性を損
うことなく、逆回復特性をソフト化しさらにQrrを小
さくすることである。
The present invention was made in view of the above-mentioned drawbacks, and it is an object of the present invention to soften the reverse recovery characteristic and further reduce Qrr without impairing other characteristics.

〔発明の概要〕[Summary of the invention]

本発明は次の数値計算の結果に基づいたものである。 The present invention is based on the results of the following numerical calculations.

まず、従来のサイリスタが第1図の回路(1社SCa、
2はL、3は電源VBである)でターンオフした場合の
シミュレーション結果を示す。サイリスタ内部は一次元
jxac tモデルを使った。計算に用いたサイリスタ
は第2図のような不純物プロファイルをもつものとする
。この第2図に示すサイリスタは、先ず不純物濃度2.
4X1018/cd 、厚さ1000μmのn−8i基
板に両面よりp型不純物を110μm程度拡散し、表面
不純物濃度lXlO19〜のpエミッタ(ロ)及びpベ
ース0$となるpmを形成する。この後、pベース(2
)となるp層表面を55μm程度エツチングし、pベー
ス(Llを45μmとしその表面から20μm程度n型
不純物を拡散して表面不純物濃度lXl0”/m程度の
nエミンタα◆を形成したものである。このサイリスタ
の少数キャリアアライフタイムはnベース(ロ)では6
0μSecの領域では1.5μsecとする。素子の大
きさは4゜dとし、100 A/mのオン状態の素子に
逆電圧500v印加し、dI/d t = 10 A/
 μsecでターンオフさせる。そのときの電流電圧及
び素子内部における正孔分布を第3図+a) 、 lb
)に示す。第3図(b)において、H】がt =、O、
(o)がt = 425μsec 、(ハ)がt=43
5.5μSeeの時である。nベース、pエミッタ接合
付近のキャリア蓄積量が多く、空乏層が広かって逆電流
最大値をとるまでに多大な時間が必要である。そのため
逆回復特性がソフトでなくQrrも大きくなっている。
First, the conventional thyristor has the circuit shown in Figure 1 (one company SCa,
2 is L and 3 is the power supply VB), the simulation results are shown. A one-dimensional jxact model was used inside the thyristor. It is assumed that the thyristor used in the calculation has an impurity profile as shown in FIG. The thyristor shown in FIG. 2 has an impurity concentration of 2.
A p-type impurity is diffused by about 110 μm from both sides of an n-8i substrate of 4×10 18 /cd and 1000 μm thick to form a p emitter (b) with a surface impurity concentration of lXlO19 and a p base of 0 $. After this, p base (2
), the p-layer surface is etched by about 55 μm, and an n-type impurity is diffused about 20 μm from the surface of the p base (Ll is 45 μm) to form an n-emitter α◆ with a surface impurity concentration of about lXl0”/m. .The minority carrier lifetime of this thyristor is 6 on n base (b).
In the 0 μSec region, it is set to 1.5 μsec. The size of the element was 4°d, a reverse voltage of 500V was applied to the element in the on state of 100 A/m, and dI/d t = 10 A/
Turn off in μsec. The current voltage and hole distribution inside the device at that time are shown in Figure 3+a), lb
). In FIG. 3(b), H] is t =, O,
(o) is t = 425μsec, (c) is t = 43
This is the time of 5.5μSee. There is a large amount of carrier accumulation near the n-base and p-emitter junctions, and the depletion layer is wide, so it takes a long time for the reverse current to reach its maximum value. Therefore, the reverse recovery characteristics are not soft and the Qrr is also large.

次に上述したモデルについて計算した結果を示す。上記
従来サイリスタと同じ不純物プロファイルをもち、少数
キャリアライフタイムが第4図のような分布をもつサイ
リスタについて、前記と同様な条件のもとにターンオフ
の計算を行った。そのときの計算結果を第5図1a) 
、 (b)に示す。
Next, the results of calculations for the above-mentioned model will be shown. Turn-off was calculated under the same conditions as above for a thyristor having the same impurity profile as the conventional thyristor and having minority carrier lifetime distribution as shown in FIG. 4. The calculation results at that time are shown in Figure 5 1a)
, shown in (b).

第3図(a)と比較するまでもなく第5図(atは逆回
復特性がソフトでありQrrも小さく良好なオフ特性を
示している。これは第5図(b)と第3図(b)を比較
するとわかりやすい。第5図(b) において、げ)が
t=o、10】がt、=406μsec 、(ハ)がt
=413.5μsecの時である。サイリスタの逆回復
特性に最も影響を及すのはnベース・pエミッタ接合近
傍のオン状態の過乗りキャリアの蓄積状態である。同一
電流密度でもこの部分の過乗り忠ヤリアの蓄積が小さい
と、上記接合(これは逆電圧の大半が印加される接合で
ある)における空乏層がはやい時間に形成され、その部
分でのキャリア排出も短時間で行われる。その結果逆電
流最大値に達する時間が短く逆回復特性がソフトになり
さらKQrrも小さくなる。
Needless to compare with Fig. 3(a), Fig. 5(at) has a soft reverse recovery characteristic and a small Qrr, showing good off-characteristics. It is easy to understand by comparing b). In Fig. 5(b), ge) is t = o, 10] is t, = 406 μsec, and (c) is t.
=413.5 μsec. What most influences the reverse recovery characteristics of the thyristor is the accumulation of overridden carriers in the on-state near the n-base/p-emitter junction. Even if the current density is the same, if the accumulation of overriding energy in this part is small, a depletion layer in the above junction (this is the junction to which most of the reverse voltage is applied) is formed quickly, and carriers are discharged in that part. is also done in a short period of time. As a result, the time required for the reverse current to reach its maximum value is shortened, and the reverse recovery characteristics become softer, and KQrr also becomes smaller.

第6図に低ライフタイム層におけるライ7タイムの値と
逆回復特性のソフト性S (tb/la・・・・・イ)
Qrr(ロ)、それにオン電圧VON(ハ)の関係を示
す。低ライフタイム層の2イアタイムの値が他のnベー
ス領域のライフタイムの値の174以下になれば。
Figure 6 shows the value of life time in the low lifetime layer and the softness of the reverse recovery characteristic S (tb/la...a)
The relationship between Qrr (b) and on-voltage VON (c) is shown. If the value of 2 ear time of the low lifetime layer becomes 174 or less of the lifetime value of other n base regions.

ソフト性が1.25倍程度となりかなり、逆回復特性が
改善したといえる。また、ライフタイムが1150 以
下だとオン電圧が大きくなり通電時のパワーロスが大き
くなるため実用化にはむかない。
The softness was approximately 1.25 times greater, which means that the reverse recovery characteristics have improved considerably. Furthermore, if the lifetime is less than 1150, the on-voltage increases and the power loss during energization increases, making it unsuitable for practical use.

従って低ライフタイム層のライフタイムの値は他のNペ
ース層ライフタイムの1/4〜1150 カよい。
Therefore, the lifetime value of the low lifetime layer is 1/4 to 1150 times better than the lifetime of other N-pace layers.

また逆回復特性に影響を与えるのは殆どNベースPエミ
ッタ接合付近の逆電圧印加時に空乏層が広がる領域にお
けるキャリア蓄積状態であるため。
Furthermore, what influences the reverse recovery characteristics is mostly the carrier accumulation state in the region where the depletion layer expands when a reverse voltage is applied near the N-base P emitter junction.

低ライフタイム層は逆電圧印加により形成される空乏層
の中以上あることが有効である。従って、低ライフタイ
ム層は少なくとも所定逆電圧により形成される空乏層の
巾は必要である。さらにリアクタンスによる逆起電力は
定格耐圧のHにはおさえねばならないので、素子(サイ
リスタ)には定格耐圧の%以上の逆耐圧が印加されない
と考えられる。そこで逆回復特性を決めるキャリア藁積
状態は定格耐圧のHの逆耐圧によって生ずる空乏層の幅
より外側の領域では特性に大きく影響しないと考えられ
るので、低ライフタイム層は広くとも定格耐圧のHの逆
電圧による生ずる空乏層の終端より内側にあれば良い。
It is effective for the low lifetime layer to exist in the middle or more of the depletion layer formed by applying a reverse voltage. Therefore, the low lifetime layer requires at least the width of the depletion layer formed by a predetermined reverse voltage. Furthermore, since the back electromotive force due to the reactance must be suppressed to H, which is the rated withstand voltage, it is considered that a reverse withstand voltage of % or more of the rated withstand voltage is not applied to the element (thyristor). Therefore, it is considered that the carrier accumulation state that determines the reverse recovery characteristics does not greatly affect the characteristics in the region outside the width of the depletion layer caused by the reverse breakdown voltage of the rated breakdown voltage H, so the low lifetime layer is wide even if the rated breakdown voltage H It suffices if it is located inside the end of the depletion layer caused by the reverse voltage.

〔発明の効果〕〔Effect of the invention〕

本発明を用いると、・第5図(b)のようにオン時のヤ
ヤリア蓄積が少なく、また蓄積キャリアの排出のはやい
ものが得られる。その結果、従来例に比較しオン特性を
悪化させることなく、逆回復特性をソフト化し、さらに
Qrrt−小さくした素子が実現できる。
By using the present invention, as shown in FIG. 5(b), it is possible to obtain a device in which there is less accumulation of carriers when on, and the accumulated carriers are quickly discharged. As a result, it is possible to realize an element with softer reverse recovery characteristics and a smaller Qrrt without deteriorating the on-characteristics compared to the conventional example.

〔発明の実施例〕[Embodiments of the invention]

以下図面を使用して本発明の一実施例を説明する。第7
図は本発明の一実施例のサイリスタの断面図である。製
造方法としてはまずn型Siに両面からGa等のp型不
純物を拡散し、pエミッタ@。
An embodiment of the present invention will be described below using the drawings. 7th
The figure is a sectional view of a thyristor according to an embodiment of the present invention. The manufacturing method is to first diffuse p-type impurities such as Ga into n-type Si from both sides to form a p-emitter @.

nベース(6)、pベース(2)のpnp三層構造とす
る。
It has a pnp three-layer structure of n base (6) and p base (2).

次にpベース(至)の上にPOCl3等の拡散によりn
エミッタ(ロ)を形成する。従来例ではこの4層形成後
pエミッタ(6)側からAu等のライフタイムキラーを
拡散することによりnベース@内のライフタイムをほぼ
均一な値にする。しかし本発明ではたとえばAuなどの
ライフタイムキラーを拡散する際に。
Next, by diffusing POCl3 etc. on the p base (to), n
Form an emitter (b). In the conventional example, after forming these four layers, a lifetime killer such as Au is diffused from the p emitter (6) side to make the lifetime within the n base@ almost uniform. However, in the present invention, for example, when diffusing a lifetime killer such as Au.

時間と拡散温度をコントロールすることによりライフタ
イムキラーがnペース(ロ)の一部までしか到達できな
いようにし第4図に示すようにnペース(ロ)内のpエ
ミッタ(6)に近い領域のみライフタイムが低くなる領
域四を設ける。これらのライフタイムコントロールff
1pエミツタ(6)及びnエミッタ(ロ)の表面にアノ
ード電極軸とカソード電極αηを形成す゛る〇 〔発明の他の実施例〕 上記説明した実施例ではサイリスタを例にとつて述べた
が1以上のことはダイオードの場合も同様である。また
ライフタイムコントロールハAuだけでなく、Pt等の
拡散あるいは電子線照射により達成できる。
By controlling the time and diffusion temperature, the lifetime killer can reach only a part of the n-pace (b), and only the area near the p emitter (6) within the n-pace (b) is shown in Figure 4. A region 4 is provided where the lifetime is low. These lifetime controlsff
1P Emitta (6) and N Emitor (b) form an anodel electrode axis and cathode electrode αη [Other embodiment of invention] In the above -described embodiment, the Sirista is described as an example, but one or more is 1 or more. The same applies to diodes. Furthermore, lifetime control can be achieved not only by Au but also by diffusion of Pt or the like or electron beam irradiation.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はサイリスタが一ターンオンした場合のシミュレ
ーションに用いた回路、第2図はサイリスタの不純物プ
ロファイルを示す図、第3図は従来のターンオフさせた
時の電流電圧及び素子内部における正札分布を示す図、
第4図は本発明のライフタイム分布を示す図、第5図は
本発明のターンオンさせた時め電流電圧及び素子内部に
おける正孔分布を示す図、第6図は低ライフタイム層の
ライフタイムの値とソフト性8 、 Qrr及びオン電
圧YONとの関係を示した図、第7図は本発明の一実施
例を説明するためのサイリスタ断面図である。 11・・・ nベース 12・・・pエミッタ13・・
・ pベース 14・・―nエミッタ15・・・ ライ
フタイムが低くなる領域16・・・ アノード電極 1
7・・・カソード電極第1図 第4図 第8図 (α) (ム) D「〃吠 ・χI、mm) 第5図 (OL) EMI77FRAN# χ(、/LLm1 第6図 h−一← 第7図
Figure 1 shows the circuit used for simulation when the thyristor is turned on once, Figure 2 shows the impurity profile of the thyristor, and Figure 3 shows the current voltage and the distribution inside the element when the thyristor is turned off in the conventional manner. figure,
Fig. 4 is a diagram showing the lifetime distribution of the present invention, Fig. 5 is a diagram showing the turn-on current voltage and hole distribution inside the device of the present invention, and Fig. 6 is a diagram showing the lifetime of the low lifetime layer. FIG. 7 is a cross-sectional view of a thyristor for explaining an embodiment of the present invention. 11... N base 12... P emitter 13...
・P base 14...-n emitter 15... Region where lifetime is low 16... Anode electrode 1
7... Cathode electrode Fig. 1 Fig. 4 Fig. 8 (α) (mu) D "〃倃 χI, mm) Fig. 5 (OL) EMI77FRAN# χ(,/LLm1 Fig. 6 h-1← Figure 7

Claims (3)

【特許請求の範囲】[Claims] (1) 少なくとも1つのpn接合を有するスイッチン
グ素子において、ターンオフ動作時に逆4圧の大半が印
加されるpn接合を形成する異なった導電型の2つの領
域のうち、不純物の低い方の領域内でライフタイムを不
均一にし、上記pn接合に近い部分で他の部分に比ベラ
イフタイムの値を174〜1150にしたことを特徴と
するスイッチング素子。
(1) In a switching element having at least one pn junction, in the region with lower impurity content among the two regions of different conductivity types forming the pn junction to which most of the inverse 4 voltage is applied during turn-off operation. A switching element characterized in that the lifetime is made non-uniform, and the value of the lifetime in a portion close to the pn junction is set to 174 to 1150 compared to other portions.
(2) ターンオフ動作時に逆電圧の大半が印加される
pn接合を形成する異った導電型の2つの領域のうち、
不純物の低い方の領域内でライフタイムの低い領域が上
記pn接合から定格耐圧の%の1圧より生じる空乏層の
終端より内側にあることを特徴とする特許請求の範囲第
1項記載のスイッチング素子。
(2) Of the two regions of different conductivity types that form the pn junction to which most of the reverse voltage is applied during turn-off operation,
The switching device according to claim 1, wherein the region with a low lifetime in the region with low impurity is located inside the termination of a depletion layer generated from the pn junction by 1% of the rated withstand voltage. element.
(3) 低ライフタイム領域が上記pn接合からはじま
り所定逆電圧より生じる空乏層の終端より外側にある仁
とを特徴とする特許請求の範囲$1項記載のスイッチン
グ素子。
(3) The switching element according to claim 1, wherein the low lifetime region starts from the pn junction and is located outside the end of a depletion layer generated by a predetermined reverse voltage.
JP59054174A 1984-03-23 1984-03-23 Switching element Expired - Lifetime JPH0640581B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59054174A JPH0640581B2 (en) 1984-03-23 1984-03-23 Switching element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59054174A JPH0640581B2 (en) 1984-03-23 1984-03-23 Switching element

Publications (2)

Publication Number Publication Date
JPS60198778A true JPS60198778A (en) 1985-10-08
JPH0640581B2 JPH0640581B2 (en) 1994-05-25

Family

ID=12963175

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JP59054174A Expired - Lifetime JPH0640581B2 (en) 1984-03-23 1984-03-23 Switching element

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6350067A (en) * 1986-08-20 1988-03-02 Toshiba Corp Thyristor
EP0651446A2 (en) * 1993-10-28 1995-05-03 Kabushiki Kaisha Toshiba GTO thyristor
EP0767500A2 (en) * 1995-10-03 1997-04-09 Hitachi, Ltd. Power semiconductor device with lattice defects
US5717244A (en) * 1994-10-25 1998-02-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having layers with varying lifetime characteristics

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5739577A (en) * 1980-06-27 1982-03-04 Westinghouse Electric Corp Method of reducing reverse recovery charge for thyristor
JPS5833875A (en) * 1981-08-25 1983-02-28 Toyo Electric Mfg Co Ltd High speed diode
JPS58114467A (en) * 1981-12-28 1983-07-07 Toyo Electric Mfg Co Ltd High speed diode

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5739577A (en) * 1980-06-27 1982-03-04 Westinghouse Electric Corp Method of reducing reverse recovery charge for thyristor
JPS5833875A (en) * 1981-08-25 1983-02-28 Toyo Electric Mfg Co Ltd High speed diode
JPS58114467A (en) * 1981-12-28 1983-07-07 Toyo Electric Mfg Co Ltd High speed diode

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6350067A (en) * 1986-08-20 1988-03-02 Toshiba Corp Thyristor
EP0651446A2 (en) * 1993-10-28 1995-05-03 Kabushiki Kaisha Toshiba GTO thyristor
EP0651446A3 (en) * 1993-10-28 1997-09-17 Toshiba Kk GTO thyristor.
US5717244A (en) * 1994-10-25 1998-02-10 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having layers with varying lifetime characteristics
EP0767500A2 (en) * 1995-10-03 1997-04-09 Hitachi, Ltd. Power semiconductor device with lattice defects
US5883403A (en) * 1995-10-03 1999-03-16 Hitachi, Ltd. Power semiconductor device
EP0767500A3 (en) * 1995-10-03 1999-07-28 Hitachi, Ltd. Power semiconductor device with lattice defects

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