JP2618943B2 - Semiconductor switching equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a semiconductor device capable of turning on and off a current by a gate signal, and particularly to a gate turn-off (hereinafter, GT).
The present invention relates to a semiconductor switching apparatus in which a thyristor and a bipolar transistor are formed on a single semiconductor substrate.

[Conventional technology]

As a prior art related to a semiconductor switching device in which a GTO thyristor and a bipolar transistor are formed on a single semiconductor substrate, for example, a technology described in Japanese Patent Application Laid-Open No. 52-60560 is known.

 Hereinafter, an example of this kind of prior art will be described with reference to the drawings.

FIG. 2 is a cross-sectional view showing a configuration example of a conventional semiconductor switching device. In FIG. 2, 1 is a semiconductor switching device, 2 is an anode electrode, 3 is a cathode electrode, 4 is a base electrode of a transistor, 5 is a gate electrode of a GTO thyristor, 21 is an n emitter layer, and 22 is a p base layer.

As shown in FIG. 2, a semiconductor switching device 1 according to the prior art includes a GTO having an npnp structure in a single semiconductor substrate.
The thyristor and the transistor having the npn structure are formed, and in this case, the n emitter layer 21 and the p base layer 22 of the transistor are formed the same as those of the GTO thyristor. The emitter of the transistor and the cathode of the GTO thyristor are connected to a common cathode electrode 3, and the collector of the transistor and the anode of the GTO thyristor are connected to a common anode electrode 2.
GTO thyristors are connected in parallel to form one semiconductor switching device. Such a semiconductor switching device needs to be a device with a low ON voltage and a wide ASO by combining a GTO thyristor with a low ON voltage and a transistor with a wide safe operation area (hereinafter, referred to as ASO).

[Problems to be solved by the invention]

However, the prior art described above does not take into consideration that a switching device having a low ON voltage and a wide ASO is realized. That is, as described above, the prior art
The n-emitter layer 21 and the p-base layer 22 of the transistor are formed in the same manner as those of the GTO thyristor, and the sheet resistance δsp of the p-base layer 22 immediately below the n-emitter layer 21 is increased in order to reduce the ON voltage of the GTO thyristor. Need, but p
If the sheet resistance Δsp of the base layer 22 is increased, the ASO of the transistor becomes narrow, and there is a problem that a high-voltage, large-current switching device cannot be realized.

An object of the present invention is to provide a low on-voltage GTO thyristor and a high ASO
A low-cost, high-performance semiconductor switching device that enables high-voltage, large-current switching by forming the same transistor and a single transistor on a single semiconductor substrate using the same process as when using a GTO thyristor alone. To provide.

[Means for solving the problem]

According to the present invention, the object is to form a switching element having at least a four-layer structure of pnpn, which is turned off by a gate signal, and a transistor having at least a four-layer structure of pnpn in a single semiconductor substrate, and forming the transistor The transistor is formed with the other emitter layer of the transistor positioned immediately below one of the emitter layers, and the switching element is formed such that one of the base layers has a depth and a sheet resistance that are equal to those of the other base layer of the transistor. This is achieved by forming the same portion and a portion having a lower impurity concentration and a smaller thickness than the portion, and operating the switching element as a thyristor.

[Action]

General three-layer bipolar transistor (eg, np
In order to widen the ASO, it is necessary to reduce the sheet resistance of the p base layer. However, if the sheet resistance of the p base layer is reduced, the efficiency of electron injection from the n emitter to the collector layer decreases. And the transistor does not operate. Therefore, by adding a hole injecting p-emitter layer to the collector layer side to form an npnp structure, it is possible to obtain a transistor that operates as a transistor even if the sheet resistance of the p-base layer is reduced.

Further, in the manufacturing process of such an npnp structure transistor, a GTO thyristor which is easy to turn on and has a low on-voltage is provided at a position adjacent to the transistor by diffusing an impurity for forming a p base layer partially. It can be formed by a process, and a high-performance semiconductor switching element combining a transistor with a wide ASO and a thyristor with a low on-voltage can be obtained.

〔Example〕

Hereinafter, an embodiment of a semiconductor switching device according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of the present invention, and FIG. 3 is a circuit diagram for explaining the operation. In FIG. 1, 6 is a p emitter layer, 7 is an n-type semiconductor substrate, 8, 11 are p base layers, 9,
10 is an n emitter layer, 12 is a p layer for suppressing a surface electric field, 13 is an n ⁺ layer for a depletion layer stop, 14 is a float electrode, 16 is a passivation film, and other symbols are the same as those in FIG. .

In FIG. 1, the transistor (denoted as TRS)
The GTO thyristor (simply referred to as GTO) includes an emitter layer 10, a p base layer 11, an n layer formed of an n type semiconductor substrate 7 made of silicon and the like, and a p emitter layer 6. The n emitter layer 9, the p base layer 8, An anode electrode 2 composed of an n-layer and a p-emitter layer 6 of a semiconductor substrate 7 and common to the collector side of the transistor and the anode side of the GTO thyristor
Is provided. In the above-described transistor configuration, the n-layer formed of the semiconductor substrate 7 serves as a collector of the transistor, and the p-emitter layer 6 performs a hole injection function.

A method for manufacturing such a semiconductor switching device will be described below.

(1) First, ap ⁺ p emitter layer 6, p base layers 8, 11 and a surface electric field suppressing p layer 12 are formed on an n-type semiconductor substrate 7,
At the same time, they are formed by thermal diffusion.

(2) Next, for n emitter layers 9, 10 and depletion layer stopper
The n ⁺ layer 13 is formed at the same time.

Although the transistor and the GTO can be simultaneously formed in the semiconductor substrate 7 by the above-described process, the formation of the p base layer 11 immediately below the n emitter layer 10 of the transistor requires the sheet resistance of the p base layer 11 to be reduced. It is done to be smaller. Therefore, as an example, the surface impurity concentration of the p base layer 11 was set to 3.7 × 10 ¹⁸ / cm ³ and the diffusion depth was set to 65 μm. As a result, the sheet resistance of the p base layer 11 is 38
Ω / cm ² . The npnp-structured transistor configured as described above functions as a transistor having a wide ASO. The p base layer 8 of the GTO thyristor formed simultaneously with the p base layer 11 is formed by partially depositing a p-type impurity to have a low impurity concentration and a thin portion. You. That is, since the p-base layer 8 is formed by partially depositing the p-type impurity as described above, the p-base layer 8 is formed below the portion where the p-type impurity is not placed, as shown by a symbol B in FIG. , A thin p-type impurity region is formed, and a p-type impurity region having a low impurity concentration is formed. GT having such p base layer 8
The O thyristor is a GTO thyristor that facilitates injection of electrons from the n emitter layer 9 through the p base layer 8 to the n base layer by the semiconductor substrate 7, has a fast turn-on operation, and has a low on-voltage.

As described above, the semiconductor switching device according to the embodiment of the present invention shown in FIG. 1 has the same manufacturing process as the conventional GTO thyristor, has a fast turn-on operation, has a low ON voltage, and has a wide ASO. The transistors can be manufactured and obtained at the same time.

As shown in FIG. 3, the semiconductor switching device according to the present invention has the above-mentioned GTO thyristor and transistor electrically connected in parallel. Hereinafter, the operation of the semiconductor switching device according to the present invention will be described with reference to FIG. Will be described.

The anode of the GTO thyristor and the collector of the transistor are connected to the anode A of the switching element, and the cathode of the GTO thyristor and the emitter of the transistor are connected to the cathode K of the switching element.
The switching-action between the cathode K, application of the power supply E _S is controlled to the load. A control power supply E1 is connected between the gate and the cathode of the GTO thyristor via a switch SW1, and a control power supply E2 is connected between the gate of the GTO thyristor and the base of the transistor via a switch SW2. SW2 controls a switching device including a GTO thyristor and a transistor.

Now, when the switch SW1 is turned on, a gate current _igq1 flows through the gate of the GTO thyristor, and the GTO thyristor
Turns, and summer and on state, the supply of current i _L is carried out from power supply E _S to the load. Next, the switch SW2 is turned on, a turn-off gate current _igq2 is _supplied to the GTO thyristor, and the GTO thyristor is set to a high resistance state. At the same time, the turn-off gate current i _{Pour gq2} . For the transistor BTRS, this gate current _igq2 becomes a forward base current, whereby the transistor BTRS is turned on. Therefore, the current i _L flowing through the load is commutated to the transistor BTRS, and the GTO thyristor is turned off. When the GTO thyristor is turned off, the turning-off gate current _{igq2 of} the GTO thyristor does not flow, the forward base current of the transistor does not flow at the same time, the transistor is also turned off, and the entire switching device is turned off.

The above-described switching device according to the embodiment of the present invention includes:
It has low ON voltage and wide ASO, for example,
Within a chip size of 7 mm × 7 mm, a switching device according to the present invention having a withstand voltage of 1200 V and an effective current of 30 A class, manufactured by setting the area ratio of the n emitter of the GTO thyristor and the n emitter of the transistor to 8: 1, has an anode current of 30 A. 800V was obtained with an on-voltage of 1.1V, a turn-on time of 0.7μs, and a safe operating voltage of 30A without a snubber circuit. On the other hand, conventional 1200V,
30A class GTO thyristor has ON voltage at anode current of 30A
1.8V, turn-on time 3μs, safe operating voltage without snubber circuit 30V, 500V or less.

As described above, the semiconductor switching device of the present invention is a high-performance device that has a fast turn-on operation, a low on-voltage, and a wide safe operation area.

FIG. 4 is a sectional view showing another embodiment of the present invention, and the reference numerals in FIG. 4 are the same as those in FIG.

In this embodiment, the p-type base layers 8 and 11 of the GTO thyristor and the transistor shown in FIG. 1 are formed close to each other, and a narrow n-layer region 15 is formed in the n-type semiconductor substrate. It is possible to prevent a decrease in withstand voltage of the planar junction in a region where the base layers 8 and 11 face each other. In this embodiment, the electric field near the surface of the n-layer region 15 is different from that of the embodiment shown in FIG.
The depletion layer formed by the reverse voltage between 8, 11 and the n base layer 7 significantly reduces the depletion layer, so that a decrease in the breakdown voltage of the planar junction can be prevented.

FIG. 5 is a sectional view showing still another embodiment of the present invention, in which a p base layer 8 and an n emitter layer 9 of a GTO thyristor are shown.
Is shown only in the vicinity.

In the embodiment shown in FIG. 5, the entire n-mitter layer 9 is formed in a region having a low impurity concentration and a small thickness of the p-base layer 8. Thus, the embodiment shown in FIG. 5 has an effect that the turn-on operation is faster and the on-voltage is lower than the embodiment shown in FIG.

FIG. 6 is a sectional view showing still another embodiment of the present invention, wherein 61 is an n ⁻ layer and 62 is an n ⁺ layer.

The embodiment shown in FIG. 6 is different from the embodiment shown in FIG. 4 in that an n-base layer formed of an n-type semiconductor substrate has a low impurity concentration, a thin n ⁻ layer 61 and a high impurity concentration n ⁻ layer 61. ⁺ Layer
It is formed so as to have the same forward blocking voltage as that of the n base layer alone. The embodiment shown in FIG. 7 is a high resistance n ^- layer 61 for blocking a forward applied voltage between main electrodes.
Is formed thin, so that the ON voltage can be reduced and the turn-on and turn-off operations can be speeded up.

The n base layer in the embodiment shown in FIG. 6 n ^- layer 61
And the n ⁺ layer 62 can be similarly applied to the embodiment of the present invention shown in FIGS. 1, 4 and 5.

The GTO thyristor in the above-described embodiment may be another switching element having the same configuration, for example, an SI thyristor.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide a high-performance and inexpensive semiconductor switching device having a low on-voltage, a high turn-on operation speed, a wide ASO, and a wide range.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing an embodiment of the present invention, FIG. 2 is a cross-sectional view showing a configuration example of a conventional semiconductor switching device, and FIG. 3 is a circuit diagram illustrating the operation of the embodiment of FIG. ,
4, 5, and 6 are cross-sectional views showing other embodiments of the present invention. 1 ... semiconductor switching device, 2 ... anode electrode,
3 ... cathode electrode, 4 ... base electrode of transistor, 5 ... gate electrode of GTO thyristor, 6 ... p emitter layer, 7 ... n-type semiconductor substrate, 8, 11, 22 ... p base layer, 9 , 10,21 ... n emitter layer, 12 ... p layer for suppressing surface electric field, 13 ... n ⁺ layer for depletion layer stopper, 14 ... float electrode, 16 ... passivation film.

Claims (1)

(57) [Claims] At least pn turned off by a gate signal
a switching element having a four-layer structure of pn and at least
forming a transistor having a four-layer structure of pnpn in a single semiconductor substrate, forming the transistor immediately below one emitter layer with the other emitter layer of the transistor positioned, One base layer is formed having a portion having the same depth and sheet resistance as the one base layer of the transistor, and a portion having a lower impurity concentration and a smaller thickness than the portion, A semiconductor switching device wherein a switching element is operated as a thyristor.