EP0638204A1 - Base resistance controlled mos gated thyristor with improved turn-off characteristics - Google Patents
Base resistance controlled mos gated thyristor with improved turn-off characteristicsInfo
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- EP0638204A1 EP0638204A1 EP93910724A EP93910724A EP0638204A1 EP 0638204 A1 EP0638204 A1 EP 0638204A1 EP 93910724 A EP93910724 A EP 93910724A EP 93910724 A EP93910724 A EP 93910724A EP 0638204 A1 EP0638204 A1 EP 0638204A1
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- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 239000000463 material Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims description 6
- 239000002800 charge carrier Substances 0.000 claims 9
- 239000002019 doping agent Substances 0.000 claims 4
- 108091006146 Channels Proteins 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 10
- 238000002347 injection Methods 0.000 description 5
- 239000007924 injection Substances 0.000 description 5
- 238000001465 metallisation Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000000903 blocking effect Effects 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
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- 230000001419 dependent effect Effects 0.000 description 1
- 229940014425 exodus Drugs 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
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- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
- H01L29/744—Gate-turn-off devices
- H01L29/745—Gate-turn-off devices with turn-off by field effect
- H01L29/7455—Gate-turn-off devices with turn-off by field effect produced by an insulated gate structure
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- Thyristors (AREA)
Abstract
An inventive thyristor structure includes anode and cathode electrodes, with a diverter electrode being connected to the cathode electrode. A multi-layer body of semiconductor material has a first surface and includes a regenerative portion (110) operatively coupled between the anode and cathode electrodes, with a non-regenerative portion (120) being operatively coupled between the anode and diverter electrodes. The regenerative portion includes adjacent first (170), second (180), third (200) and fourth regions (240) of alternating conductivity type arranged respectively in series between the cathode and anode electrodes, wherein the cathode electrode is in electrical contact with the first region and the anode electrode is in electrical contact with the fourth region.
Description
BASE RESISTANCE CONTROLLED MOS GATED THYRISTOR WITH IMPROVED TURN-OFF CHARACTERISTICS
The present invention relates generally to the field of four-layer, latching semiconductor devices, and particularly to methods for controlling the conduction characteristics of such devices by modulating the voltage applied to the gate electrode of a MOSFET portion of the device.
BACKGROUND OF THE INVENTION
The development of power MOSFET's was at least in part motivated by the objective of reducing the control current required by power bipolar devices during forced turn-off. In bipolar devices the injection of minority carriers into their drift region reduces the resistance to forward current flow. These devices are capable of operation at appreciable current densities, but are relatively inefficient as a consequence of the large currents required during device turn-on and turn-off.
In contrast, the gate structure of the power MOSFET has a very high steady-state impedance. This allows control of the device by a voltage source, since only relatively small gate drive currents are required to charge and discharge the input gate capacitance. Unfortunately, the ease of gating the power MOSFET is offset by its high on-state resistance arising from the absence of minority carrier injection. Hence, a combination of low-resistance bipolar-type current conduction with MOS gate control would provide the desired features of high operating forward current density and low gate drive power.
Referring to the cross-sectional illustration of Fig. 1, a device known as an insulated gate bipolar transistor (IGBT) illustrates one approach to combining these features. In this type of structure most of the forward current flow occurs between the emitter and collector terminals of the vertical PNP bipolar transistor portion of the device. The on-state losses of the IGBT at high voltages are significantly less than those of power MOSFETs due to the injection of minority carriers (electrons) into the N-base drift region.
As shown in Fig. 2, a regenerative device known as MOS-controIled thyristor (MCT) exhibits less forward voltage drop than does the IGBT. This P-N-P-N structure can be regarded as two transistors - an upper NPN transistor and a lower PNP transistor - that are internally connected in such a fashion as to obtain regenerative feedback between each other. Specifically, a thyristor may be considered as a combination of PNP and NPN bipolar transistors connected such that the base of each is driven by the collector current of the other. Once the thyristor is turned on via the gate electrode such that the requisite transistor turn- on current is supplied each transistor then drives the other into saturation. At this juncture the thyristor is no longer under the control of its gate electrode and continues to operate even in the absence of gate drive current - a phenomenon known as regenerative latch-up. Although the large current flow characteristic of regenerative on-state operation may be extinguished by appropriate modification of the gate voltage, the current produced by the MCT may not be adjusted (i.e., "fine-tuned") during regenerative operation through modulation of the gate voltage.
Since thyristors are often used in high-power switching applications, the maximum turn-off current level is generally of considerable importance. The MCT device of Fig.2 is turned off by reversing the polarity of the applied gate voltage so as to create an inversion layer at the surface of the N-region embedded between ' the P and P+ regions underlying the gate. In this way a p-channel field-effect transistor (FEET) within the device forms an active short circuit between the N+ cathode and P-base regions. The device will cease regenerative operation when the short-circuit current increases to the extent that the voltage across the N+/P
junction falls below 0.7V. Unfortunately, the maximum current which can be switched off by the MCT markedly decreases with increasing anode voltages at elevated temperatures. As a consequence, the current handling capability of the MCT has proven to be inadequate for particular circuit applications.
Fig.3 shows a perspective view of a segment of a depletion-mode thyristor (DMT) device having a pair of entrenched MOS gate regions. Each trench region includes an elongated polysiiicon gate G insulated from the remainder of the device by an encapsulating oxide sleeve S. Practical implementations of DMT devices will typically include a plurality of the segments depicted in Fig. 3, with the polysiiicon gates from each segment being connected to a common gate contact (not shown). Regenerative operation within the thyristor section of the device (see Fig. 3) is instigated by applying a positive voltage to the common gate contact so as to form conductive channels at the interfaces between the vertical segments of the oxide sleeve S and the P-type semiconductor layer. The conductive channels facilitate electron flow from the upper N+ region at the top of the device into the N-type drift region upon application of a positive voltage to the anode contact. The electrons injected from the upper N+ layer into the drift region provide the base current required to turn-on the PNP transistor inherent within the thyristor section of the device. Actuation of the PNP transistor leads to the regenerative feedback described above, thus precipitating thyristor latch-up. In the regenerative on-state holes flow from the P+ anode into the upper P-type region via the N-type drift region. The hole current is collected by the cathode contact after flowing laterally through the P-base and P+ cathode diffusions.
Regenerative operation within the device may be halted by applying a negative voltage to the gate contact. The negative voltage applied to the gate serves to extinguish the N-type conductive channels existing along the surfaces of the oxide adjacent the P-type layer. In addition, the negative gate voltage depletes the regions R between adjacent entrenched MOS gates of electrons. The resulting barrier to electron flow effectively formed between the P-type region and the N-type drift region breaks off regenerative current flow, thereby
terminating thyristor-mode operation. Although the DMT device is capable of acceptable thyristor-mode operation, the entrenched gate structures make fabrication of the device relatively complicated and expensive.
Figure 4 shows a three-dimensional representation of a segment of a base resistance controlled thyristor (BRT). The BRT depicted in Figure 4 may be characterized as a conventional thyristor in combination with a MOSFET device, with the MOSFET serving to decrease base resistance and base current when the thyristor is in the on-state. With the device in an off-state, a positive voltage applied to the anode is supported across junction J1 between an N-drift region and a P-base region. The BRT may be turned on by applying a positive bias to the gate to create an N-type conductive channel at the surface of the P-base region. Electron flow is initially from the N+ emitter region through the conductive channel to the N-type base region. The complementary hole current originates within the P+ anode region and traverses the N-base to the P-base. As shown in Fig.4, the P-base is shorted to cathode contact #1 at a boundary B between the N+ emitter diffusion and the P-base. Accordingly, within the P-base the hole current flows laterally to cathode contact #1 , thereby creating the forward bias across the junction between the P-base and N+ emitter necessary to induce regenerative thyristor-mode operation.
The BRT device depicted in Fig.4 is turned off by applying a negative voltage to the gate contact so as to create a P-type inversion layer along the underlying surface of the N-base region. Holes within the P-base will then tend to flow through this low-impedance inversion layer to a P+ diverter region, and then laterally through the diverter region to a P-channel MOS (PMOS) section of the device. Within the PMOS section a P-type inversion layer exists at the surface of the N-base region when the negative turn-off voltage is applied to the gate. Holes flow within this inversion layer from the P+ diverter to the P+ cathode diffusion, and are collected by cathode contact #2. In this way application of the negative turn-off voltage to the gate contact reduces the flow of hole current within the P-base by creating a low-impedance path for holes to cathode #2.
This decrease in hole current eliminates the forward bias between the P-base and N+ emitter, which results in termination of the thyristor current.
Although facilitating turn-off of the BRT device depicted in Fig.4, the P+ diverter region and PMOS region combine to form a considerable series turn-off resistance between the P-base and cathode contact #2. The BRT device of Fig. 4 thus has only a limited capability to extinguish large thyristor currents, since the associated large voltage drop through the series turn-off resistance will cause junction between the P-base and the N+ emitter to remain forward-biased. Hence, it as an object of the present invention to provide a base resistance controlled thyristor device having reduced resistance in the turn-off current path.
SUMMARY OF THE INVENTION
The present invention addresses the foregoing objectives by providing a base controlled resistance thyristor structure having improved turn-off characteristics. The inventive thyristor structure includes anode and cathode electrodes, with a diverter electrode being connected to the cathode electrode. A multi-layer body of semiconductor material has a first surface and includes a regenerative portion operatively coupled between the anode and cathode electrodes, with a non- regenerative portion being operatively coupled between the anode and diverter electrodes. The regenerative portion includes adjacent first, second, third and fourth regions of alternating conductivity type arranged respectively in series between the cathode and anode electrodes, wherein the cathode electrode is in electrical contact with the first region and the anode electrode is in electrical contact with the fourth region.
The inventive thyristor is turned on by applying an enabling voltage to an insulated gate electrode disposed adjacent the first surface such that a conductive channel is created in the regenerative portion via modulation of the conductivity therein. Impression of a non-enabling voltage upon the gate electrode extinguishes channel conductivity within the third region of the regenerative portion and forms a current path between the second region of the regenerative
portion and the non-regenerative portion, thereby initiating turn-off of the device. The diverter electrode collects any charges remaining in the second region of the regenerative portion subsequent to application of the turn-off voltage to the gate electrode.
BRIEF DESCRIPTION OF THE DRAWINGS
Additional objects and features of the invention will be more readily apparent from the following detailed description and appended claims when taken in conjunction with the drawings, in which:
Figure 1 is a cross-sectional illustration of a conventional insulated gate bipolar transistor (IGBT) device.
Figure 2 shows a prior art P-N-P-N regenerative semiconductor device generally known as a MOS-controlied thyristor (MCT).
Figure 3 shows a perspective view of a segment of a prior art depletion-mode thyristor (DMT) device having a pair of entrenched MOS gate regions.
Figure 4 shows a perspective view of a segment of a conventional base resistance controlled thyristor (BRT).
Figure 5 shows a cross-sectional representation of a preferred embodiment of the inventive base controlled MOS gated thyristor device.
Figure 6 shows a simplified perspective view of a preferred embodiment of the thyristor device of the present invention in which, for purposes of clarity, the oxide and metallization layers above a substrate surface have been omitted from view.
Figure 7 depicts a cross-sectional representation of an alternate preferred embodiment of the inventive base controlled MOS gated thyristor device.
Figure 8 shows a simplified perspective view of the alternate preferred embodiment of the inventive thyristor device in which the oxide and metallization layers above a substrate surface have been omitted from view.
DESCRIPTION OF THE PREFERRED EMBODIMENT
Referring to Figure 5, there is shown a cross-sectional representation of a preferred embodiment of the inventive base controlled MOS gated thyristor device 100. As is discussed hereinafter, rapid turn-off of the device 100 is effected by diverting charge from a regenerative portion 110 to a non-regenerative portion 120 upon application of a turn-off voltage to a gate terminal 130. More specifically, applying the requisite turn-off voltage to gate terminal 130 creates a P-type conductive channel along the surface of a body of semiconductor material 140 underneath gate electrode 150. The conductive channel provides a low-resistance path from region 180 of regenerative portion 110 to a diverter electrode 152 coupled to cathode terminal 160. The resultant exodus of charge from region 180 through the electrode 152 serves to extinguish self-sustaining current flow within the regenerative portion 110, thereby expediting turn-off of the device 100.
In order to simplify explanation, only a single segment of the inventive thyristor 100 is depicted in Fig.5. Specifically, by forming the mirror image of the thyristor segment shown in Fig. 5 about reference axes A and B a multi-section device may be created. The four-layer regenerative portion 110 of the semiconductor body 140 includes an emitter region 170 of N+ conductivity material, and a base region 180 of P conductivity material forming a first PN junction 190 with the emitter 170. A third layer of the regenerative portion of the thyristor device 100 is identified as a drift region 200, which consists of N-type semiconductor material adjacent to and forming a second PN junction 210 with the base region 180. As shown in Fig. 5, the semiconductor body 140 is bounded by a substantially planar upper surface 142 defined in part by the uppermost portions of the emitter 170, base 180, and drift 200 regions. A set of reference coordinates are included in Fig. 5 and are used in the following description to specify direction.
The drift region 200 separates the base 180 from a fourth layer, or anode region 220, of the regenerative portion 110. The drift region 200 includes an optional buffer layer 230 of N-type semiconductor, which forms a PN junction 234 with a P+ anode layer 240. The three-layer non-regenerative structure 120 is located adjacent to the four-layer regenerative portion 110, and is comprised of a P+ diverter diffusion 250, the drift region 200, and the anode region 240. Ohmic contacts exist between the lower surface of anode region 240 and an anode electrode 260, between the upper surface 142 of the P+ diffusion 250 and the diverter electrode 152, and between the N+ emitter and an emitter electrode 270.
Figure 6 shows a simplified perspective view of the thyristor device 100 in which, for purposes of clarity, the oxide and metallization layers above surface 142 have been omitted from view. However, it is noted that a metal layer (not shown) above surface 142 connects the divertor electrode 152 to the emitter electrode 270, thereby establishing an electrical connection between the divertor electrode 152 and the cathode terminal 160. Each region of the regenerative 110 and non-regenerative portions 120 of the device 100 forms an elongated segment in a Z-direction perpendicular to the X-Y plane of Fig. 5. As shown in Figure 6, the P-base 180 forms a well in which is disposed the N+ emitter 170. The cathode electrode 270 (not shown in Fig.6) extends back along the Z-direction so as to overlay both the N+ emitter 170 and the portion 272 of the P-base 180 behind the N+ emitter 170. Hence the P-base 180 is electrically coupled to the cathode electrode 270, with the base resistance to the flow of holes in the Z- direction being represented by a base resistor Rb (Fig. 5). In addition, the P+ diverter 250 extends in the X-direction and merges with the P-base diffusion 180 in a plane 280. The diverter and cathode electrodes 152 and 270 (Fig. 5) similarly merge at the plane 280, thus enabling holes within the P+ diverter 250 to be withdrawn through the cathode terminal 160.
Again referring to Fig.5, a thfn oxide layer 290 insulates the gate electrode 150 from the N+ diffusion 170, P-base diffusion 180, drift region 200, and P+ divertor region 250. The thickness of the thin oxide layer 290 is typically chosen such that an inversion layer may be formed in the P-type base 180 upon application
of a typical gate turn-on bias to the electrode 212. For example, for a thin oxide thickness of 500 angstroms a gate voltage on the order of 5 to 15 volts will lead to creation of a conductive channel at the surface 142 of the base 180.
With the cathode electrode 160 and gate terminal 130 held at the same (e.g., zero volt) potential, the thyristor 100 is in a forward blocking mode. In the blocking mode the device 100 behaves like an open circuit, and respectively supports positive and negative voltage differentials between the anode and cathode electrodes 260 and 270 across the PN junctions 210 and 234. The device is initially actuated by applying the requisite turn-on voltage to the gate terminal 130. The subsequent formation of a conductive channel at the surface of the P-type diffusion 180 proximate the thin oxide 290 allows electrons to be injected from the N+ region 170 into the drift region 200. At these low current levels the thyristor device 100 operates similarly to the conventional IGBT (Insulated Gate Bipolar Transistor) shown in Fig. 1. Current flow through the regenerative portion 110 has not yet become self-sustaining (i.e., latched-up) while the device 100 is in the IGBT mode, and hence the anode current remains dependent on the magnitude of the applied gate voltage.
The electrons flowing from the N+ region 190 into the drift region 130 serve as base current for the PNP transistor inherent within the four layer regenerative portion 110. When a sufficient voltage is applied to the anode electrode 260 the resulting current flow is adequate to induce regenerative thyristor action (i.e. latch up) within the four layer portion 110. The onset of regenerative action (on- state) is precipitated by the flow of hole current laterally through the base 180 in the Z direction perpendicular to the plane of Fig. 5. Specifically, the hole current produces a voltage drop which develops a forward bias across the junction 190, thereby causing electrons to be injected from the emitter 170 into the drift region 200. The hole current is collected by the cathode electrode 270 proximate the plane 280 (Fig. 6) after longitudinally traversing the base region 180 underneath the emitter 170. At sufficiently large values of gate bias the hole current becomes large enough to sustain regenerative charge injection. The anode current density at the onset of regenerative action will, for example,
typically be approximately 25 Acm2 for a Z-direction emitter length of 100 microns and a P-base sheet resistance of 3000 ohms/square. At larger anode current densities the regenerative portion 110 latches up and the device 100 operates in a regenerative mode.
As shown in Figure 5, the device 100 includes a P-channel turn-off MOSFET 310 which incorporates the gate electrode 150 and underlying thin oxide 290, as well as the surface areas of the P-base 180, drift region 200, and diverter region 250 adjacent thereto. When it is desired to terminate thyristor action within the regenerative portion 110 of the device 100 a negative voltage (e.g., -15V) is impressed on the gate terminal 130. This creates a P-type channel typically having a length on the order of 1 micron at the surface of the drift region 200, thereby creating a low resistance path between the diverter electrode 152 and the P-base 180. Since the diverter electrode 152 is in electrical contact with the cathode 160, fewer holes will flow longitudinally through the higher resistivity P-base 180 in orderto reach the cathode electrode 270 proximate the plane 280 (Fig.6). The forward bias across the junction 190 is correspondingly reduced, thus facilitating termination of thyristor action by impeding charge injection within the regenerative portion 110.
As was mentioned in the Background of the Invention, the P+ diverter region and PMOS region included within the conventional BRT device of Figure 4 facilitate turn-off but combine to form a considerable series turn-off resistance. This limits the magnitude of thyristor current which may be extinguished, since the associated large voltage drop through the series turn-off resistance will cause the P-base to remain forward-biased relative to the N+ emitter. In contrast, the inventive thyristor 100 is capable of terminating relatively high thyristor currents as a consequence of the low-impedance path created between the diverter electrode 152 and the P-base 180 during device turn-off.
Referring to Figure 7, there is shown a cross-sectional representation of an alternate preferred embodiment of the inventive base controlled MOS gated thyristor device 400. The device 400 operates in substantially the same manner
as the device 100, with rapid turn-off being effected by diverting charge from a regenerative portion 410 to a non-regenerative portion 420 upon application of a turn-off voltage to a gate terminal 430. More specifically, applying the requisite turn-off voltage to gate terminal 430 creates P-type conductive channels along the surface of a body of semiconductor material 440 underneath first and second gate electrodes 450 and 454. The conductive channels, in conjunction with a floating P+ region 458, provide a low-resistance path from the regenerative portion 420 to a diverter electrode 450 coupled to cathode terminal 460. The flow of charge from the regenerative portion 410 through the electrode 450 serves to extinguish self-sustaining current flow within the regenerative portion 410, thereby expediting turn-off of the device 400.
Figure 8 shows a simplified perspective view of the thyristor device 400 in which, for purposes of clarity, the oxide and metallization layers above surface 440 have been omitted from view. As was previously discussed with reference to the device 100 shown in Figure 6, each region of the regenerative 410 and non- regenerative portions 420 of the device 400 forms an elongated segment in a Z-direction perpendicular to the X-Y plane of Fig.7. Inspection of Figures 6 and 8 reveals that the embodiments 100 and 400 of the inventive thyristor are substantially similar in structure, with the exception that the device 400 includes the P+ floating emitter region 458 as well as a first and a second P-channel MOSFET 480 and 484 (Fig. 7). As is shown in Figure 8, the P+ floating region 458 extends longitudinally in the Z-direction and is buffered from P-base region 490 and P+ diverter region 500 by N-type drift region 510. In addition, the gate structures of the first and second MOSFETs 480 and 484 (not shown in Figure 8) merge in an area G between the rear boundary of P+ floating region 458 and the P+ diverter 500. The floating region 458 provides a low-impedance path between the first and second MOSFETs 480 and 484 during device turn-off.
Again, the P+ diverter region 500 initially extends in the Z-direction from the cross-section depicted in Figure 7, and then bends in the X-direction to merge with the P-base region 490 in a plane 530. The diverter electrode 450 and a cathode electrode 550 (Fig..7) similarly merge at the plane 530, thus enabling
holes within the P+ diverter 500 to be withdrawn through the cathode terminal 160 during device turn-off.
While the present invention has been described with reference to a few specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims. Specifically, thyristor devices incorporating the teachings of the present invention may be embodied in semiconductor structures which differ from those depicted in the Figures. For example, the diverter region need not be realized using the specific diffusion geometry specified herein. Those skilled in the art may be aware of other device geometries disposed to collect holes from the regenerative portion of the thyristor during device turn-off.
Claims
1. A semiconductor thyristor device comprising: a substrate forming a drift region, an emitter region, a base region having a first portion interposed between said drift region and said emitter region, an anode region adjacent a lower portion of said drift region distal said base region, and a diverter region adjacent a channel portion of said drift region distal said anode region; a cathode electrode electrically coupled to said emitter region and to a second portion of said base region; an anode electrode coupled to said anode region; an insulated gate forming a first MOS transistor connecting said emitter region to said drift region when a tum-on voltage is applied to said insulated gate, said insulated gate also forming a second MOS transistor connecting said base region to said diverter region when a turn-off voltage is applied to said insulated gate; and a diverter electrode, coupled to said diverter region and to said cathode electrode, for collecting charge carriers from said base and drift regions when a turn-off voltage is applied to said insulated gate; wherein a first current path from said anode to said cathode is formed by said first MOS transistor when said turn-on voltage is applied to said insulated gate, and wherein when said turn-off voltage is applied to said insulated gate said first current path is shut off and a second current path is formed between said base and diverter regions by said second MOS transistor such that any charges remaining in said base region are collected by said diverter electrode.
2. The semiconductor device of Claim 1 wherein said insulated gate means includes: an oxide layer adjacent said emitter, base, drift and diverter regions, and a gate electrode in contact with said oxide layer.
3. The semiconductor device of Claim 2 wherein said base and diverter regions consist of P-type semiconductor material, and wherein dopant concentration is higher in said diverter region than in said base region.
4. The semiconductor device of Claim 2 wherein said emitter and drift regions consist of N-type semiconductor material, and wherein dopant concentration is higher in said emitter region than in said drift region.
5. A semiconductor thyristor device comprising: anode and cathode electrodes; a diverter electrode coupled to said cathode electrode; a multi-layer body of semiconductor material having a first surface and including a regenerative portion operatively coupled between said anode and cathode electrodes, and a non-regenerative portion operatively coupled between said anode and diverter electrodes, said regenerative portion including adjacent first, second, third and fourth regions of alternating conductivity type arranged respectively in series between said cathode and anode electrodes, said cathode electrode being in electrical contact with said first region and said anode electrode being in electrical contact with said fourth region; and an insulated gate electrode disposed adjacent said first surface for modulating electrical conductivity within said second region of said regenerative portion in order to turn said device on upon application of a turn-on voltage to said gate electrode, and for modulating electrical conductivity within said third region of said regenerative portion in order to turn said device off by forming a current path between said second region of said regenerative portion and said non-regenerative portion upon application of a turn-off voltage to said gate electrode; wherein any charges remaining in said second region of said regenerative portion are collected by said diverter electrode subsequent to said application of said turn-off voltage to said gate electrode.
6. The semiconductor device of Claim 5 wherein said third region separates said second region and said non-regenerative portion adjacent said insulated gate electrode.
7. The semiconductor device of Claim 6 wherein said second region of said regenerative portion consists of a P-type well adjacent said drift region, and wherein said first region is disposed within said P-well.
8. The semiconductor device of Claim 7 wherein a first conductive channel is created in said P-well adjacent said insulated gate upon application of said tum-on voltage thereto, and wherein said first conductive channel is extinguished and a second conductive channel is created in said third region adjacent said insulated gate upon application of said turn-off voltage to said insulated gate.
9. A semiconductor thyristor device comprising: anode and cathode electrodes; a diverter electrode coupled to said cathode electrode; a multi-layer body of semiconductor material having a first surface and including a regenerative portion operatively coupled between said anode and cathode electrodes, and a non-regenerative portion operatively coupled between said anode and diverter electrodes, said regenerative portion including adjacent first, second, third and fourth regions of alternating conductivity type arranged respectively in series between said cathode and anode electrodes, said cathode electrode being in electrical contact with said first region and said anode electrode being in electrical contact with said fourth region; and an insulated gate forming a first MOS transistor connecting said first region to said third region when a turn-on voltage is applied to said insulated gate, and forming a second MOS transistor connecting said second region of said regenerative portion with said non-regenerative portion when a turn-off voltage is applied to said insulated gate; wherein a first current path from said anode electrode to said cathode electrode is formed by said first MOS transistor when said turn-on voltage is applied to said insulated gate, and wherein when a turn-off voltage is applied
to said insulated gate said first current path is shut off and a second current path is formed by said second MOS transistor between said second region of said regenerative portion and said non-regenerative region such that any charges remaining in said second region are collected by said diverter electrode.
10. A semiconductor thyristor device comprising: a substrate forming a drift region, an emitter region, a base region having a first portion interposed between said drift region and said emitter region, an anode region adjacent a lower portion of said drift region distal said base region, a floating region inteφosed between first and second channel portions of said drift region distal said anode region, and a diverter region separated from said floating region by said second channel portion; a cathode electrode electrically coupled to said emitter region and to a second portion of said base region; an anode electrode coupled to said anode region; an insulated gate disposed to form a conductive layer of a first polarity within said first channel so as to connect said emitter region to said drift region when a tum-on voltage is applied to said insulated gate, said insulated gate being further disposed to form conductive layers of a second polarity within said first and second channels when a turn-off voltage is applied to said insulated gate so as to enable said diverter region to collect charge carriers from said base and drift regions.
AMENDED CLAIMS
[received by the International Bureau on 28 September 1993 (28.09.93); original claims 1,5,9 and 10 amended; remaining claims unchanged (4 pages)]
1. A semiconductor thyristor device comprising: a substrate forming a drift region, an emitter region, a base region having a first portion inteφosed between said drift region and said emitter region, an anode region adjacent a lower portion of said drift region not immediately proximate said base region, and a diverter region adjacent a channel portion of said drift region not immediately proximate said anode region; a cathode electrode electrically coupled to said emitter region and to a second portion of said base region; an anode electrode coupled to said anode region; an insulated gate forming a first MOS transistor connecting said emitter region to said drift region when a turn-on voltage is applied to said insulated gate, said insulated gate also forming a second MOS transistor connecting said base region to said diverter region when a turn-off voltage is applied to said insulated gate, said second MOS transistor expediting turn-off of said device by removing charge carriers from said base region when said turn-off voltage is applied to said insulated gate; and a diverter electrode, coupled to said diverter region and to said cathode electrode, for collecting said charge carriers from said base region and for collecting charge carriers from said drift region when said turn-off voltage is applied to said insulated gate; wherein a first current path from said anode to said cathode is formed by said first MOS transistor when said turn-on voltage is applied to said insulated gate, and wherein when said tum-off voltage is applied to said insulated gate said first current path is shut off and a second current path is formed between said base and diverter regions by said second MOS transistor such that any charges remaining in said base region are collected by said diverter electrode.
2. The semiconductor device of Claim 1 wherein said insulated gate means includes: an oxide layer adjacent said emitter, base, drift and diverter regions, and a gate electrode in contact with said oxide layer.
3. The semiconductor device of Claim 2 wherein said base and diverter regions consist of P-type semiconductor material, and wherein dopant concentration is higher in said diverter region than in said base region.
4. The semiconductor device of Claim 2 wherein said emitter and drift regions consist of N-type semiconductor material, and wherein dopant concentration is higher in said emitter region than in said drift region.
5. A semiconductor thyristor device comprising: anode and cathode electrodes; a diverter electrode coupled to said cathode electrode; a multi-layer body of semiconductor material having a first surface and including a regenerative portion operatively coupled between said anode and cathode electrodes, and a non-regenerative portion operatively coupled between said anode and diverterelectrodes, said regenerative portion including adjacent first, second, third and fourth regions of alternating conductivity type arranged respectively in series between said cathode and anode electrodes, said cathode electrode being in electrical contact with said first region and said anode electrode being in electrical contact with said fourth region; and an insulated gate electrode disposed adjacent said first surface for modulating electrical conductivity within said second region of said regenerative portion in order to turn said device on upon application of a tum-on voltage to said gate electrode, and for modulating electrical conductivity within said third region of said regenerative portion in order to turn said device off by forming a current path between said second region of said regenerative portion and said non-regenerative portion through which charge carriers are removed from said second region of said regenerative portion, said current path being formed upon application of a tum-off voltage to said gate electrode; wherein any charges remaining in said second region of said regenerative portion are collected by said diverter electrode subsequent to said application of said tum-off voltage to said gate electrode.
6. The semiconductor device of Claim 5 wherein said third region separates said second region and said non-regenerative portion adjacent said insulated gate electrode.
7. The semiconductor device of Claim 6 wherein said second region of said regenerative portion consists of a P-type well adjacent said drift region, and wherein said first region is disposed within said P-well.
8. The semiconductor device of Claim 7 wherein a first conductive channel is created in said P-weii adjacent said insulated gate upon application of said turn-on voltage thereto, and wherein said first conductive channel is extinguished and a second conductive channel is created in said third region adjacent said insulated gate upon application of said tum-off voltage to said insulated gate.
9. A semiconductor thyristor device comprising: anode and cathode electrodes; a diverter electrode coupled to said cathode electrode; a multi-layer body of semiconductor material having a first surface and including a regenerative portion operatively coupled between said anode and cathode electrodes, and a non-regenerative portion operatively coupled between said anode and diverterelectrodes, said regenerative portion including adjacent first, second, third and fourth regions of alternating conductivity type arranged respectively in series between said cathode and anode electrodes, said cathode electrode being in electrical contact with said first region and said anode electrode being in electrical contact with said fourth region; and an insulated gate forming a first MOS transistor connecting said first region to said third region when a tum-on voltage is applied to said insulated gate, and forming a second MOS transistor connecting said second region of said regenerative portion with said non-regenerative portion when a tum-off voltage is applied to said insulated gate, said second MOS transistor expediting tum-off of said device by removing charge carriers from said second region of said regenerative portion when said tum-off voltage is applied to said insulated gate;
wherein a first current path from said anode electrode to said cathode electrode is formed by said first MOS transistor when said tum-on voltage is applied to said insulated gate, and wherein when a tum-off voltage is applied to said insulated gate said first current path is shut off and a second current path is formed by said second MOS transistor between said second region of said regenerative portion and said non-regenerative region such that any charges remaining in said second region are collected by said diverter electrode.
10. A semiconductor thyristor device comprising: a substrate forming a drift region, an emitter region, a base region having a first portion inteφosed between said drift region and said emitter region, an anode region adjacent a lower portion of said drift region not immediately proximate said base region, a floating region interposed between first and second channel portions of said drift region not immediately proximate said anode region, and a diverter region separated from said floating region by said second channel portion; a cathode electrode electrically coupled to said emitter region and to a second portion of said base region; an anode electrode coupled to said anode region; an insulated gate disposed to form a conductive layer of a first polarity within said first channel so as to connect said emitter region to said drift region when a tum-on voltage is applied to said insulated gate, said insulated gate being further disposed to form conductive layers of a second polarity within said first and second channels through which charge carriers are removed from said base region when a tum-off voltage is applied to said insulated gate so as to enable said diverter region to collect charge carriers from said base and drift regions.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US87575192A | 1992-04-29 | 1992-04-29 | |
| US875751 | 1992-04-29 | ||
| PCT/US1993/003789 WO1993022798A1 (en) | 1992-04-29 | 1993-04-21 | Base resistance controlled mos gated thyristor with improved turn-off characteristics |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| EP0638204A1 true EP0638204A1 (en) | 1995-02-15 |
Family
ID=25366307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP93910724A Withdrawn EP0638204A1 (en) | 1992-04-29 | 1993-04-21 | Base resistance controlled mos gated thyristor with improved turn-off characteristics |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0638204A1 (en) |
| JP (1) | JPH07506933A (en) |
| CA (1) | CA2133585A1 (en) |
| WO (1) | WO1993022798A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5444272A (en) * | 1994-07-28 | 1995-08-22 | International Rectifier Corporation | Three-terminal thyristor with single MOS-gate controlled characteristics |
| US7989885B2 (en) | 2009-02-26 | 2011-08-02 | Infineon Technologies Austria Ag | Semiconductor device having means for diverting short circuit current arranged in trench and method for producing same |
| US8232579B2 (en) | 2009-03-11 | 2012-07-31 | Infineon Technologies Austria Ag | Semiconductor device and method for producing a semiconductor device |
| DE102010039258B4 (en) | 2010-08-12 | 2018-03-15 | Infineon Technologies Austria Ag | Transistor device with reduced short-circuit current |
| CN110364569B (en) * | 2019-06-10 | 2022-11-22 | 西安理工大学 | Trench gate MOS-GCT structure and preparation method thereof |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3018468A1 (en) * | 1980-05-14 | 1981-11-19 | Siemens AG, 1000 Berlin und 8000 München | THYRISTOR WITH CONTROLLABLE EMITTER SHORT CIRCUITS AND METHOD FOR ITS OPERATION |
| US4799095A (en) * | 1987-07-06 | 1989-01-17 | General Electric Company | Metal oxide semiconductor gated turn off thyristor |
| US4827321A (en) * | 1987-10-29 | 1989-05-02 | General Electric Company | Metal oxide semiconductor gated turn off thyristor including a schottky contact |
| US4982258A (en) * | 1988-05-02 | 1991-01-01 | General Electric Company | Metal oxide semiconductor gated turn-off thyristor including a low lifetime region |
-
1993
- 1993-04-21 CA CA 2133585 patent/CA2133585A1/en not_active Abandoned
- 1993-04-21 WO PCT/US1993/003789 patent/WO1993022798A1/en not_active Application Discontinuation
- 1993-04-21 EP EP93910724A patent/EP0638204A1/en not_active Withdrawn
- 1993-04-21 JP JP5519372A patent/JPH07506933A/en active Pending
Non-Patent Citations (1)
| Title |
|---|
| See references of WO9322798A1 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO1993022798A1 (en) | 1993-11-11 |
| CA2133585A1 (en) | 1993-11-11 |
| JPH07506933A (en) | 1995-07-27 |
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