JPH0548083A - Power semiconductor element - Google Patents

Abstract

PURPOSE:To improve turn-off capability of a power semiconductor element having a mesa structure. CONSTITUTION:The basic structure is a p-n-p-n consisting of a p<+> type emitter layer 2, an n type buffer layer 3, an n<-> type base layer 4, a p type base layer 5 and an n<+> type emitter layer 6. Irregularities are formed on the surface of a substrate, and the n<+> type emitter layer 6 is formed on the surface of the protruding part, and an anode electrode 1 is formed on the p type emitter layer, and a cathode electrode 11 is formed on the n<+> type emitter layer 6, and a gate electrode 10 is formed on the p type base layer 5 of the recessed part. From the side surface to the bottom surface of the recessed part of the p type base layer 5, in order to reduce resistance in the lateral direction of a base, a high concentrated p<+> type layer 7 is formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device such as a gate turn-off thyristor or a bipolar transistor having a mesa structure.

[0002]

2. Description of the Related Art A gate turn-off thyristor (hereinafter referred to as G
A TO thyristor) is an element that performs a self-turn-off by applying a bias to the gate electrode and discharging a part of the anode current to the outside as a gate current.
In such a GTO thyristor, it is known that a pressure contact electrode structure is used as a mesa structure in which a step is provided between the split emitter surface and the gate electrode surface.

FIG. 7 shows a sectional structure of a main part of such a conventional GTO thyristor. From the back side of the board in the figure, p ⁺ Type emitter layer 2, n type buffer layer 3, n ⁻ Type base layer 4, p type base layer 5 and n ⁺ It has a pnpn structure composed of the type emitter layer 6. Concavities and convexities are formed on the substrate surface side, and n ⁺ is formed on the convex surface. The type emitter layer 6 is formed, and the p-type base layer 5 is exposed in the recess. The p-type emitter layer 2 has an anode electrode 1 of n ⁺ A cathode electrode 11 is formed on the mold emitter layer 6, and a gate electrode 10 is formed on the p-type base layer 5 in the recess. The substrate surface between the gate electrode 10 and the cathode electrode 11 is covered with the first insulating film 8, and the gate electrode 10 is covered with the second insulating film 9. Since there is a step between the cathode electrode 11 and the gate electrode 10 and the gate electrode 10 is covered with the insulating film 9, the cathode electrode 11 can be connected to the outside by a pressure contact electrode.

In such a GTO thyristor, the lateral resistance of the p-type base layer 5 from the contact position of the gate electrode 10 to the central portion of the n-type emitter layer 6 is a major factor that determines the current cutoff capability (turn-off capability). Known to be. When the lateral resistance of the p-type base layer 5 is large, a forward bias is applied between the p-type base layer 5 and the n-type emitter layer 6 due to a voltage drop in the p-type base layer 5 due to carrier discharge at turn-off. , The element cannot be turned off without stopping the electron injection from the n-type emitter layer 6.
Therefore, the smaller the lateral resistance of the p-type base layer 5, the better the turn-off characteristics.

However, the G of the mesa structure as shown in FIG.
In the TO thyristor, the distance between the contact position of the base electrode 10 and the n-type emitter layer 6 is relatively long, and p
Since the mold base layer 5 is usually formed by diffusion from the substrate surface, the impurity concentration at the bottom is low. Therefore, the lateral resistance of the p-type base layer 5 from the contact position of the gate electrode 10 to the central portion of the n-type emitter layer 6 has a large value, and there is a problem that sufficient turn-off capability cannot be obtained.

[0006]

As described above, the GTO thyristor having the conventional mesa structure has a problem that the lateral resistance of the p-type base layer is high and a high turn-off capability cannot be obtained. Similar problems exist in other power semiconductor devices having a similar structure, for example, a bipolar transistor having a similar split emitter structure and mesa structure. The present invention has been made in view of the above circumstances, and an object thereof is to provide a power semiconductor device having an improved turn-off capability.

[0007]

In a power semiconductor device according to the present invention, a second conductivity type base layer is formed on a surface of a high resistance first conductivity type semiconductor layer, and a surface of the second conductivity type base layer is formed. It has a basic structure in which unevenness is formed, a first conductivity type emitter layer is formed on the surface of the unevenness, an emitter electrode is formed there, and a control electrode is formed in the concave. The second conductivity type layer is formed.

[0008]

According to the present invention, the high-concentration second-conductivity-type layer is formed on the concave side surface of the first-conductivity-type emitter layer formed on the convex portion of the device surface and the control electrode formed on the concave portion around the element layer, that is, on the side surface of the mesa. Thus, the lateral resistance of the second conductive type base layer is small. Therefore, a GTO thyristor or a bipolar transistor having a high turn-off ability can be obtained.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing one cathode region of a GTO thyristor according to an embodiment of the present invention.
Is a sectional view taken along line AA ′.

From the back side of the substrate, p ⁺ Type emitter layer 2, n type buffer layer 3, n ⁻ Type base layer 4, p type base layer 5 and n ⁺ It has a pnpn structure composed of the type emitter layer 6.
Concavities and convexities are formed on the substrate surface side, and n ⁺ is formed on the convex surface. The type emitter layer 6 is formed, and the p-type base layer 5 is exposed in the recess. The p-type emitter layer 2 has the anode electrode 1 and n
⁺ A cathode electrode 11 is formed on the mold emitter layer 6, and a gate electrode 10 is formed on the p-type base layer 5 in the recess.
The substrate surface between the gate electrode 10 and the cathode electrode 11 is the first
Of the insulating film 8 and the gate electrode 10 is
Is covered with an insulating film 9. There is a step between the cathode electrode 11 and the gate electrode 10, and the gate electrode 10
The top is covered with an insulating film 9. The basic structure so far is
It is the same as the conventional one.

In this embodiment, the p-type base layer 5 has a high concentration of p ⁺ from the side surface to the bottom surface of the recess. The mold layer 7 is formed. Further, in this embodiment, n ^{+ on the} surface of the convex portion is Type emitter layer 6 is p ⁺ It is selectively formed on the surface of the convex portion so as not to directly contact the mold layer 7.

FIG. 3 shows the manufacturing process of the GTO thyristor according to this embodiment. p ⁺ Type emitter layer, n type buffer layer 3, n ⁻ Of the p-type base layer 4 and the p-type base layer 5
After the structure is formed by a known process, the first mask material 12 is patterned on the surface of the p-type base layer 5 ((a)). The first mask material 12 has openings in the n-type emitter layer forming region and the gate electrode forming region. Then, the second mask material 13 is patterned so as to partially overlap the first mask material 12 and cover the n-type emitter layer forming region ((b)).
). The p-type base layer 5 exposed in this state is subjected to RIE.
Etching is performed to form a recess ((c)). Then, oblique ion implantation is performed with the first and second mask materials 12 and 13 left, so that high-concentration p ⁺
The mold layer 7 is formed ((d)).

Subsequently, the first and second mask materials 12, 13
Among them, the second mask material 13 is removed, and the third mask material 14 that covers the concave portion is formed again by patterning. Impurity ion implantation is performed using the first and third mask materials 12 and 14 to selectively implant n ^{+ on the} surface of the convex portion. The type emitter layer 6 is formed ((e)). As described above, the layer formation and dispersion process is completed, and then all the mask material is removed ((f)) to form electrodes.

In the GTO thyristor of this embodiment, p ^{+ is formed} from the concave side surface to the bottom surface of the p-type base layer 5 formed with irregularities. Since the mold layer 7 is formed, the lateral resistance of the p-type base layer 6 is small. This allows
High turn-off ability is obtained. Also in this example,
n ⁺ Type emitter layer 6 is p ⁺ It is selectively formed on the surface of the convex portion so as not to come into direct contact with the mold layer 7, and therefore p ⁺ The formation of the mold layer 7 does not lower the breakdown voltage between the emitter and the base.

FIG. 4 shows a sectional view of a GTO thyristor of another embodiment corresponding to FIG. In this embodiment, unlike the previous embodiment, the p-type base layer 5 is formed shallower than the recess of the gate electrode formation portion.

Even with such a structure, a high concentration of p ^{+ is formed} from the side surface to the bottom surface of the recess. Since the mold layer 7 is formed,
There is no problem in applying a bias to the p-type base layer 5, and p ⁺
The mold layer 7 provides a low lateral resistance. Further, when the structure of this embodiment is adopted, the impurity diffusion time for forming the p-type base layer 5 can be shortened.

FIG. 5 shows a sectional structure of a main part of a GTO thyristor of still another embodiment, corresponding to FIG.
In this example, n ⁺ The type emitter layer 6 is formed on the entire surface of the convex portion, and therefore p ⁺ It is in direct contact with the mold layer 7.

In the structure of this embodiment, the breakdown voltage is lower than that of the embodiment of FIG. 2, but the emitter area is large. In the case where the breakdown voltage and the on-state voltage are not required and the breakdown voltage is higher than that in the previous embodiment, the present embodiment can be adopted.

FIG. 6 is a cross-sectional structure of a main part of an embodiment in which the present invention is applied to a bipolar transistor. From the back of the board, n ⁺ Type collector contact layer 22, high resistance n ⁻
Type collector layer 23, p type base layer 24 and n ⁺ The type emitter layer 25 has an npn structure. This is the GT in Figure 2.
O thyristor p ⁺ This is the same as the state in which the mold emitter layer 2 is not provided. The p-type base layer 24 has an uneven surface,
n ⁺ The type emitter layer 25 is formed on the convex portion. Then, as in the case of the GTO thyristor, high concentration p ⁺ The mold layer 26 is formed. The emitter side surface is covered with an insulating film 27, and an opening is opened in this to form an emitter electrode 29 and a base electrode 28. The base electrode 28 is further covered with an insulating film 30. n ⁺ A collector electrode 21 is formed on the type collector / contact layer 22.

In the case of the npn transistor of this embodiment, too, like the GTO thyristor, excess holes are accumulated in the steady ON state, and therefore, at the time of turn-off, the operation of discharging excess holes by the gate electrode is required. Therefore,
p ⁺ If the mold layer 26 is formed, the base resistance is reduced, excess holes are discharged at high speed, and high-speed turn-off is possible.

[0021]

As described above in detail, according to the present invention, a high concentration layer is formed from the side surface of the concave portion of the split-emitter type power semiconductor device having a mesa structure to the bottom surface thereof, so that a high turn-off capability is achieved. Can be realized.

[Brief description of drawings]

FIG. 1 is a plan view of a main part of a GTO thyristor according to an embodiment of the present invention.

FIG. 2 is a sectional view taken along the line AA ′ in FIG.

FIG. 3 is a sectional view for explaining the manufacturing process for the embodiment.

FIG. 4 is a sectional view of a main part of a GTO thyristor of another embodiment.

FIG. 5 is a sectional view of an essential part of a GTO thyristor of another embodiment.

FIG. 6 is a cross-sectional view of essential parts of a bipolar transistor of another embodiment.

FIG. 7 is a sectional view of a main part of a conventional GTO thyristor.

[Explanation of symbols]

1 ... Anode electrode, 2 ... p ⁺ -Type emitter layer, 3 ... n-type buffer layer, 4 ... n ^- Type base layer, 5 ... p type base layer, 6 ... n ⁺ Type emitter layer, 7 ... p ⁺ Mold layer, 8, 9 ... Insulating film, 10 ... Gate electrode, 11 ... Cathode electrode, 21 ... Collector electrode, 22 ... N ⁺ Type collector contact layer, 23 ... n ^- Type collector layer, 24 ... p type base layer, 25 ... n ⁺ Type emitter layer, 26 ... p ⁺ Mold layer, 29 ... Emitter electrode, 30 ... Base electrode.

Continuation of the front page (51) Int.Cl. ⁵ Identification number Office reference number FI technical display location H01L 29/74 B 7013-4M J 7013-4M

Claims (1)

[Claims] 1. A second conductivity type base layer is formed on the surface of a high resistance first conductivity type semiconductor layer, and irregularities are formed on the surface of the second conductivity type base layer. In a power semiconductor device in which an emitter layer is formed, an emitter electrode is formed thereon, and a control electrode is formed in a recess, a high-concentration second conductivity type layer is formed on a side surface and a bottom surface of the recess. Power semiconductor device.