JPS62198160A - Insulated gate field effect transistor - Google Patents

Abstract

PURPOSE:To attain the high input impedance, high speed switching and large power of a transistor by forming an MOS gate structure, a conductivity modulation structure and a minority carrier extraction structure as a switching mechanism. CONSTITUTION:An element structure has a region projected in a columnar shape from a semiconductor substrate for forming parts of a drain region 28 (P<+> type) and a conductivity modulation region 27 at parts of a channel region 26 (P) and the conductivity modulation region 27 (N<-> type), a source region 29 (N<+> type) disposed at the top of the columnar projection and a gate oxide film 30 and a polysilicon electrode 31 disposed at the periphery, and a grid region 32 (P<+> type) to surround the root of the columnar projection attached to the region 27 of the substrate. As a result, the region 27 has both majority carrier and minority carrier to enhance a current density, and to remarkably reduce the resistance at ON time. The excess minority carrier fed to the region 27 is extracted from a grid region 32 near a channel provided to prevent the later thyristor operation and a latchup from occurring.

Description

[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] The present invention relates to a power switching semiconductor device that has high input power/Vidas/S, high speed switching and switching characteristics, and can be used with large power. .

[Prior art and its problems]

First, the structures of a bipolar transistor, an insulated gate transistor, and a static induction transistor, which are conventionally known as power switching semiconductor devices, are shown in cross-sectional views in FIGS. 5, 6, and 7, respectively.

In the bipolar transistor shown in FIG. 5, 1 is a base electrode, 2 is a space region [F], 3 is an emitter electrode, 4 is an emitter region (into), and 5 is a collector region (injection).

Reference numeral 6 indicates the collector region (which has a higher impurity concentration than the collector region 5), and 7 indicates the collector electrode. In this bipolar transistor, minority carrier injection from the emitter region 4 is excited by a pace current, and most of the minority carriers are Since the current control method passes through the base region 2 and collects the current at the collector, it has drawbacks such as low input impedance, difficulty in high-speed switching operation, and limited operating range due to secondary breakdown phenomenon.

From the top, 8 is a gate electrode, 9 is a gate insulating film, 10 is a source electrode, 11 is a source region (N), and 12 is a channel region (2) of the single-gate transistor shown in Figure N6.

Reference numeral 13 represents a drain region (N) with low impurity lateral variation, 14 represents a drain region (N) with high impurity concentration, and 15 represents a drain electrode. The electrostatic induction transistor shown in FIG. 7 has a source electrode 16. Source region 17 (N), gate electrode 18° gate region 19. Drain region 20 (to), drain region 21 (N) with higher impurity concentration than region 2o, drain electric polishing 22
．． And it consists of a folding layer 23(P). Both such insulated gate type and static induction type transistors are voltage-driven switching elements, and are promising as power switching semiconductor devices having high input impedance and high-speed switching characteristics. However, insulated gate type transistors/distor and static 1! Inductive type transistors are all uniball type in which majority carriers flow between the source and drain due to channel induction, so low resistance is a problem and it is difficult to apply them to high power applications.

Figure N8 shows the structure of a conductivity-modulated insulated gate transistor that has improved the above-mentioned drawbacks. Parts common to those in Figure 6 are denoted by the same symbols. The difference between FIG. 8 and FIG. 6 is that in FIG. 8, the drain region 24 (P) has a conductivity type opposite to that of the drain region 14 (N) in FIG. ), and in addition to the conventional insulated gate transistor operation, conductivity modulation is caused in the drain region 13 (N), making it possible to increase current density, lower resistance, and increase power. It is. However, this structure has the drawback that, since it is an N-P-N-P structure, thyristor operation is likely to occur, and measures to prevent latch-up are required.

FIG. 9 has been proposed as a further improvement of the structure of FIG. 8, and common parts with those in FIG. Low resistance layer 25 (P) of the same conductivity type as
By providing the source region 1 through the vicinity of the channel,
The structure is designed to alleviate the generation of minority carriers that reach dll(N) as much as possible. Another structure of this improved version of the spit is a low resistance 11 inside the channel region 12.
A system with a . However, at present, none of these improved structures can be said to have sufficiently improved structures.

Moreover, Figure 6! In order to control the channel length in both horizontal orientations shown in FIGS. 8 and 9, the channel region 12 and source region 11 are formed by double diffusion.
A problem arises in that the impurity materials and materials used to form each of these layers are limited. Furthermore, such a structure has the disadvantage that the minority carrier injection phenomenon causes a long tail at turn-off, which is disadvantageous in terms of frequency characteristics.Currently, countermeasures to this problem include gold diffusion and high-energy electron beam irradiation. These methods have been addressed by generating recombination centers, but these methods also affect the interface of the channel region and the gate oxide film, and it is important to obtain reproducibility in the manufacturing process. I have a problem.

[Purpose of the invention]

The present invention has been made in view of the above points, and its purpose is to take full advantage of all the characteristics of insulated gate type transistors having high-speed switching characteristics, while also solving the disadvantages of low 1tItt and density as a structure that produces conductivity modulation. It also eliminates the disadvantages of conductivity-modulated insulated gate transistors, such as thyristor operation, possibility of latch-up, and long tails at turn-on/off, resulting in high input impedance, high-speed switching, and high power. The object of the present invention is to provide a new and satisfying insulated gate field effect transistor.

[Key points of the invention]

The present invention provides a semiconductor drain region having one conductivity type, a conduction variation region having a vague conductivity type, a semiconductor channel forming region having the same conductivity type as the drain region, and a conduction variation region having the same conductivity as the drain region. A source region having a conductivity type, a gate insulating film formed over the entire surface of the channel forming region and extending to at least the side surface of the convex portion of the source region and the conductivity modulation region, and a gate provided on the gate insulating film. By adopting a structure that includes an electrode, in the on state, when a voltage higher than the threshold voltage is applied to the gate electrode, a channel layer is formed at the interface between the gate insulating film and the semiconductor channel forming region, and a large number of layers from the source region are formed. Injection of carriers and injection of minority carriers from the semiconductor drain region simultaneously occur in the conductivity modulation region, resulting in an effect of increasing the density of current flowing through the conductivity modulation region. ? ! By disposing a semiconductor grid region of a low resistance layer having the same conductivity type as the drain region so as to surround at least a portion of the flow path, most of the minority carriers injected from the drain region are drawn into the grid region, This prevents minority carriers from flowing into the vicinity of the channel, prevents latch-up, and allows minority carriers to be instantly pulled out through the grid area in the 1-off state, thereby shortening the tail length at turn-off. In other words, by combining the MOS gate structure as a switching mechanism, a conductivity modulation structure, and a minority carrier extraction structure, the transistor can achieve high input impedance and high-speed switching.

This achieved high power consumption.

[Embodiments of the invention]

The present invention will be explained below based on examples.

FIG. 1 shows a surface external view of a semiconductor chip in which a large number of insulated gate field effect transistor cells according to the present invention are arranged. Figure 2 shows the A-A' section t-2nd.
It is shown in FIG. 3 to correspond to the figure. Therefore, in FIGS. 1 to 3, common parts are indicated by the same reference numerals. As explained below with reference to Figures 2 and 3,
In the device structure of the present invention, a part of the channel region 26 (P) and the conductivity modulation region 27 (N) is
(P) and a part of the conductivity modulation region 27, the structure has a columnar region projecting from the semiconductor substrate, and the source region 29 (
N).

Surrounding gate oxide film 30 and polysilicon gate electrode 31
The grid area 32 (P
) is formed.

In this structure, when a voltage higher than the threshold voltage is applied to the gate electrode 31, the channel layer 3 shown by a dotted line forms near the interface with the gate oxide H30 of the channel region 26.
3 is formed and the source, ([34 causes the source region 29
The majority carriers injected from the channel layer 33 flow into the conductivity modulation region 27 and reach the drain region 28. On the other hand, the drain electrode 35
Minority carriers injected from 8 have a conduction variation of 1v! As a result, majority carriers and minority carriers coexist in the conductivity modulation/transmission region 27, increasing the current density and greatly reducing the resistance during off-state. The surplus minority carriers that have flowed into the conduction and modulation region 27 are extracted from the grid region 32 near the channel provided to prevent subsequent thyristor operation and latch-up.

In addition, in order to further enhance the extraction of minority carriers by the grid region 32, as shown in FIG. 4, a grid region 32a (P ) is also effective, and this works even more effectively to prevent thyristor operation and latch-up.

As described above, the present invention utilizes the characteristics of a conductivity modulation type insulated gate transistor to increase current density, and also provides a grid region to draw excess minority carriers remaining in the conductivity modulation region into the grid region, thereby creating a thyristor. This realizes an insulated gate field effect transistor that suppresses operation, has high input impedance, high speed switching characteristics, and can be used for high power.

〔Effect of the invention〕

As explained above in the embodiments, according to the present invention, a minority carrier extraction layer (grid By providing a conductivity modulation region), it is possible to make maximum use of the excellent characteristics of conductivity modulation, ill-type insulated gate transistors, and also to eliminate the possibility of occurrence of thyristor operation and latch-up, which are unique to conductivity modulation region edge gate transistors. can suppress, resulting in high input impedance,
We have succeeded in obtaining a power switching semiconductor device that has high-speed switching characteristics and can be used for high power applications.

[Brief explanation of drawings]

Figure 1 is a surface external view of a semiconductor chip according to the present invention, Figure 2 is a plan view showing the element structure of the present invention, Figure 3 is a first folded view, and Figure 4 shows an example of a structure different from Figure 3. Cross-sectional views, Figure 8g5 is a cross-sectional view of a conventional bipolar transistor, Figure 6 is a cross-sectional view of an insulated gate transistor, Figure 7 is a cross-sectional view of a static induction transistor, and Figure 8 is a conductivity modulation transistor. FIG. 9 is a cross-sectional view of the improved conductivity modulated insulated gate transistor of FIG. 1...Pace! ffi, 2...Base area, 3...
・Emitter polarization, 4... Emitter region, 5, 6...
Collector region, 7... Collector electrode, 8, 18.31
... Gate electrode, 9, 30 ... Gate insulating film, 10
, 16 , 34... Source 1! pole, 11, 17
, 29... Source region, 12.26... Channel region, 13, 14, 20, 21, 24.28... Drain region, 15, 22.35... Drain tl! very,
19... Gate region, 23... Buried III, 25...
...Low resistive layer, 27...Conductivity modulation region, 32...
Grid area, 33...￥ 1 Figure 4 Figure i2 Figure 3

Claims (1)

[Scope of Claims] 1) A conductivity modulation type insulated gate field effect transistor, which comprises a drain region having one conductivity type, a conductivity modulation region having a conductivity type different from that of the drain region, and the same conductivity as the drain region. a channel region having the same conductivity type as the conductivity modulation region, and a source region having the same conductivity type as the conductivity modulation region are deposited in this order so as to cover at least the entire side surface of the channel region and on the side surfaces of the source region and the conductivity modulation region. a gate insulating film extending from the source region to the drain region, a gate electrode provided on the gate insulating film, and a current path in the conductivity modulation region from the source region to the drain region through a channel layer formed in the channel region. An insulated gate field effect transistor comprising: a grid region that surrounds at least a portion of the drain region and has the same conductivity type as the drain region. 2) An insulated gate field effect transistor according to claim 1, wherein the channel region and a part of the conductivity modulation region are formed to protrude from the conductivity modulation region.