JP2003031584A - Bipolar transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To actualize a semiconductor element which has high static dielectric strength and a sustain voltage, and a high current gain and a low ON-voltage at the same time. SOLUTION: On one surface of a high-resistance n-type base layer 1, an n-type collector layer 2 of high concentration is formed and on the other surface, a p-type base layer 3 is selectively formed. In the p-type base layer 3, an n-type emitter layer 4 is formed and in a region on the surface of the n-type base layer 1, which is different from the p-type base layer 3, a trench groove 8 is formed. Furthermore, a base electrode 5 is provided on the p-type base layer 3 located adjacent to the n-type emitter layer 4, a collector layer 6 is provided on the n-type collector layer 2, and an emitter electrode 7 is provided on the n-type emitter layer 4. In the trench groove 8, an embedded electrode 10 is formed via an insulation film 9. The embedded electrode 10 is electrically connected to the base electrode 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly to a bipolar semiconductor device suitable as a power switching device.

[0002]

2. Description of the Related Art In the field of power electronics in recent years, there is a demand for miniaturization and high performance of power supply equipment. In response to this demand, in power semiconductor devices used for power supply equipment, etc., along with higher breakdown voltage and larger current,
Attention has been focused on performance improvement for low loss, high speed, and high breakdown resistance. In particular, in order to reduce the loss of the semiconductor element, it is necessary to reduce the on-voltage (steady loss) and the switching loss, and various element structures have been developed and studied.

Among them, a power transistor having a planar structure, which is a typical medium-capacitance element used in a wide variety of fields at present, will be described.

FIG. 20 is a sectional view showing the structure of an npn type power transistor. In this power transistor, a high-concentration n-type base layer 1a has a high-concentration n-type on one surface thereof.
The type collector layer 2a is formed. A p-type base layer 3a is formed on the other surface of the high resistance n-type base layer 1a, and p
An n-type emitter layer 4a is selectively formed on the surface of the type base layer 3a. A base electrode 5a is provided on a region of the surface of the p-type base layer 3a different from that of the n-type emitter layer 4a. A collector electrode 6a is provided on the n-type collector layer 2a, and an emitter electrode 7a is provided on the n-type emitter layer 4a.

This power transistor operates as follows. It is assumed that a positive voltage is applied to the collector electrode 6a and a zero voltage is applied to the emitter electrode 7a. At the time of turn-on, a positive voltage larger than the built-in voltage of the pn junction composed of the p-type base layer 3a and the n-type emitter layer 4a is applied to the base electrode 5a.

As a result, as shown in FIG. 21, holes h are injected from the base electrode 5a to the n-type emitter layer 4a through the p-type base layer 3a, and the holes h are injected from the n-type emitter layer 4a to the p-type base layer 3a. The electrons e are injected. Some electrons e are
Although it recombines with the holes h in the p-type base layer 3a and disappears,
Since the junction depth of the p-type base layer 3a is shallow and the collector electrode 6a is biased to a positive potential, most of the electrons e are injected from the p-type base layer 3a into the n-type base layer 1a and the n-type collector is formed. It flows out to the collector electrode 6a through the layer 2a. When electrons e are injected into the n base layer 1a, holes h are also injected into the n type base layer 1a so as to satisfy the charge neutral condition. By this operation, conductivity modulation occurs, and the power transistor is turned on (conducting state).

On the other hand, at the time of turn-off, a negative voltage smaller than the withstand voltage of the pn junction composed of the p-type base layer 3a and the n-type emitter layer 4a is applied to the base electrode 5a.
This reverse-biases between the base and the emitter, n
The injection of electrons e from the type emitter layer 4a is stopped, and holes h accumulated in the high-resistance n-type base layer 1a are stopped.
Are discharged from the base electrode 5a and turned off.

In this power transistor, since the holes h are injected from the p-type base layer 3a into the high-resistance n-type base layer 1a, conductivity modulation occurs in the n-type base layer 1a, so that the on-state voltage is low, It has the feature of controlling a large current.

[0009]

However, in the conventional power transistor, a considerable proportion of the hole current injected from the base electrode 5a in the ON state is not injected into the high resistance n-type base layer 1a. , Recombine with electrons e in the p-type base layer 3a or on the surface of the p-type base layer 3a, or directly through the p-type base layer 3a to the n-type emitter layer 4a.
Flow into.

Similarly, a considerable proportion of the electron current injected from the emitter electrode 7a is the high resistance n-type base layer 1.
a is not injected into a and recombines with the holes h in the p-type base layer 3a and the surface of the p-type base layer 3a, or the p-type base layer 3a
And flow directly into the base electrode 5a.

Therefore, a large base current is required,
There is a problem that the current gain (DC current amplification factor: hFE = IC / IB) is small. Particularly, in the conventional structure, the p-type base layer 3a is formed over the entire element effective region except the junction termination region and the electrode bonding pad region. p
The type base layer 3a has a higher impurity concentration and a shorter carrier lifetime than the high resistance n-type base layer 1a.
The amount of carrier recombination is large. Therefore, in the conventional structure in which the p-type base layer 3a is formed over the entire element effective region, the current gain is significantly reduced.

As described above, since the conventional transistor has a problem that the current gain is small, the transistor is often used in a Darlington connection form as shown in FIG. As a result, the base current can be small, but unless the collector voltage of 0.8 V or more is applied, the base current is not transferred from the upper transistor to the lower transistor. Therefore, as seen from the current-voltage characteristics of FIG. 23, there is a problem that the ON voltage of the element cannot be reduced to 0.8 V or less.

As described above, the conventional semiconductor device has a problem that the current gain is small or the on-voltage is large.

An object of the present invention was made in consideration of the above circumstances, and is to provide a semiconductor element capable of increasing the current gain and reducing the on-voltage as compared with the conventional one.

[0015]

A semiconductor device according to the present invention comprises a high resistance first conductivity type base layer and a first conductivity type collector layer formed on one surface of the first conductivity type base layer. A second conductivity type base layer selectively formed on the other surface of the first conductivity type base layer, and a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer. A trench groove formed on the other surface of the first conductivity type base layer in a region different from that of the second conductivity type base layer, and formed on a surface of the second conductivity type base layer,
And a base electrode formed adjacent to the first conductivity type emitter layer, a first main electrode formed on the surface of the first conductivity type collector layer, and a surface of the first conductivity type emitter layer. And a second main electrode formed above.

Further, in the semiconductor device according to the present invention, a high resistance first conductivity type base layer, a first conductivity type collector layer formed on one surface of the first conductivity type base layer, and the first resistance type base layer. A second conductivity type base layer selectively formed on the other surface of the conductivity type base layer; a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer; A trench groove selectively formed on the surface of the conductive type base layer, and formed on the surface of the second conductive type base layer,
A base electrode formed adjacent to the first conductivity type emitter layer, a first main electrode formed on the first conductivity type collector layer, and a first main electrode formed on the first conductivity type emitter layer. It is characterized by having two main electrodes.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In all the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type.
I am using a mold. (First Embodiment) FIG. 1 is a sectional view showing the structure of a main part of a semiconductor device according to the first embodiment of the present invention. In this embodiment, a high-concentration n-type collector layer 2 is formed on one surface of a high-resistance n-type base layer 1. A p-type base layer 3 is selectively formed on the other surface of the n-type base layer 1, and an n-type emitter layer 4 is formed in the p-type base layer 3. Further, a trench groove 8 having a depth deeper than the p-type base layer 3 and halfway through the n-type base layer 1 is formed in a region on the surface of the n-type base layer 1 different from the p-type base layer 3. Further, a base electrode 5 is provided on the p-type base layer 3 adjacent to the n-type emitter layer 4, a collector electrode 6 is provided on the n-type collector layer 2, and an emitter is provided on the n-type emitter layer 4. An electrode 7 is provided. A buried electrode 10 is formed in the trench groove 8 via an insulating film 9. The embedded electrode 10 is electrically connected to the base electrode 5.

Next, the operation of such a semiconductor device will be described with reference to FIG.
This will be described using the time chart of. Each line in Figure 2 is
The base voltage VB of the base terminal B, the base current IB of the base terminal B, the collector voltage VCE of the collector terminal C, and the collector current IC of the collector terminal C are shown in order from the top.

At turn-on (time t = t1), a positive voltage is applied to the base terminal B with respect to the emitter. As a result, as shown in FIG. 3, holes are injected from the p-type base layer 3 to the n-type base layer 1 and at the same time electrons are injected from the n-type emitter layer 4 to the n-type base layer 1 to turn on the device. To do. As a result, conductivity modulation occurs in the n-type base layer 1, and current is applied at a low on-voltage.

FIG. 4 shows a carrier distribution in a conducting state (on state) in a vertical cross section that cuts the n emitter layer 4. Holes are injected to a deep position in the n-type base layer 1 to cause conductivity modulation, and the on-voltage is reduced. This is n
This is because the region of the p-type base layer 3 occupying the surface of the type base layer 1 is small, and thus the recombination amount of electrons and holes in the p-type base layer 3 is reduced.

FIG. 5 is a diagram showing the voltage-current characteristics of the semiconductor device of the present invention, and is a diagram for comparison with the voltage-current characteristics of the conventional power transistor shown in FIG. Both the semiconductor device of the present invention and the conventional power transistor show voltage-current characteristics when a current of 2 A / cm ^{2 is} applied as a base current. For example, when a collector current of 100 A / cm ² is applied, a low ON voltage of about 0.3 V can be obtained by the semiconductor device of the present invention.

However, in the case of the conventional power transistor, the collector current that can be passed with the collector voltage of 0.3 V is 30 A / cm ² or less at the most. If, in order to approach the voltage-current characteristics of the present invention, it is necessary to apply a current of about 15 A / cm ² as a base current, resulting in a large base drive loss (power consumption). For this reason, the conventional power transistor is used in Darlington connection as shown in FIG. 22, and due to this, the voltage-current characteristic is about 0.8.
Stand up from V.

On the other hand, in the semiconductor device of the present invention,
Since the base current required to obtain a low ON voltage is small and the current gain (DC current amplification factor: hFE = IC / IB) is large, it is not necessary to use Darlington connection. As a result, the current rises from zero voltage as shown in FIG. 5, so that a low on-voltage can be obtained from the low current region to the high current region.

Now, the reason why a large current gain is obtained in the semiconductor device of the present invention will be described. FIG. 6 is a diagram showing the dependence of the current gain on the width of the p-type base layer 3 in the semiconductor device of FIG. Since the current gain largely depends on the area ratio of the high-concentration impurity layer to the unit structure area (cell area), in the present embodiment, the p-type base layer 3 is used.
Area occupancy (Wp / Wcell) and the area occupancy of the n-type emitter layer 4 (Wn + / Wcell). This is because the carrier lifetime is smaller as the impurity concentration is higher. That is, as the area of the p-type base layer 3 and the area of the n-type emitter layer 4 are larger, the amount of carriers (recombination current) in which the holes h injected from the base electrode 5 are recombined in these high-concentration impurity layers. Is increased and the current gain is decreased.

On the other hand, in the semiconductor device of the present invention,
Since the p-type base layer 3 is selectively divided and formed, and the area of the p-type base layer 3 is set small, a large current gain is realized. Specifically, for example, as shown in FIG. 6, the unit structure and the p-type base layer 3 are Wcell = 20 μm,
A high current gain of hFS = 50 or more can be obtained by forming the p-type base layer 3 with a low dose of 1 × 10 ¹⁴ cm ⁻² or less while forming it with a size of Wp = 8 μm. .

However, when the p-type base layer 3 is simply formed separately without providing the trench groove 8 and the buried electrode 10 as shown in FIG. 1, as the area occupation ratio of the p-type base layer 3 is reduced, The static withstand voltage (V _DSS ) of the device and the sustain voltage (V _{DSX (SUS)} , surge withstanding capacity) at turn-off decrease,
In some cases, the device may be destroyed. In Fig. 6, the △ mark and ×
The points indicated by marks correspond to this.

FIG. 7 shows the dependence of the current gain and the static breakdown voltage on the dose amount of the p-type base layer. When the p-type base layer 3 is simply formed without providing the trench groove 8 and the buried electrode 10 as shown in FIG. 1, the breakdown voltage decreases as shown by the dotted line in FIG. This is for the following reason. When a high voltage is generated due to the blocking state (off state) of the device or turn-off, n
The breakdown voltage is maintained by the junction between the mold base layer 1 and the p-type base layer 3. When the p-type base layer 3 is formed separately and separated from each other, a corner portion (edge portion at the bottom) of the p-type base layer 3 is formed.
In this case, the electric field strength increases, and the element breakdown voltage and the sustain voltage decrease.

On the other hand, in the semiconductor device of the present invention,
Since the trench groove 8 is formed, the electric field strength does not increase at the corners of the p-type base layer 3, and the p-type base layer 3
It is possible to make the distance from the edge of the depletion layer to the edge of the depletion layer uniform. In addition, the depletion layer spreads from the adjacent trench grooves 8,
Since they are connected to each other and the shape of the depletion layer is flattened, a high breakdown voltage and a sustain voltage are maintained. As a specific example, as shown in FIG. 7, the static breakdown voltage is improved from the dotted line to the solid line (arrow A), and the static breakdown voltage is comparable to that when the p-type base layer 3 is formed with a high dose amount. .

FIG. 8 shows the dependence of the current gain on the area occupation ratio of the p-type base layer 3 and the n-type emitter layer 4. n
By setting the area occupancy of the p-type base layer 3 on the surface of the mold base layer 1 to 0.1 or less (point A), a high current gain can be realized without lowering the static withstand voltage and the sustain voltage.

On the other hand, the semiconductor device according to the first embodiment applies a negative voltage to the base terminal at the time of turn-off (FIG. 2, time t = t3). As a result, as shown in FIG. 9, the holes h accumulated in the n-type base layer 1 are discharged from the base electrode 5 to the outside of the element through the p-type base layer 3. As the holes h are discharged, the potential of the p-type base layer 3 becomes pn.
As a result of lowering to the built-in voltage of the junction or lower, electron injection from the n-type emitter layer 4 stops, and the device turns off (t = t3 to t4). At the time of turn-off, the holes h are discharged through the base electrode 5 provided adjacent to the n-type emitter layer 4, so that a semiconductor element having a high turn-off capability can be realized.

Further, in the off-state, a negative voltage is applied to the base terminal B to the emitter (t = t4.about.) After turn-off. As a result, the potential of the p-type base layer 3 is fixed to a negative potential via the base electrode 5, so that false ignition due to noise can be prevented.

As described above, according to the first embodiment, in the ON state, carriers of both electrons and holes are accumulated up to the deep position of the n-type base layer 1 to cause conductivity modulation, and Since carrier recombination in the p-type base layer 3 and the n-type emitter layer 4 is reduced, a high current gain (DC current amplification factor) can be realized. Further, at the time of turn-off, the holes h are discharged through the base electrode 5 provided adjacent to the n-type emitter layer 4, so that a high turn-off ability can be obtained. Further, since the electric field concentration at the end portion of the p-type base layer 3 is relaxed by the trench groove 8 and the embedded electrode 10, a high sustain voltage (surge withstand amount) is maintained. Further, in the off state, the embedded electrode 10
Since the depletion layers extending from are connected and the shape of the depletion layer is flattened, a high static breakdown voltage is maintained. Further, by applying a negative voltage to the base electrode 5 with respect to the emitter, the potential of the p-type base layer 3 is fixed to a negative potential, so that false ignition due to noise can be prevented. (Second Embodiment) FIG. 10 is a cross-sectional view showing a main structure of a semiconductor device according to a second embodiment of the present invention, which is a modification of the semiconductor device of FIG. In addition,
The same parts as those in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted, and only different parts will be described here.

In this embodiment, unlike the first embodiment shown in FIG. 1, a p + type layer 11 is formed adjacent to the n type emitter layer 4 on the p type base layer 3, and the p + type layer 11 is formed. The base electrode 5 is provided on the mold layer 11. This reduces the contact resistance of the base electrode 5,
Holes can be efficiently injected at the time of turn-on, and holes can be discharged earlier at the time of turn-off. This further reduces the on-voltage and switching time. (Third Embodiment) FIG. 11 is a cross-sectional view showing a main structure of a semiconductor element according to a third embodiment of the present invention, which is a modification of the semiconductor element shown in FIG.

In the present embodiment, unlike the first embodiment shown in FIG. 1, the buried electrode 10 and the emitter electrode 7 are electrically connected. As a result, the potential of the embedded electrode 10 is always fixed to the emitter potential, so that a high static withstand voltage and a sustain voltage can be obtained more stably. (Fourth Embodiment) FIG. 12 is a cross-sectional view showing a main structure of a semiconductor element according to a fourth embodiment of the present invention, which is a modification of the semiconductor element shown in FIG.

In this embodiment, unlike the first embodiment shown in FIG. 1, in the selectively formed p-type base layer 3, the n-type emitter layer 4 is formed in a region in contact with the trench groove 8. Has been formed. Thereby, the n-type emitter layer 4
Since the density of the electrons is increased, electrons are efficiently injected, and a lower on-voltage can be obtained. (Fifth Embodiment) FIG. 13 is a cross-sectional view showing a main structure of a semiconductor element according to a fifth embodiment of the present invention, which is a modification of the semiconductor element shown in FIG.

In this embodiment, unlike the first embodiment shown in FIG. 1, the embedded electrode 10 is directly and electrically connected by the base electrode 5. As a result, the structure is simplified and it can be formed by a simple manufacturing method. (Sixth Embodiment) FIG. 14 is a sectional view showing a main structure of a semiconductor element according to a sixth embodiment of the present invention, which is a modification of the semiconductor element shown in FIG.

In the present embodiment, unlike the first embodiment shown in FIG. 1, on the surface of the n-type base layer 1, p
A plurality of trench grooves 8 are formed in a region different from the mold base layer 3. This facilitates the step of forming the trench groove 8 and the step of burying the buried electrode 10 in the trench groove 8, and at the same time, the same effect as that of the first embodiment is realized. (Seventh Embodiment) FIG. 15 is a cross-sectional view showing the main structure of a semiconductor device according to a seventh embodiment of the present invention, which is a modification of the semiconductor device shown in FIG.

In the present embodiment, unlike the fifth embodiment shown in FIG. 13, the trench groove 8 is not completely filled with the buried electrode 10. That is, the embedded electrode 10 formed integrally with the base electrode 5 is embedded in the surface of the n-type base layer 1 via the insulating film 9.
Thereby, when forming the embedded electrode 10,
For example, it is not necessary to use a polysilicon deposition step by a chemical vapor deposition method (CVD method). Moreover, since the base electrode 5 can be collectively formed when the base electrode 5 is formed, for example, by the metal electrode forming step, the manufacturing process is simplified. (Eighth Embodiment) FIG. 16 is a perspective sectional view showing the structure of a main part of a semiconductor device according to an eighth embodiment of the present invention.

In the present embodiment, the sectional structure shown in FIG. 1 is formed uniformly along the depth direction (direction parallel to trench groove 8). As a result, the same effect as the effect described with reference to FIG. 1 is realized. (Ninth Embodiment) FIG. 17 is a perspective sectional view showing a main part structure of a semiconductor element according to a ninth embodiment of the present invention, which is a modification of the semiconductor element shown in FIG.

In the present embodiment, unlike the eighth embodiment shown in FIG. 16, the p-type base layer 3 is divided and formed in the depth direction (direction parallel to the trench groove 8). As a result, the area occupation ratio of the p-type base layer 3 and the n-type emitter layer 4 in the element region is further reduced, so that the current gain is further improved. (Tenth Embodiment) FIG. 18 shows a first embodiment of the present invention.
FIG. 17 is a perspective cross-sectional view showing the main part structure of the semiconductor element according to the embodiment of 0, and is a modification of the semiconductor element of FIG. 16.

In this embodiment, unlike the eighth embodiment shown in FIG. 16, the trench grooves 8 are provided in a lattice shape, and the trench grooves 8 are formed in both the x and y directions when viewed from the upper surface of the device. A cross-sectional structure similar to is formed. As a result, the area occupation ratio of the p-type base layer 3 and the n-type emitter layer 4 in the element region is effectively reduced, and at the same time, high static breakdown voltage and sustain voltage are maintained. (Eleventh Embodiment) FIG. 19 shows a first embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a main part structure of the semiconductor element according to the first embodiment.

In the present embodiment, the trench groove 8 is formed on the surface of the p-type base layer 3, and the depth of the trench groove 8 is deeper than the depth of the n-type emitter layer 4 and is p-type base layer 3.
Is formed shallower than the depth of. As a result, not only the electric field concentration on the corners of the p-type base layer 3 is eliminated but also the electric field concentration on the corners of the trench groove 8 is alleviated, so that the high static breakdown voltage and the sustain voltage are held more stably. It At the same time, since the volume occupation ratio of the p-type base layer 3 is reduced,
A high current gain is realized by a mechanism similar to that shown in FIG. In particular, when the p-type base layer 3 is formed by impurity diffusion from the surface of the n-type base layer 1, the impurity concentration of the p-type base layer 3 is higher as it is closer to the surface and the carrier lifetime is closer to the surface. Since it is small, the volume of the low lifetime region is reduced by the trench groove 8,
High current gain can be obtained.

Of course, various modifications can be made without departing from the scope of the invention.

[0044]

As described above in detail, according to the present invention, since the trench groove and the buried electrode are provided to reduce the electric field concentration at the end of the p-type base layer, the breakdown voltage of the element is lowered in the off state. Therefore, a high sustain voltage can be maintained even during turn-off. Further, in the ON state, carriers of both electrons and holes are accumulated to a deep position in the n-type base layer to cause conductivity modulation, and the p-type base layer 3 and the n-type emitter layer 4 are formed.
Since carrier recombination at is reduced, a high current gain (DC current amplification factor) can be obtained. As a result, it is possible to realize a semiconductor element having a low on-voltage, a high static breakdown voltage, and a breakdown resistance.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a main part structure of a semiconductor element according to a first embodiment of the present invention.

FIG. 2 is a time chart showing an operation and a base driving method according to the first embodiment.

FIG. 3 is a schematic diagram showing a flow of carriers in a conductive state according to the first embodiment.

FIG. 4 is a diagram showing a carrier concentration distribution in a conductive state according to the first embodiment.

FIG. 5 shows a current flowing through a semiconductor device according to the first embodiment.
The characteristic view which compares and shows the voltage characteristic and the current-voltage characteristic of the conventional power transistor.

FIG. 6 is a characteristic diagram showing the p-type base layer width dependence of the current gain in the first embodiment.

FIG. 7 is a characteristic diagram showing the dependence of the current gain and the static breakdown voltage on the p-type base layer dose amount in the first embodiment.

FIG. 8 is a characteristic diagram showing the dependence of the current gain on the high-concentration layer area in the first embodiment.

FIG. 9 is a schematic diagram showing the flow of carriers at the time of turn-off in the first embodiment.

FIG. 10 is a cross-sectional view showing a main part structure of a semiconductor element according to a second embodiment of the present invention.

FIG. 11 is a sectional view showing a main part structure of a semiconductor element according to a third embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a main part structure of a semiconductor element according to a fourth embodiment of the present invention.

FIG. 13 is a sectional view showing a main part structure of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 14 is a cross-sectional view showing a main structure of a semiconductor element according to a sixth embodiment of the present invention.

FIG. 15 is a cross-sectional view showing the main part structure of a semiconductor element according to a seventh embodiment of the present invention.

FIG. 16 is a perspective sectional view showing a main structure of a semiconductor element according to an eighth embodiment of the present invention.

FIG. 17 is a perspective sectional view showing a main part structure of a semiconductor element according to a ninth embodiment of the present invention.

FIG. 18 is a perspective sectional view showing a main part structure of a semiconductor device according to a tenth embodiment of the invention.

FIG. 19 is a sectional view showing a main part structure of a semiconductor element according to an eleventh embodiment of the present invention.

FIG. 20 is a sectional view showing the configuration of a conventional npn-type power transistor.

FIG. 21 is a schematic diagram showing a flow of carriers in an ON state in a conventional npn type power transistor.

FIG. 22 is a diagram showing Darlington connection when a conventional npn type power transistor is used.

23 is a characteristic diagram showing current-voltage characteristics of the configuration shown in FIG.

[Explanation of symbols]

1, 1a ... High resistance n-type base layer 2, 2a ... n type collector layer 3, 3a ... p-type base layer 4, 4a ... N-type emitter layer 5, 5a ... Base electrode 6, 6a ... Collector electrode 7, 7a ... Emitter electrode 8 ... Trench groove 9 ... Insulating film 10 ... Embedded electrode 11 ... p + type layer (high concentration p type layer)

Claims (8)

[Claims] 1. A high-conductivity first conductivity type base layer, a first conductivity type collector layer formed on one surface of the first conductivity type base layer, and the other of the first conductivity type base layer. A second conductive type base layer selectively formed on the surface, a first conductive type emitter layer selectively formed on the surface of the second conductive type base layer, and the other of the first conductive type base layer A trench groove formed on a surface of the second conductivity type base layer in a region different from that of the second conductivity type base layer; and adjacent to the first conductivity type emitter layer formed on a surface of the second conductivity type base layer. A formed base electrode; a first main electrode formed on the surface of the first conductivity type collector layer; and a second main electrode formed on the surface of the first conductivity type emitter layer. A semiconductor device characterized by the above. 2. The second conductive layer is formed on the surface of the first conductive type base layer.
The semiconductor element according to claim 1, wherein an area occupation ratio of the conductive type base layer is 0.1 or less. 3. The semiconductor device according to claim 1, wherein a buried electrode is formed in the trench structure via an insulating film. 4. The semiconductor element according to claim 3, wherein the embedded electrode is electrically connected to the second main electrode or the base electrode. 5. The semiconductor device according to claim 1, wherein a depth of the trench groove is deeper than a depth of the second conductivity type base layer. 6. A high resistance first conductivity type base layer, a first conductivity type collector layer formed on one surface of the first conductivity type base layer, and the other of the first conductivity type base layer. A second conductivity type base layer selectively formed on the surface, a first conductivity type emitter layer selectively formed on the surface of the second conductivity type base layer, and a surface of the second conductivity type base layer A trench groove selectively formed in the first conductive layer, a base electrode formed on the surface of the second conductive type base layer and adjacent to the first conductive type emitter layer, and the first conductive type collector. A semiconductor element comprising: a first main electrode formed on the layer; and a second main electrode formed on the first conductivity type emitter layer. 7. The semiconductor device according to claim 6, wherein an area occupation ratio of a region where the trench groove is not formed on the surface of the second conductivity type base layer is 0.1 or less. . 8. The depth of the trench groove is shallower than the depth of the second conductive type base layer and deeper than the depth of the first conductive type emitter layer. Semiconductor device.