JP2001274400A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize ensuring load short-circuit endurance and reduction of ON-state voltage and input capacitance of a trench gate type IGBT. SOLUTION: In a trench gate type IGBT, a P-type base region is formed in a stripe-shape in the direction perpendicular to the direction of a trench gate. Channel lengths of the respective unit cells are formed to be almost constant, and equal to or shorter than those of the conventional trench IGBT.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device, and more particularly to a trench gate type MOS device.
For example, trench gate type IGBT, power MOSFET
It is used for such purposes.

[0002]

2. Description of the Related Art Conventionally, in a trench gate type MOS device, a base region in which a channel is formed has been formed over the entire device region.

FIGS. 13 (a) to 13 (d) show an example of a conventional trench gate type IGBT. FIG. 13 (a) is a perspective view schematically showing a part of the IGBT, and FIG. ) Is a cross-sectional view taken along line AA ′ in FIG. (A), FIG. (C) is a cross-sectional view taken along line BB ′ in FIG. (A), and FIG. FIG. 3A is a perspective view partially cut away for explaining a surface state of a gate insulating film when a forward bias is applied between a gate electrode and an emitter electrode in FIG.

In FIGS. 13A to 13 C, a p-type base layer 2 is formed over the entire surface region of a semiconductor substrate having an n − -type base layer 1. P-type base layer 2 from the surface
Is formed to reach the n − -type base layer 1, and a gate insulating film 4 and a gate electrode 5 are provided in the groove 3. An n + emitter layer 6 is formed in a portion of the surface region of the mold base layer 2 which is in contact with the groove 3. The emitter electrode 7 is formed so as to be connected to both the n + -type emitter layer 6 and the p-type base layer 2. A p-type collector layer 8 and a collector electrode 9 are formed on the back surface of the semiconductor substrate.

Next, the operation of the trench gate type IGBT will be described with reference to FIGS. 14 (a), 14 (b) and 13 (d).
This will be described with reference to FIG.

When a forward bias is applied between the collector electrode 9 and the emitter electrode 7 and a forward bias is applied between the gate electrode 5 and the emitter electrode 7 as shown in FIG. As shown in d), an n + -type inversion layer 101 (channel) is formed in the surface region of the gate insulating film 4 in the p-type base layer 2.

As a result, as shown in FIG.
Electrons are injected from the n + -type emitter layer 6 into the n − -type base layer 1 via the n + -type inversion layer 101, and holes are injected from the p-type collector layer 8 into the n − -type base layer 1. As a result, conduction between the collector electrode 9 and the emitter electrode 7 is established. At this time, as shown in FIG. 14B, an n + type accumulation layer 102 is formed in the surface region of the gate insulating film 4 in the n− type base layer 1.

On the other hand, when a zero bias or a reverse bias is applied between the gate electrode 5 and the emitter electrode 7,
The n + type inversion layer 101 (channel) disappears, and the current flowing between the collector electrode 9 and the emitter electrode 7 is cut off.

[0009]

As described above, in the conventional trench gate type IGBT, the p-type base region 2 in which the channel is formed is formed on the entire surface of the element region. In addition, there is a problem that the load short-circuit withstand capability is reduced and the input capacitance is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a semiconductor device capable of securing load short-circuit withstand capability, reducing on-voltage, and reducing input capacitance.

[0011]

According to a first semiconductor device of the present invention, there is provided a semiconductor substrate having a first conductivity type base layer, and a stripe pattern in which a band-like pattern is intermittently repeated on a first main surface of the semiconductor substrate. A second conductivity type base layer selectively formed so as to have a planar pattern of: a first conductivity type emitter layer selectively formed on a surface portion of the second conductivity type base layer;
The first main surface of the semiconductor substrate intersects the direction of the strip pattern of the second conductive type base layer, and penetrates the first conductive type emitter layer and the second conductive type base layer from the surface to form the first conductive type base layer. A groove formed to a depth reaching the inside of the mold base layer; a gate electrode formed in the premise via an insulating layer; and a first conductive type emitter layer at an intermediate portion between adjacent regions of the groove. An emitter electrode formed to be connected to the second conductivity type base layer;
A second conductivity type collector layer formed on the main surface of
And a collector electrode formed to be connected to the conductivity type collector layer.

Here, a distance from a junction between the first conductivity type base layer and the second conductivity type base layer to a junction between the second conductivity type base layer and the first conductivity type emitter layer on a side wall surface of the groove. However, it is desirable that the width be substantially constant on the side wall surface of each groove.

The first conductive type in an intermediate portion between adjacent regions of the groove is located at a position closer to the junction between the first conductive type base layer and the second conductive type base layer on the side wall surface of the groove. The junction between the base layer and the second conductivity type base layer may be deeper.

Further, the emitter electrode is connected to a second conductive type base layer in an inter-region adjacent to the groove and the first conductive type base layer.
The conductive type emitter layer may be formed only in a part of all units on the semiconductor chip.

According to a second semiconductor device of the present invention, there is provided a semiconductor substrate having a first conductivity type base layer, and a first substrate of the semiconductor substrate.
A second conductive type base layer selectively formed so as to have a striped planar pattern in which a band-shaped pattern intermittently repeats on the main surface of the second conductive type base layer; The first conductive type emitter layer and the second conductive type base layer on the first main surface of the semiconductor substrate in the direction of the strip pattern, and from the surface, the first conductive type emitter layer and the second conductive type base. A groove formed to a depth penetrating a layer and reaching the inside of the first conductivity type base layer; a gate electrode formed in the premise via an insulating layer; and a groove formed in the second conductivity type base layer. A second conductivity type contact layer selectively formed in the vicinity of the first conductivity type emitter layer at an intermediate portion between adjacent inter-regions; and a first conductivity type contact layer at an intermediate portion between the adjacent inter-regions in the trench. Emitter layer and second conductive type contact layer An emitter electrode formed so as to connect the second formed in the second main surface of the semiconductor substrate
It is characterized by comprising a conductive type collector layer and a collector electrode formed so as to be connected to the second conductive type collector layer.

Here, a distance from a junction between the first conductivity type base layer and the second conductivity type base layer to a junction between the second conductivity type base layer and the first conductivity type emitter layer on the side wall surface of the groove. However, it is desirable that the width be substantially constant on the side wall surface of each groove.

The position of the first conductive type base layer and the second conductive type base layer at the junction between the first conductive type base layer and the second conductive type base layer on the side wall surface of the groove may be larger than that of the first conductive type base layer. The junction between the base layer and the second conductivity type base layer may be deeper.

Further, the emitter electrode may be a part of the whole unit on the semiconductor chip using the second conductive type contact layer and the first conductive type emitter layer as a unit in an inter-region adjacent to the trench. May be formed only on the surface.

Further, a second conductivity type drain layer is selectively formed on a portion of the first main surface of the semiconductor substrate where the second conductivity type base layer is not formed, and the second conductivity type drain layer is formed. It may be formed so as to connect the drain electrode to the layer.

According to a third semiconductor device of the present invention, there is provided a semiconductor substrate having a first conductivity type base layer;
A second conductive type base layer selectively formed so as to have a striped planar pattern in which a band-shaped pattern intermittently repeats on the main surface of the second conductive type base layer; The first conductive type source layer and the first conductive type source layer and the second conductive type base which intersect with the direction of the strip pattern of the second conductive type base layer on the first main surface of the semiconductor substrate. A groove formed to a depth reaching the inside of the first conductivity type base layer through a layer, a gate electrode formed in the premise via an insulating layer, and an intermediate portion between adjacent regions of the groove The first conductivity type source layer and the second conductivity type
A source electrode formed to be connected to the conductive type base layer; a first conductive type drain layer formed on the second main surface of the semiconductor substrate; and a source electrode formed to be connected to the first conductive type drain layer. And a drain electrode provided.

Here, on the side wall surface of the groove, a portion from the junction between the first conductivity type base layer and the second conductivity type base layer to the junction between the second conductivity type base layer and the first conductivity type source layer is provided. It is desirable that the distance be substantially constant on the side wall surface of each groove.

The position of the first conductive type base layer and the second conductive type base layer on the side wall surface of the groove is more than the position of the first conductive type base layer and the second conductive type base layer in the intermediate portion of the adjacent region of the groove. It is also possible to make the junction between the base layer and the second conductivity type base layer deeper.

[0023]

Embodiments of the present invention will be described below in detail with reference to the drawings.

<Embodiment 1> FIGS. 1 (a) to 1 (d)
Is a trench gate type IG according to the first embodiment of the present invention.
FIG. 2A is a perspective view schematically showing a BT taken out, and FIG. 2B is a perspective view of the BT shown in FIG.
A cross-sectional view along the line A ', and FIG.
FIG. 4D is a cross-sectional view taken along the line B ′, and FIG. 4D is partially cut to explain the surface state of the gate insulating film when a forward bias is applied between the gate electrode and the emitter electrode in FIG. FIG.

1A to 1C, a p-type base layer 2 is formed on a first main surface (a surface region of the n-type base layer 1) of a semiconductor substrate having an n-type base layer 1. ing. In this case, the p-type base layer 2 is selectively formed so as to have a striped planar pattern in which the strip pattern repeats intermittently on the first main surface.

A groove 3 penetrating the p-type base layer 2 from the surface and reaching the n − -type base layer 1 is formed so as to intersect with the p-type base layer 2. A gate electrode 5 is provided through the gate electrode 4. And p
An n + emitter layer 6 is formed in the surface region of the mold base layer 2 so as to be in contact with the groove 3. In other words, the groove 3 is formed at a depth penetrating the n + emitter layer 6 and the p-type base layer 2 and reaching the inside of the n- type base layer 1. In this example, the case where the groove 3 is formed so as to be orthogonal to the p-type base layer 2 is illustrated.

An emitter electrode 7 is formed so as to be connected to both the n + type emitter layer 6 and the p type base layer 2. Further, a p-type collector layer 8 and a collector electrode 9 are formed on the back surface of the semiconductor substrate.

The junction between the n − type base layer 1 and the p type base layer 2 on the surface of the gate insulating film 4 (the side wall surface of the groove) is denoted by B, and the p type base layer 2 on the surface of the gate insulating film 4 is denoted by B.
When the junction between N + and n + type emitter layer 6 is represented by A, FIG.
As shown in (c), the p-type base layer 2 has a junction A and a junction B
Is formed so that the distance between the first and second grooves is substantially constant on the side wall surface of each groove. Such a structure is realized by, for example, a combination of multiple times of impurity ion implantation and thermal diffusion.

Next, the operation of the trench gate type IGBT will be described with reference to FIG.

When a forward bias is applied between the collector electrode 9 and the emitter electrode 7 and a forward bias is applied between the gate electrode 5 and the emitter electrode 7 as shown in FIG. In the surface region of the gate insulating film 4 in the layer 2 (the region where the p-type base layer 2 and the gate insulating film 4 are in contact), n +
A pattern inversion layer 101 (channel) is formed.

As a result, electrons are injected from the n + -type emitter layer 6 to the n − -type base layer 1 via the n + -type inversion layer 101, and holes are injected from the p-type collector layer 8 to the n − -type base layer 1. Is done. As a result, conduction between the collector electrode 9 and the emitter electrode 7 is established.

On the other hand, when a zero bias or a reverse bias is applied between the gate electrode 5 and the emitter electrode 7,
The n + type inversion layer 101 (channel) disappears, and the current flowing between the collector electrode 9 and the emitter electrode 7 is cut off.

At the time of conduction of the above-mentioned trench gate type IGBT, as shown in FIG. 1D, the distance (channel length) between junction A and junction B is constant, so that the channel width of the conventional trench gate type IGBT is small. , The channel resistance is equivalent to that of the conventional trench gate type lGBT. Here, the channel width represents the length of the junction B.

Therefore, when a large current flows when the load of the trench gate type IGBT is short-circuited, the channel and n +
Since the electron current density increases at the boundary with the mold emitter layer 6 and becomes saturated, the current flowing through the element is limited, and the breakdown strength is improved.

As can be seen from a comparison between the surface condition of the gate insulating film shown in FIG. 1D and the surface condition of the gate insulating film of the conventional trench gate type IGBT shown in FIG. 3 is the same as the conventional trench gate type IGBT, the conventional trench gate type IGBT
The region where the groove 3 protrudes into the n − -type base layer 1 is smaller than that of the BT. This is a conventional trench gate type IGB
This is equivalent to making the groove 3 deeper at T. That is, FIG.
In FIG. 2B, in the region C where the groove 3 protrudes greatly from the n − -type base layer 1, the hole discharge resistance increases during conduction, so that carriers are accumulated and the resistance decreases. Thereby, the ON voltage of the trench gate type IGBT is reduced.

As shown in FIG. 1D, the surface region of the gate insulating film 4 in the n − type base layer 1 (the region where the n − type base layer 1 and the gate insulating film 4 are in contact) is As described above, when a forward bias is applied between the gate electrode 5 and the emitter electrode 7, the n + type accumulation layer 102 is formed. FIG.
As can be seen from the comparison between FIG. 13D and FIG.
Is the same as that of the conventional trench gate type IGBT, in this example, the area where the trench 3 is in contact with the n − type base layer 1 is larger than that of the conventional trench gate type IGBT.
Therefore, the area of n + type accumulation layer 102 generated on the surface of trench 3 is larger than that of the conventional trench gate type IGBT. If the area of the n + type accumulation layer 102 is large, the emission of electrons during conduction is promoted, and the efficiency of electron injection is improved.
The ON voltage of the trench gate type IGBT is reduced.

The input capacitance of the trench gate type IGBT is the capacitance between the gate electrode 5 and the emitter electrode 7,
It is substantially proportional to the area where the groove 3 and the p-type base layer 2 are in contact.
As can be seen from a comparison between FIG. 1 (d) and FIG. 13 (d),
In this example, the groove 3 is compared with the conventional trench gate type IGBT.
And the area where the p-type base layer 2 is in contact is small. Therefore, as compared with the conventional trench gate type IGBT, the input capacitance is reduced, and not only the driving power can be reduced, but also the power loss at the time of turn-on and at the time of turn-off can be reduced.

<Second Embodiment> The trench gate type IGBT according to the first embodiment described above has a structure in which the junction B between the n − type base layer 1 and the p
The distance from the mold base layer 2 to the junction A of the n + -type emitter layer 6 is substantially constant on the side wall surface of each groove 3 and
The case where the depth position of the junction B on the side wall surface of the groove 3 and the depth position of the junction B in the middle part of the adjacent region of the groove 3 are substantially the same, It is also possible to configure so that the depth position of the junction B is different from the height position and the intermediate portion of the adjacent region between the grooves 3, and an example thereof will be described below.

FIGS. 2A to 2C show a trench gate type IGBT according to a second embodiment of the present invention, and FIG. FIG. 2B is a sectional view taken along line AA ′ in FIG. 2A, and FIG. 2C is a sectional view taken along line BB ′ in FIG.

The trench gate type IGBT is different from the trench gate type IGBT according to the first embodiment in that the trench 3
The depth position of the junction B in the middle part of the adjacent region of the groove 3 is configured to be deeper than the depth position of the junction B on the side wall surface. That is, the p-type base layer 2
Is deep in the middle of the adjacent area between the grooves 3 and
Is formed shallow in a region in contact with. Further, the distance (channel length) between junctions A and B on the side wall surface of trench 3 is formed shorter than the channel length of trench gate IGBT according to the first embodiment. The distance between the joints A and B on the side wall surface of each groove 3 is substantially constant. Others are shown in Fig. 1 (a)
Since they are the same as those in FIGS.

The operation and effect of this trench gate type IGBT are described in the first embodiment with reference to FIG.
Is basically the same as the operation of the trench gate type IGBT according to the above.

Further, according to the trench gate type IGBT, when conducting, the distance (channel length) between junctions A and B is constant, and the channel length of trench gate type IGBT according to the first embodiment. If it is shorter and has a channel width (length of the junction B) equal to that of the conventional trench gate IGBT, the channel resistance is equal to or less than the channel resistance of the conventional trench gate IGBT.

Therefore, when a large current flows when the load of the trench gate type IGBT is short-circuited, the channel and n +
Since the electron current density increases at the boundary with the mold emitter layer 6 and becomes saturated, the current flowing through the element is limited, and the breakdown strength is improved.

For the same reason as in the trench gate type IGBT according to the first embodiment, when the search for the groove 3 is the same as that of the conventional trench gate type IGBT, compared to the conventional trench gate type IGBT, The region where the groove 3 protrudes into the n − type base layer 1 is small. This is equivalent to making the trench 3 deeper in the conventional trench gate type IGBT. That is, in FIG. 2B, in the region C where the groove 3 protrudes greatly from the n − -type base layer 1, the hole discharge resistance increases during conduction, so that carriers are accumulated and the resistance decreases. Thereby, the trench gate type IG
The ON voltage of the BT is reduced.

As described above, the surface of the gate insulating film 4 in the n − type base layer 1 (the region where the n − type base layer 1 is in contact with the gate insulating film 4) is provided with the gate electrode 5 and the emitter electrode 4. N + type storage layer when a forward bias is applied between
102 is formed. For the same reason as in the trench gate type IGBT according to the first embodiment, when the search for the groove 3 is the same as that of the conventional trench gate type IGBT, the groove 3 in the present example is smaller than that of the conventional trench gate type IGBT. n-
The area in contact with the mold base layer 1 is large. Therefore,
The area of the n + type accumulation layer 102 generated on the surface of the trench 3 is wider than that of the conventional trench gate type IGBT. If the area of the n + -type storage layer 102 is large, the emission of electrons during conduction is promoted and the efficiency of electron injection is improved, so that the on-voltage of the trench gate IGBT is reduced.

The input capacitance of the trench gate type IGBT is the capacitance between the gate electrode 5 and the emitter electrode 7,
It is substantially proportional to the area where the groove 3 and the p-type base layer 2 are in contact.
For the same reason as in the trench gate type IGBT according to the first embodiment, the conventional trench gate type IGBT
In this example, the area where the groove 3 and the p-type base layer 2 are in contact with each other is small. Therefore, the conventional trench gate type IG
As compared with the BT, the input capacitance is reduced, and not only the driving power can be reduced, but also the power loss at the time of turning on and at the time of turning off can be reduced.

<Third Embodiment> The first embodiment described above,
2. The trench gate type IGBT according to FIG.
Is the p-type base layer 2 in the region between adjacent grooves 3
And the n + type emitter layer 6 as a unit has been described for all units on the semiconductor chip. However, it is also possible to omit some of the emitter electrodes 7, and an example thereof will be described below. I do.

FIGS. 3A to 3C show a trench gate type IGBT according to a third embodiment of the present invention. FIG. 3A is a perspective view showing a part of the trench gate type IGBT. FIG. 2B is a sectional view taken along line AA ′ in FIG. 2A, and FIG. 2C is a sectional view taken along line BB ′ in FIG.

The trench gate type IGBT is different from the trench gate type IGBT according to the first embodiment in that the trench 3
The emitter electrode 7 is formed only in a part of all the units on the semiconductor chip in which the p-type base layer 2 and the n + -type emitter layer 6 are used as a unit in an adjacent inter-region.
In other words, there is a point that the emitter electrode does not exist even if the n + -type emitter layer 6 or the p-type base layer 2 exists, and the other parts are the same as those in FIGS. Is attached.

The operation and effect of the trench gate type IGBT are basically the same as the operation of the trench gate type IGBT according to the first embodiment described above. As compared with the trench gate type IGBT according to the first embodiment, the hole discharge resistance during conduction is further increased, so that the accumulation of carriers occurs, the resistance becomes lower, and the on-voltage is further reduced.

<Fourth Embodiment> In a trench gate IGBT according to a fourth embodiment, a part of the emitter electrode 7 of the trench gate IGBT according to the second embodiment is omitted according to the third embodiment.

FIGS. 4A to 4C show a trench gate type IGBT according to a fourth embodiment of the present invention, and FIG. 4A is a perspective view schematically showing a part of the IGBT taken out. FIG. 2B is a sectional view taken along line AA ′ in FIG. 2A, and FIG. 2C is a sectional view taken along line BB ′ in FIG.

This trench gate type IGBT is different from the trench gate type IGBT according to the second embodiment in that n +
The point that the emitter electrode does not exist even if the p-type base layer 2 or the p-type base layer 2 exists, and the other parts are the same as those in FIGS. ing.

The operation and effect of the trench gate type IGBT are basically the same as the operation of the trench gate type IGBT according to the second embodiment described above. As compared with the trench gate type IGBT according to the second embodiment, the hole discharge resistance during conduction is further increased, so that carriers are accumulated, the resistance is further reduced, and the ON voltage is further reduced.

<Embodiment 5> Each Embodiment 1 described above.
In the trench gate type IGBTs according to the first to fourth embodiments, the case where the emitter electrode 7 is connected to the p-type base layer 2 and the n + -type emitter layer 6 in the inter-region adjacent to the trench 3 has been described. It is also possible to selectively form a p-type contact layer in No. 2 and connect an emitter electrode to the p-type contact layer and the n + -type emitter layer, examples of which are described below.

FIGS. 5A to 5C show a trench gate type IGBT according to a fifth embodiment of the present invention, and FIG. 5A is a perspective view schematically showing a part of the trench gate type IGBT. FIG. 2B is a sectional view taken along line AA ′ in FIG. 2A, and FIG. 2C is a sectional view taken along line BB ′ in FIG.

The trench gate type IGBT is different from the trench gate type IGBT according to the first embodiment in that the trench 3
The p + contact layer 11 is selectively formed near the n + type emitter layer 6 in the middle part of the adjacent inter-region, and the n + type emitter layer and p +
The difference is that the emitter electrode 7 is formed on the contact layer 11, and the other parts are the same as those in FIGS.

The operation and effect of the trench gate type IGBT are basically the same as the operation of the trench gate type IGBT according to the first embodiment described above. However, since the p + type contact layer 11 is provided, the p type base layer The resistance of holes to be discharged in 2 is reduced, latch-up can be prevented, and the breakdown strength is further improved.

<Sixth Embodiment> In a trench gate type IGBT according to a sixth embodiment, the p-type base layer 2 of the trench gate type IGBT according to the second embodiment is selectively p-type according to the fifth embodiment. A contact layer is formed, and an emitter electrode is connected to the p-type contact layer and the n + -type emitter layer.

FIGS. 6A to 6C show a trench gate type IGBT according to a sixth embodiment of the present invention. FIG. 6A is a perspective view schematically showing a part of the trench gate type IGBT. FIG. 2B is a sectional view taken along line AA ′ in FIG. 2A, and FIG. 2C is a sectional view taken along line BB ′ in FIG.

The trench gate type IGBT is different from the trench gate type IGBT according to the second embodiment in that
The p + contact layer 11 is selectively formed near the n + type emitter layer 6 in the middle part of the adjacent inter-region, and the n + type emitter layer and p +
The difference is that the emitter electrode 7 is formed on the contact layer 11, and the other parts are the same as those in FIGS.

The operation and effect of the trench gate type IGBT are basically the same as the operation of the trench gate type IGBT according to the second embodiment described above. However, since the p + type contact layer 11 is provided, the p type base layer The resistance of holes to be discharged in 2 is reduced, latch-up can be prevented, and the breakdown strength is further improved.

<Seventh Embodiment> In a trench gate type IGBT according to a seventh embodiment, p-type base layer 2 of trench trench type IGBT according to the third embodiment is selectively p-type according to the fifth embodiment. A contact layer is formed, and an emitter electrode is connected to the p-type contact layer and the n + -type emitter layer.

7A to 7C show a trench gate type IGBT according to a seventh embodiment of the present invention. FIG. 7A is a perspective view schematically showing a part of the trench gate type IGBT. FIG. 2B is a sectional view taken along line AA ′ in FIG. 2A, and FIG. 2C is a sectional view taken along line BB ′ in FIG.

The trench gate type IGBT is different from the trench gate type IGBT according to the third embodiment in that the trench 3
The p + contact layer 11 is selectively formed near the n + type emitter layer 6 in the middle part of the adjacent inter-region, and the n + type emitter layer and p +
The difference is that the emitter electrode 7 is formed on the contact layer 11, and the other parts are the same as those in FIGS.

The operation and effect of the trench gate type IGBT are basically the same as the operation of the trench gate type IGBT according to the third embodiment. However, since the p + type contact layer 11 is provided, the p type base layer The resistance of holes to be discharged in 2 is reduced, latch-up can be prevented, and the breakdown strength is further improved.

Eighth Preferred Embodiment In a trench gate type IGBT according to an eighth preferred embodiment, p-type base layer 2 of trench trench type IGBT according to the fourth preferred embodiment is selectively p-type according to the fifth preferred embodiment. A contact layer is formed, and an emitter electrode is connected to the p-type contact layer and the n + -type emitter layer.

FIGS. 8A to 8C show a trench gate type IGBT according to an eighth embodiment of the present invention, and FIG. 8A is a perspective view schematically showing a part of the trench gate type IGBT. FIG. 2B is a cross-sectional view taken along line AA ′ of FIG. 2A, and FIG. 2C is a cross-sectional view taken along line BB ′ of FIG.

This trench gate type IGBT is different from trench gate type IGBT according to the fourth embodiment in that grooves 3
The p + contact layer 11 is selectively formed near the n + type emitter layer 6 in the middle part of the adjacent inter-region, and the n + type emitter layer and p +
The difference is that the emitter electrode 7 is formed on the contact layer 11, and the other parts are the same as those in FIGS.

The operation and effect of the trench gate type IGBT are basically the same as the operation of the trench gate type IGBT according to the fourth embodiment. However, since the p + type contact layer 11 is provided, the p type base layer The resistance of holes to be discharged in 2 is reduced, latch-up can be prevented, and the breakdown strength is further improved.

<Embodiment 9> Each of Embodiments 1 and 2 described above.
In the trench gate type IGBT according to any one of the first to eighth embodiments, only the n + emitter layer 6 is provided in the surface region of the p-type base layer 2 so as to be in contact with the groove 3; It is also possible to form a p + type drain layer instead of the n + emitter layer 6 so as to be in contact with the groove in some of the p type base layers 2 and to connect a drain electrode to this p + type drain layer. An example will be described below.

FIGS. 9A to 9C show a trench gate type IGBT according to a ninth embodiment of the present invention, and FIG. 9A is a perspective view schematically showing a part of the trench gate type IGBT. FIG. 2B is a sectional view taken along line AA ′ in FIG. 2A, and FIG. 2C is a sectional view taken along line BB ′ in FIG.

In this trench gate type IGBT, the n + emitter layer 6 or the p + type drain layer 21 are alternately grooved in the arrangement of the striped p-type base layers 2 as compared with the trench gate type IGBT according to the fifth embodiment. 3 is formed. The difference is that the drain electrode 22 is formed so as to be connected to the p + type drain layer 21.
Since they are the same as those in (a) to (c), they are denoted by the same reference numerals. A p + type contact layer 11 is formed in the vicinity of the n + type emitter layer 6.
The emitter electrode 7 is formed so as to be connected to both of the + -type contact layers 11.

The operation and effect of the trench gate type IGBT are basically the same as the operation of the trench gate type IGBT according to the fifth embodiment described above. However, since the trench gate type IGBT has the p + type drain layer 21 and the drain electrode 22, Hole discharge resistance in the p-type base layer 2 is further reduced, the effect of preventing latch-up is increased, and the breakdown strength is further improved.

Tenth Preferred Embodiment In a trench gate type IGBT according to a tenth preferred embodiment, an arrangement of striped p-type base layers 2 of the trench gate type IGBT according to the sixth preferred embodiment according to the ninth preferred embodiment. N + emitter layer 6 alternately within
Alternatively, the p + -type drain layer 21 was formed so as to be in contact with the trench 3, and the drain electrode 22 was connected to the p + -type drain layer 21.

FIGS. 10 (a) to 10 (c) show a trench gate type IGBT according to a tenth embodiment of the present invention, and FIG. FIG. 2B is a sectional view taken along line AA ′ in FIG. 2A, and FIG. 2C is a sectional view taken along line BB ′ in FIG.

The trench gate type IGBT according to the sixth embodiment is different from the trench gate type IGBT according to the sixth embodiment in that the n + emitter layer 6 or the p + type drain layer 21 is alternately grooved in the arrangement of the striped p-type base layers 2. 3 is formed. The difference is that the drain electrode 22 is formed so as to be connected to the p + drain layer 21.
Since they are the same as those in (a) to (c), they are denoted by the same reference numerals. A p + type contact layer 11 is formed in the vicinity of the n + type emitter layer 6.
The emitter electrode 7 is formed so as to be connected to both of the + -type contact layers 11.

The operation and effect of the trench gate type IGBT are basically the same as the operation of the trench gate type IGBT according to the sixth embodiment described above. However, since the trench gate type IGBT has the p + type drain layer 21 and the drain electrode 22, Hole discharge resistance in the p-type base layer 2 is further reduced, the effect of preventing latch-up is increased, and the breakdown strength is further improved.

Eleventh Embodiment In a trench gate type IGBT according to an eleventh embodiment, the arrangement of the striped p-type base layer 2 of the trench gate type IGBT according to the seventh embodiment is based on the ninth embodiment. N + emitter layer 6 alternately within
Alternatively, the p + -type drain layer 21 was formed so as to be in contact with the trench 3, and the drain electrode 22 was connected to the p + -type drain layer 21.

FIGS. 11 (a) to 11 (c) show a trench gate type IGBT according to an eleventh embodiment of the present invention, and FIG. 11 (a) is a perspective view schematically showing a part of the trench gate type IGBT. FIG. 2B is a sectional view taken along line AA ′ in FIG. 2A, and FIG. 2C is a sectional view taken along line BB ′ in FIG.

The trench gate type IGBT according to the seventh embodiment differs from the trench gate type IGBT according to the seventh embodiment in that the n + emitter layer 6 or the p + type drain layer 21 is alternately grooved in the arrangement of the striped p-type base layers 2. 3 is formed. The difference is that the drain electrode 22 is formed so as to be connected to the p + type drain layer 21.
Since they are the same as those in (a) to (c), they are denoted by the same reference numerals. A p + type contact layer 11 is formed in the vicinity of the n + type emitter layer 6.
The emitter electrode 7 is formed so as to be connected to both of the + -type contact layers 11. Further, there are portions where the emitter electrode 7 does not exist even if the n + emitter layer 6 or the p + type contact layer 11 exists.

The operation and effect of the trench gate type IGBT are basically the same as the operation of the trench gate type IGBT according to the above-described seventh embodiment, but include the p + type drain layer 21 and the drain electrode 22. Hole discharge resistance in the p-type base layer 2 is further reduced, the effect of preventing latch-up is increased, and the breakdown strength is further improved.

<Twelfth Embodiment> In a trench gate type IGBT according to a twelfth embodiment, the arrangement of the striped p-type base layer 2 of the trench gate type IGBT according to the eighth embodiment is based on the ninth embodiment. N + emitter layer 6 alternately within
Alternatively, the p + -type drain layer 21 was formed so as to be in contact with the trench 3, and the drain electrode 22 was connected to the p + -type drain layer 21.

FIGS. 12 (a) to 12 (c) show a trench gate type IGBT according to an eleventh embodiment of the present invention, and FIG. FIG. 2B is a sectional view taken along line AA ′ in FIG. 2A, and FIG. 2C is a sectional view taken along line BB ′ in FIG.

The trench gate type IGBT according to the eighth embodiment is different from the trench gate type IGBT according to the eighth embodiment in that the n + emitter layer 6 or the p + type drain layer 21 is alternately grooved in the arrangement of the striped p-type base layers 2. 3 is formed. The difference is that the drain electrode 22 is formed so as to be connected to the p + type drain layer 21.
Since they are the same as those in (a) to (c), they are denoted by the same reference numerals. A p + type contact layer 11 is formed in the vicinity of the n + type emitter layer 6.
The emitter electrode 7 is formed so as to be connected to both of the + -type contact layers 11. Further, there are portions where the emitter electrode 7 does not exist even if the n + emitter layer 6 or the p + type contact layer 11 exists.

The operation and effect of this trench gate type IGBT are basically the same as the operation of the trench gate type IGBT according to the seventh embodiment described above. However, since the trench gate type IGBT has the p + type drain layer 21 and the drain electrode 22, Hole discharge resistance in the p-type base layer 2 is further reduced, the effect of preventing latch-up is increased, and the breakdown strength is further improved.

The present invention is not limited to the trench gate type IGBT of each of the above embodiments, but in each of the above embodiments, the n + emitter layer 6 is an n + source layer, and the p type collector layer 8 and the collector electrode 9 are n type Even when applied to a power MOSFET changed to a drain layer and a drain electrode, effects similar to those of the above embodiments can be obtained.

[0088]

As described above, according to the semiconductor device of the present invention, it is possible to secure the load short-circuit tolerance, reduce the ON voltage, and reduce the input capacitance.

[Brief description of the drawings]

FIG. 1 shows a trench gate type according to a first embodiment of the present invention.
A perspective view, a cross-sectional view, and a gate electrode
FIG. 4 is a partially cutaway perspective view illustrating a surface state of a gate insulating film when a forward bias is applied between emitter electrodes.

FIGS. 2A and 2B are a perspective view and a sectional view schematically showing a trench gate type IGBT according to a second embodiment of the present invention.

FIG. 3 is a perspective view and a sectional view schematically showing a trench gate type IGBT according to a third embodiment of the present invention.

FIG. 4 is a perspective view and a sectional view schematically showing a trench gate type IGBT according to a fourth embodiment of the present invention.

FIG. 5 is a perspective view and a sectional view schematically showing a trench gate type IGBT according to a fifth embodiment of the present invention.

FIG. 6 is a perspective view and a sectional view schematically showing a trench gate type IGBT according to a sixth embodiment of the present invention.

FIG. 7 is a perspective view and a sectional view schematically showing a trench gate type IGBT according to a seventh embodiment of the present invention.

FIG. 8 is a perspective view and a sectional view schematically showing a trench gate type IGBT according to an eighth embodiment of the present invention.

FIG. 9 is a perspective view and a sectional view schematically showing a trench gate type IGBT according to a ninth embodiment of the present invention.

FIG. 10 is a perspective view and a sectional view schematically showing a trench gate type IGBT according to a tenth embodiment of the present invention.

FIG. 11 is a perspective view and a sectional view schematically showing a trench gate type IGBT according to an eleventh embodiment of the present invention.

FIG. 12 is a perspective view and a sectional view schematically showing a trench gate type IGBT according to a twelfth embodiment of the present invention.

FIG. 13 is a perspective view and a cross-sectional view schematically showing an example of a conventional trench gate type IGBT, and a part for explaining a surface state of a gate insulating film when a forward bias is applied between a gate electrode and an emitter electrode. FIG.

14 is an operation diagram of the trench gate type IGBT of FIG. 13 and a diagram schematically showing a carrier flow.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... n-type base layer, 2 ... p-type base layer, 3 ... groove | channel, 4 ... gate insulating film, 5 ... gate electrode, 6 ... n + emitter layer, 7 ... emitter electrode, 8 ... p-type collector layer, 9 ... Collector electrode, A: junction between p-type base layer 2 and n + type emitter layer 6, B: junction between n- type base layer 1 and p-type base layer 2.

Claims (12)

[Claims] 1. A semiconductor substrate having a first conductivity type base layer, and a semiconductor substrate selectively formed so as to have a striped planar pattern in which a strip pattern is intermittently repeated on a first main surface of the semiconductor substrate. A two-conductivity-type base layer; a first-conductivity-type emitter layer selectively formed on a surface portion of the second-conductivity-type base layer; and a second-conductivity-type base layer on a first main surface of the semiconductor substrate. A groove that intersects the direction of the strip pattern and is formed to a depth reaching from the surface to the inside of the first conductivity type base layer through the first conductivity type emitter layer and the second conductivity type base layer; A gate electrode formed with an insulating layer interposed therebetween, and an emitter electrode formed to be connected to the first conductive type emitter layer and the second conductive type base layer at an intermediate portion between adjacent regions of the trench. A shape on the second main surface of the semiconductor substrate; Semiconductor device characterized by comprising a second conductivity type collector layer which is, and a collector electrode formed to be connected to the second conductivity type collector layer. 2. The method according to claim 1, wherein the first conductive type base layer and the second conductive type base layer are bonded to each other on a side wall surface of the groove.
2. The semiconductor device according to claim 1, wherein a distance between the junction between the base layer of the second conductivity type and the emitter layer of the first conductivity type is substantially constant on a side wall surface of each groove. 3. The first conductivity type in an intermediate portion between adjacent regions of the groove, as compared to a position of a junction between the first conductivity type base layer and the second conductivity type base layer on a side wall surface of the groove. 3. The semiconductor device according to claim 2, wherein the junction between the base layer and the second conductivity type base layer is deeper. 4. The semiconductor device according to claim 1, wherein the emitter electrode is a part of a unit of the second conductive type base layer and the first conductive type emitter layer in the inter-region adjacent to the trench. The semiconductor device according to claim 1, wherein the semiconductor device is formed only on the semiconductor device. 5. A semiconductor substrate having a first conductivity type base layer, and a semiconductor substrate selectively formed so as to have a striped planar pattern in which a strip pattern is intermittently repeated on a first main surface of the semiconductor substrate. A two-conductivity-type base layer; a first-conductivity-type emitter layer selectively formed on a surface portion of the second-conductivity-type base layer; and a second-conductivity-type base layer on a first main surface of the semiconductor substrate. A groove formed so as to intersect with the direction of the band-shaped pattern and penetrate from the surface through the first conductivity type emitter layer and the second conductivity type base layer to the inside of the first conductivity type base layer; A gate electrode formed with an insulating layer interposed therebetween, and a second electrode selectively formed near the first conductivity type emitter layer at an intermediate portion between adjacent regions of the trench in the second conductivity type base layer. A conductive contact layer, next to the groove An emitter electrode formed to connect to the first conductivity type emitter layer and the second conductivity type contact layer at an intermediate portion of the corresponding inter-region; and a second electrode formed on a second main surface of the semiconductor substrate. A semiconductor device comprising: a conductive type collector layer; and a collector electrode formed to be connected to the second conductive type collector layer. 6. A distance from a junction between the first conductivity type base layer and the second conductivity type base layer to a junction between the second conductivity type base layer and the first conductivity type emitter layer on a side wall surface of the groove. 6. The semiconductor device according to claim 5, wherein the width is substantially constant on a side wall surface of each groove. 7. The first conductivity type in an intermediate portion between adjacent regions of the groove, as compared to a position of a junction between the first conductivity type base layer and the second conductivity type base layer on a side wall surface of the groove. 7. The semiconductor device according to claim 6, wherein the junction between the base layer and the second conductivity type base layer is deeper. 8. The first conductive type contact layer in an inter-region adjacent to the trench and the first conductive type contact layer.
8. The semiconductor device according to claim 5, wherein the semiconductor device is formed only in a part of all units on the semiconductor chip having the conductive type emitter layer as a unit. 9. 9. The semiconductor device according to claim 5, further comprising: a portion of the first main surface of the semiconductor substrate on which the second conductivity type base layer is not formed. Selectively formed
A semiconductor device comprising: a two-conductivity-type drain layer; and a drain electrode formed to be connected to the second-conductivity-type drain layer. 10. A semiconductor substrate having a first conductivity type base layer, and a semiconductor substrate selectively formed so as to have a striped planar pattern in which a strip pattern is intermittently repeated on a first main surface of the semiconductor substrate. A two-conductivity-type base layer; a first-conductivity-type source layer selectively formed on a surface portion of the second-conductivity-type base layer; and a second-conductivity-type base layer on a first main surface of the semiconductor substrate. A groove formed so as to intersect the direction of the strip pattern and penetrate from the surface through the first conductivity type source layer and the second conductivity type base layer to reach the inside of the first conductivity type base layer; A gate electrode formed with an insulating layer interposed therebetween, and a source electrode formed so as to be connected to the first conductivity type source layer and the second conductivity type base layer at an intermediate portion between the adjacent regions of the trench. Formed on the second main surface of the semiconductor substrate And a first conductivity type drain layer, a semiconductor device characterized by comprising a drain electrode formed to connect to the first conductivity type drain layer. 11. A distance from a junction between the first conductivity type base layer and the second conductivity type base layer to a junction between the second conductivity type base layer and the first conductivity type source layer on a sidewall surface of the groove. 11. The semiconductor device according to claim 10, wherein the width is substantially constant on the side wall surface of each groove. 12. The first conductivity type in an intermediate portion between adjacent regions of the groove, as compared to a position of a junction between the first conductivity type base layer and the second conductivity type base layer on a side wall surface of the groove. 12. The semiconductor device according to claim 11, wherein a junction between the base layer and the second conductivity type base layer is deeper.