JP2008027945A - Trench-type insulated gate bipolar transistor - Google Patents

Trench-type insulated gate bipolar transistor Download PDF

Info

Publication number
JP2008027945A
JP2008027945A JP2006195194A JP2006195194A JP2008027945A JP 2008027945 A JP2008027945 A JP 2008027945A JP 2006195194 A JP2006195194 A JP 2006195194A JP 2006195194 A JP2006195194 A JP 2006195194A JP 2008027945 A JP2008027945 A JP 2008027945A
Authority
JP
Japan
Prior art keywords
trench
conductivity type
type
region
bipolar transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2006195194A
Other languages
Japanese (ja)
Other versions
JP5261893B2 (en
Inventor
Hiroki Wakimoto
博樹 脇本
Masato Otsuki
正人 大月
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Device Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Device Technology Co Ltd filed Critical Fuji Electric Device Technology Co Ltd
Priority to JP2006195194A priority Critical patent/JP5261893B2/en
Publication of JP2008027945A publication Critical patent/JP2008027945A/en
Application granted granted Critical
Publication of JP5261893B2 publication Critical patent/JP5261893B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

<P>PROBLEM TO BE SOLVED: To provide a cellular trench-type insulated gate bipolar transistor in which low on-resistance and enhancement of durability of turnoff can be achieved. <P>SOLUTION: A cell divided trench-type insulated gate bipolar transistor arranged such that a second conductivity type base region and the substrate surface appear alternately in the longitudinal direction between parallel trenches, in which a contact hole formed in an interlayer insulating film for insulating and isolating the gate electrode and the emitter electrode has a length corresponding to the longitudinal direction of the trench longer than the first conductivity type source region. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、電力変換装置などに用いられるトレンチ型絶縁ゲートバイポーラトランジスタに関する。さらに詳しくは、ストライプ状表面パターンに形成されるトレンチとその側壁面に形成されるゲート絶縁膜とこのゲート絶縁膜を介して前記トレンチ内に埋め込まれる制御電極からなるトレンチ型絶縁ゲートバイポーラトランジスタ（以降、トレンチＩＧＢＴと略すこともある）に関する。   The present invention relates to a trench type insulated gate bipolar transistor used for a power conversion device or the like. More specifically, a trench-type insulated gate bipolar transistor (hereinafter referred to as a trench-type insulated gate bipolar transistor) comprising a trench formed in a striped surface pattern, a gate insulating film formed on the side wall thereof, and a control electrode embedded in the trench through the gate insulating film. , Sometimes abbreviated as trench IGBT).

近年のパワーエレクトロニクス分野における電源機器の小型化、高性能化への要求を受けて、電力用半導体装置では、高耐圧化、大電流化と共に、低損失化、高破壊耐量化、高速化に対する性能改善に注力されている。その結果、そのような大電流化、低損失化が可能になった電力用半導体装置として、パワーＩＧＢＴなどの絶縁ゲートを備える縦型の電力用ＭＯＳ半導体装置が進展してきた。電力用ＭＯＳ半導体装置ではＭＯＳゲートを基板表面に平板状に設けたプレーナ型絶縁ゲート構造およびＭＯＳゲートをトレンチ内に埋め込み形成したトレンチ型絶縁ゲート構造の２種類が広く知られている。最近の電力用ＭＯＳ半導体装置においては、構造的に低オン抵抗特性が得やすいことから、後者のトレンチ型絶縁ゲート構造を備えるトレンチ型ＭＯＳ半導体装置が注目されている。   In response to the recent demand for miniaturization and high performance of power supply equipment in the field of power electronics, power semiconductor devices have high breakdown voltage and large current, as well as low loss, high destruction resistance, and high speed performance. Focus is on improvement. As a result, a vertical power MOS semiconductor device having an insulated gate such as a power IGBT has been developed as a power semiconductor device capable of increasing the current and reducing the loss. Two types of power MOS semiconductor devices are widely known: a planar insulated gate structure in which a MOS gate is provided in a flat plate shape on a substrate surface, and a trench insulated gate structure in which a MOS gate is embedded in a trench. In recent power MOS semiconductor devices, since a low on-resistance characteristic is easily obtained structurally, a trench type MOS semiconductor device having the latter trench type insulated gate structure has attracted attention.

このようなトレンチ型絶縁ゲート構造を有する縦型のトレンチ型ＭＯＳ半導体装置については、トレンチ内に絶縁膜を介してゲート電極が埋め込まれたトレンチ型絶縁ゲート構造を有し、そのトレンチのストライプ状表面パターン間の長手方向の基板表面にｐ型チャネル領域とｎ型半導体基板領域が交互に現れるセル分割型パターン構造を備えたトレンチゲート型ＩＧＢＴが、低オン抵抗と高耐圧を同時に実現可能なものとして既に公知になっている（特許文献１）。   A vertical trench type MOS semiconductor device having such a trench type insulated gate structure has a trench type insulated gate structure in which a gate electrode is embedded in the trench through an insulating film, and the stripe-like surface of the trench A trench gate type IGBT having a cell-divided pattern structure in which a p-type channel region and an n-type semiconductor substrate region appear alternately on the substrate surface in the longitudinal direction between patterns can realize low on-resistance and high breakdown voltage simultaneously. It is already known (Patent Document 1).

また、トレンチゲート型ＩＧＢＴにおいて、ｐ型ベース領域をトレンチゲートの長手方向に対して直角方向で島状に形成し、さらに、各トレンチ間の単位セルのチャネル長を従来のトレンチＩＧＢＴに比べて同一または短くなるように略一定に形成することにより、負荷短絡耐量を向上させる発明が公開されている（特許文献２）。
このようなトレンチＩＧＢＴのうち、特に、セル型トレンチＩＧＢＴと表記されるセル分割型トレンチゲートバイポーラトランジスタの構造の一例を図５の平面図と、この図５のＢ−Ｂ線で切断したトレンチＩＧＢＴの断面図を図６に示す。以下、このセル型トレンチＩＧＢＴの構造並びに動作について前記図面等を参照しながら説明する。 In the trench gate IGBT, the p-type base region is formed in an island shape in a direction perpendicular to the longitudinal direction of the trench gate, and the channel length of the unit cell between the trenches is the same as that of the conventional trench IGBT. Alternatively, an invention that improves the load short-circuit withstand capability by forming a substantially constant length so as to be short is disclosed (Patent Document 2).
Among such trench IGBTs, in particular, an example of the structure of a cell-divided trench gate bipolar transistor expressed as a cell-type trench IGBT is a plan view of FIG. 5 and a trench IGBT cut along the line BB in FIG. FIG. 6 shows a sectional view. Hereinafter, the structure and operation of the cell type trench IGBT will be described with reference to the drawings.

半導体基板１１１の一方の主面（以下、表面とも記すことがある）に選択的に形成されるｐ型ベース領域１１２を有し、その他方の主面（以下、裏面と記す）に、ｐ型コレクタ層１５１とコレクタ電極１５０とを有し、多数のトレンチ１１３が、ｐ型ベース領域１１２に直交する表面ストライプ状パターンを有すると共に、前記半導体基板１１１の表面からｐ型ベース領域１１２を貫通してｎ−型ドレイン層（ｎ型半導体基板領域）１１１に達する深さに形成されている。そのトレンチ１１３の内表面にはゲート酸化膜１１４が被覆され、さらにその内表面側には導電性多結晶シリコン等からなるゲート電極１１５が埋設されている。そして離間して配置される別のトレンチ１１３との間のｐベース領域１１２の表面にはその略中間にｐ＋型コンタクト領域１１７が配設されている。そしてｐ＋型コンタクト領域１１７とトレンチ１１３とにそれぞれ隣接してｎ＋型ソース領域１１６が設けられている。ゲート電極１１５上には絶縁層１１８が配設され、セル領域の全面にアルミニウム等のエミッタ電極１１９が設けられ、この絶縁層１１８がゲート電極１１５とエミッタ電極１１９とを絶縁分離している。そして、エミッタ電極１１９がｎ＋型ソース領域１１６とｐ＋型コンタクト領域１１７の双方の表面に前記絶縁膜１１８に開口されたコンタクトホール１２０でオーミック接触するように構成されている。 The semiconductor substrate 111 has a p-type base region 112 selectively formed on one main surface (hereinafter also referred to as a surface), and the other main surface (hereinafter referred to as a back surface) has a p-type. A collector layer 151 and a collector electrode 150, and a large number of trenches 113 have a surface stripe pattern orthogonal to the p-type base region 112 and penetrate the p-type base region 112 from the surface of the semiconductor substrate 111. The n − type drain layer (n type semiconductor substrate region) 111 is formed to a depth reaching the n − type drain layer (n type semiconductor substrate region) 111. A gate oxide film 114 is coated on the inner surface of the trench 113, and a gate electrode 115 made of conductive polycrystalline silicon or the like is buried on the inner surface side. A p + -type contact region 117 is disposed substantially in the middle of the surface of the p base region 112 between another trench 113 that is spaced apart. An n + type source region 116 is provided adjacent to each of the p + type contact region 117 and the trench 113. An insulating layer 118 is disposed on the gate electrode 115, and an emitter electrode 119 such as aluminum is provided on the entire surface of the cell region. The insulating layer 118 insulates and separates the gate electrode 115 and the emitter electrode 119 from each other. The emitter electrode 119 is configured to make ohmic contact with both surfaces of the n + type source region 116 and the p + type contact region 117 through the contact hole 120 opened in the insulating film 118.

このようなセル（分割）型トレンチＩＧＢＴにおいては、ゲート電極１１５に所定の閾値以上の電圧を与えることによりトレンチ１１３の側壁に沿って、ゲート絶縁膜を介してｐ型ベース領域の表面層に形成されるｎ型の反転層（図６には図示せず）が形成され、後述の図７において矢印で示すような電流路が形成される。これによりセル型トレンチＩＧＢＴのエミッタ・コレクタ間がオン状態となる。また、ゲート電極１１５の電圧を閾値以下とすることで、トレンチ１１３の側壁に沿った前記ｐ型ベース領域１１２の表面層に形成されるｎ型の反転層が消失して前記電流路が消滅し、セル型トレンチＩＧＢＴのエミッタ・コレクタ間がオフ状態となる。さらに、トレンチ１１３に沿って縦方向（基板主面に垂直な方向）並びに横方向（基板主面に平行な方向）の電流路が形成されることから、公知のプレーナ型あるいはトレンチ型の縦型ＩＧＢＴと比較して、セル型トレンチＩＧＢＴでは電流路の面積が格段に拡大される。さらに、基板表面側のトレンチ１１３間においてｎ型半導体基板層１１１の露出している表面領域に少数キャリアの蓄積が生じ、そのオン抵抗を小さくすることができるという利点も生じる。
特開２０００−２２８５１９号公報 特開２００１−２７４４００号公報 In such a cell (divided) trench IGBT, a voltage equal to or higher than a predetermined threshold is applied to the gate electrode 115 to form the surface layer of the p-type base region along the sidewall of the trench 113 via the gate insulating film. An n-type inversion layer (not shown in FIG. 6) is formed, and a current path as shown by an arrow in FIG. 7 described later is formed. As a result, the emitter-collector of the cell type trench IGBT is turned on. Further, by setting the voltage of the gate electrode 115 to a threshold value or less, the n-type inversion layer formed on the surface layer of the p-type base region 112 along the sidewall of the trench 113 disappears, and the current path disappears. The emitter-collector of the cell type trench IGBT is turned off. Furthermore, since current paths in the vertical direction (direction perpendicular to the main surface of the substrate) and in the horizontal direction (direction parallel to the main surface of the substrate) are formed along the trench 113, a known planar type or trench type vertical type is formed. Compared with the IGBT, the area of the current path is greatly expanded in the cell type trench IGBT. Furthermore, minority carrier accumulation occurs in the exposed surface region of the n-type semiconductor substrate layer 111 between the trenches 113 on the substrate surface side, and the on-resistance can be reduced.
JP 2000-228519 A JP 2001-274400 A

一般的に、ＩＧＢＴのターンオフ過程では、オン状態でｐ型コレクタ層１５１からｎ型ベース層１１１へ注入された少数キャリア（正孔）はエミッタ電極１１９へ排出される。その際、特に、前述のセル型トレンチＩＧＢＴでは、トレンチ１１３側壁面とｎ型ベース層１１１の境界部分に形成される蓄積層を通じて、図７の従来のセル分割型トレンチＩＧＢＴのセル部平面図に鎖線の丸枠内に矢印で示すように、ｐ型ベース層１１１の角部分に少数キャリア電流（ここでは、ホール電流）が集中して流れ、狭いコンタクトホール１２０に向かっていく。その結果、このホール電流のうち、ｎ＋型ソース領域１１６の下部を通る電流も増加することになる。このｎ＋型ソース（またはエミッタ）領域１１６の下部を流れるホール電流は、ｎ＋型ソース（エミッタと同じ）領域１１６／ｐ型ベース領域１１２／ｎ型半導体基板層（ｎ型ベース層）１１１からなるｎｐｎトランジスタのベース電流に相当しており、ホール電流の集中による電流増加は、このｎｐｎトランジスタの動作を容易なものとし、結果として、ｎ＋型ソース（またはエミッタ）領域１１６／ｐ型ベース領域１１２／ｎ型半導体基板層１１１／ｐ型コレクタ層１５１からなるＩＧＢＴの寄生サイリスタをラッチアップさせ、このＩＧＢＴをターンオフ制御不能にするため、ターンオフ耐量が低下する。言い換えるとターンオフ時の遮断可能電流が低下し、破壊に至る場合がある。 In general, in the IGBT turn-off process, minority carriers (holes) injected from the p-type collector layer 151 to the n-type base layer 111 in the ON state are discharged to the emitter electrode 119. At that time, in particular, in the above-described cell-type trench IGBT, the cell portion plan view of the conventional cell-divided trench IGBT of FIG. 7 is passed through an accumulation layer formed at the boundary between the sidewall of the trench 113 and the n-type base layer 111. Minority carrier current (hole current here) concentrates on the corners of the p-type base layer 111 and flows toward the narrow contact hole 120 as indicated by an arrow in a chain line circle. As a result, the current passing through the lower part of the n + type source region 116 in the hole current also increases. The hole current flowing under the n + -type source (or emitter) region 116 is from the n + -type source (same as the emitter) region 116 / p-type base region 112 / n-type semiconductor substrate layer (n-type base layer) 111. The increase in the current due to the concentration of the hole current facilitates the operation of the npn transistor. As a result, the n + type source (or emitter) region 116 / p type base region Since the IGBT parasitic thyristor composed of the 112 / n-type semiconductor substrate layer 111 / p-type collector layer 151 is latched up and the IGBT cannot be turned off, the turn-off resistance is reduced. In other words, the current that can be cut off at the time of turn-off is reduced, which may lead to destruction.

本発明は、以上述べた点に鑑みてなされたものであり、本発明の目的は、低オン抵抗化、ターンオフ耐量の向上が達成できるセル型のトレンチ型絶縁ゲートバイポーラトランジスタを提供することである。   The present invention has been made in view of the above points, and an object of the present invention is to provide a cell-type trench insulated gate bipolar transistor that can achieve low on-resistance and improved turn-off resistance. .

特許請求の範囲の請求項１記載の発明によれば、第一導電型半導体基板と、該半導体基板の一方の主表面層に選択的に形成される第二導電型のベース領域と、この第二導電型ベース領域の表面層に選択的に形成される第一導電型ソース領域と、前記半導体基板表面から第二導電型のベース領域を超える深さを有し、並列ストライプ状表面パターンに形成されるトレンチと、該トレンチの側壁に形成されるゲート絶縁膜を介してトレンチ内に埋設されるポリシリコンゲート電極と、このポリシリコンゲート電極上に層間絶縁膜を介して形成されるエミッタ電極と、このエミッタ電極が前記第一導電型ソース領域と前記第二導電型ベース領域の双方の表面に接触するように前記層間絶縁膜に設けられるコンタクトホールと、前記第一導電型半導体基板の他方の主表面層に形成される第二導電型コレクタ層と、該第二導電型コレクタ層表面に接触するコレクタ電極とを備え、前記第一導電型半導体基板の一方の主表面では、前記並列トレンチ間の長手方向に第二導電型ベース領域と第一導電型半導体基板の各表面が交互に現われるように配設されるトレンチ型絶縁ゲートバイポーラトランジスタにおいて、前記コンタクトホールが、このコンタクトホールの前記トレンチの長手方向に相当する長さについて、前記第一導電型ソース領域よりも長くされているトレンチ型絶縁ゲートバイポーラトランジスタとすることにより、前記本発明の目的は達成される。   According to the first aspect of the present invention, the first conductivity type semiconductor substrate, the second conductivity type base region selectively formed on one main surface layer of the semiconductor substrate, and the first conductivity type semiconductor substrate. A first conductive type source region selectively formed on the surface layer of the two conductive type base region, and a depth exceeding the second conductive type base region from the surface of the semiconductor substrate, and formed in a parallel striped surface pattern A trench, a polysilicon gate electrode embedded in the trench through a gate insulating film formed on the sidewall of the trench, and an emitter electrode formed on the polysilicon gate electrode through an interlayer insulating film A contact hole provided in the interlayer insulating film so that the emitter electrode contacts the surfaces of both the first conductivity type source region and the second conductivity type base region; and the first conductivity type semiconductor A second conductivity type collector layer formed on the other main surface layer of the plate, and a collector electrode in contact with the second conductivity type collector layer surface, on one main surface of the first conductivity type semiconductor substrate, In the trench-type insulated gate bipolar transistor arranged such that the surfaces of the second conductivity type base region and the first conductivity type semiconductor substrate alternately appear in the longitudinal direction between the parallel trenches, the contact hole is the contact hole. The object of the present invention is achieved by providing a trench type insulated gate bipolar transistor having a length corresponding to the longitudinal direction of the trench longer than the first conductivity type source region.

特許請求の範囲の請求項２記載の発明によれば、前記コンタクトホールが前記トレンチの長手方向に相当する一方向側の長さについて、前記第一導電型ソース領域よりも０．５μｍ乃至４．０μｍの範囲で、長くされている特許請求の範囲の請求項１に記載のトレンチ型絶縁ゲートバイポーラトランジスタとすることが好ましい。
特許請求の範囲の請求項３記載の発明によれば、前記第二導電型ベース領域内に、該ベース領域よりも高濃度の第二導電型コンタクト領域が形成されている特許請求の範囲の請求項１または２記載のトレンチ型絶縁ゲートバイポーラトランジスタとすることが望ましい。 According to a second aspect of the present invention, the length of the contact hole in one direction corresponding to the longitudinal direction of the trench is 0.5 μm to 4.4 μm from the first conductivity type source region. Preferably, the trench-type insulated gate bipolar transistor according to claim 1 is elongated in a range of 0 μm.
According to the invention of claim 3, the second conductivity type contact region having a higher concentration than the base region is formed in the second conductivity type base region. The trench-type insulated gate bipolar transistor according to Item 1 or 2 is desirable.

特許請求の範囲の請求項４記載の発明によれば、前記第二導電型コンタクト領域が前記トレンチの長手方向に相当する一方向側の長さについて、前記第一導電型ソース領域よりも０．５μｍ乃至４．０μｍの範囲で、長くされている特許請求の範囲の請求項３に記載のトレンチ型絶縁ゲートバイポーラトランジスタとすることがより望ましい。
要するに、本発明は、トレンチゲートの長手方向に関して、ｎ＋型ソース領域の端から、コンタクトホールをはみ出させた構造とする。このようなパターンにすることにより、ターンオフ時のホール電流集中が緩和され、遮断可能電流が増大するのである。 According to the invention of claim 4, the length of the second conductivity type contact region in one direction corresponding to the longitudinal direction of the trench is less than the first conductivity type source region. More preferably, the trench type insulated gate bipolar transistor according to claim 3 is elongated in the range of 5 μm to 4.0 μm.
In short, the present invention has a structure in which the contact hole protrudes from the end of the n + type source region in the longitudinal direction of the trench gate. By adopting such a pattern, the hole current concentration at the time of turn-off is alleviated, and the interruptable current increases.

本発明を適用すれば、低オン抵抗化、ターンオフ耐量の向上が達成できるセル分割型のトレンチＩＧＢＴを提供することができる。   By applying the present invention, it is possible to provide a cell-divided trench IGBT that can achieve low on-resistance and improved turn-off resistance.

図１−１は本発明にかかるセル分割型トレンチＩＧＢＴのセルユニット部の平面図である。図１−２は、図１−１のＡ−Ａ線で切断したセル分割型トレンチＩＧＢＴの断面図である。図２は本発明にかかるセル分割型トレンチＩＧＢＴの距離Ｘをパラメーターとした場合の遮断可能電流とオン電圧との関係図である。図３は本発明にかかる、異なるセル分割型トレンチＩＧＢＴのセルユニット部の平面図である。図４は本発明にかかる、ｎ＋型ソース領域のトレンチ長手方向に関する長さとコンタクトホール及びｐ＋型コンタクト領域の長さの関係をパラメーターとした場合の、遮断可能電流とオン電圧との関係図である。 FIG. 1-1 is a plan view of a cell unit portion of a cell division type trench IGBT according to the present invention. FIG. 1-2 is a cross-sectional view of the cell division type trench IGBT cut along line AA in FIG. 1-1. FIG. 2 is a graph showing the relationship between the cutoff current and the on-voltage when the distance X of the cell division type trench IGBT according to the present invention is used as a parameter. FIG. 3 is a plan view of a cell unit portion of a different cell division type trench IGBT according to the present invention. FIG. 4 is a diagram showing the relationship between the breakable current and the on-voltage when the length of the n + -type source region in the trench longitudinal direction and the length of the contact hole and the p + -type contact region are used as parameters. It is.

以下、本発明にかかるセル分割型のトレンチ型絶縁ゲートバイポーラトランジスタについて、図面を用いて詳細に説明する。本発明はその要旨を超えない限り、以下に説明する実施例の記載に限定されるものではない。
図１−１に本発明の実施例１にかかる一セル分の平面図、図１−２に、図１−１のＡ−Ａ線で切断したセル分割型トレンチＩＧＢＴの断面図を示す。前記従来のセル分割型トレンチＩＧＢＴを示す前記図５、図６、図７と比較して、トレンチ長手方向の長さに関し、実施例１ではコンタクトホール１０がｎ＋型ソース領域６より長いパターンとなっているところが異なるだけであり、その他の構成は前記図７および図５、図６により示される従来のセル分割型トレンチＩＧＢＴと同様であるので、詳細な説明を省略する。なお、図７でも、ｐ＋型コンタクト領域１１７の長さがｎ＋型ソース領域１１６より長くされているように図面上では見えるが、不純物拡散の拡がりによるものであり、意図的に長くしたものではないし、長さ的にもわずかである。 Hereinafter, a cell division type trench insulated gate bipolar transistor according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
1-1 is a plan view for one cell according to Example 1 of the present invention, and FIG. 1-2 is a cross-sectional view of the cell-divided trench IGBT cut along the line AA in FIG. 1-1. Compared to FIGS. 5, 6, and 7 showing the conventional cell-divided trench IGBT, in the first embodiment, the contact hole 10 has a longer pattern than the n + -type source region 6 with respect to the length in the trench longitudinal direction. However, since the other configurations are the same as those of the conventional cell-divided trench IGBT shown in FIGS. 7, 5, and 6, detailed description thereof is omitted. In FIG. 7 as well, the p + type contact region 117 is longer than the n + type source region 116 in the drawing, but it is due to the diffusion of impurity diffusion and is intentionally increased. It is not a little in length.

図１−１、図１−２では、コンタクトホール１０がｎ＋型ソース領域６より「距離Ｘ」の長さだけ長くされることにより、図１−１で矢印で示すホール電流が流れることができる実効断面積が鎖線で示す丸い枠内のように図７よりも広がるので、過度な電流集中が起き難くなる。この効果により、ターンオフ時の遮断可能電流を大幅に増大させることが可能となる。ただし、前述のように「距離Ｘ」を長くし過ぎると、オン状態での少数キャリアの排出も多くなるため、伝導度変調効果が小さくなり、オン状態での電圧降下（Ｖｃｅ（ｓａｔ））が上昇、すなわち、オン電圧が大きくなるので、距離Ｘにはおのずと上限がある。 1-1 and 1-2, the contact hole 10 is made longer than the n + -type source region 6 by the length of “distance X”, so that the hole current indicated by the arrow in FIG. Since the effective cross-sectional area that can be generated is larger than that in FIG. 7 as in a round frame indicated by a chain line, excessive current concentration is less likely to occur. Due to this effect, the current that can be cut off at the time of turn-off can be greatly increased. However, if the “distance X” is too long as described above, minority carriers are discharged more in the on state, so that the conductivity modulation effect is reduced and the voltage drop in the on state (Vce (sat)) is reduced. Since the rise, that is, the ON voltage increases, the distance X naturally has an upper limit.

実施例１にかかるセル分割型トレンチＩＧＢＴについて、距離Ｘをパラメーターとした場合の、オン電圧（Ｖｃｅ（ｓａｔ））とターンオフ耐量の関係図を図２に示す。図２から、距離ＸがＸ＝０からＸ＝４．０μｍへと大きくなるにつれて、オン電圧（Ｖｃｅ（ｓａｔ））と遮断可能電流共に増大することが分かる。また、遮断可能電流には一般的に規格が設けられており、図２ではその遮断可能電流規格を点線で示す。図２によれば、「距離Ｘ」が０．５μｍ以上で点線で示す遮断可能電流規格を満たすことを示している。遮断可能電流の規格は、定格電流値の３〜５倍程度であることが多い。さらに距離Ｘを大きくしていくと、オン電圧（Ｖｃｅ（ｓａｔ））が次第に増大するが、４μｍ以上では、急激にオン電圧値が大きくなると同時に、遮断可能電流の上昇が飽和することが分かる。このことから、前述のようにオン電圧を考慮すると、距離Ｘの上限は４．０μｍ程度が好ましいので、実施例１にかかる距離Ｘの好ましい範囲は０．５μｍ以上４μｍ以下とすることができる。ただし、前記距離Ｘが４μｍ以下の場合でも、コンタクトホール１０の前記長さをｐ型ベース領域２の長さを超えてｎ型ベース領域１の表面露出領域まで到達する長さにしてはならない。その理由は、そのようにすると、セル分割型トレンチＩＧＢＴのコレクタ／エミッタ間の順方向耐圧がでなくなるからである。   FIG. 2 shows a relationship diagram between the on-voltage (Vce (sat)) and the turn-off resistance when the distance X is used as a parameter for the cell division type trench IGBT according to the first example. From FIG. 2, it can be seen that as the distance X increases from X = 0 to X = 4.0 μm, both the ON voltage (Vce (sat)) and the cutoff current increase. In addition, a standard is generally provided for the breakable current, and in FIG. 2, the breakable current standard is indicated by a dotted line. FIG. 2 shows that “distance X” is 0.5 μm or more and satisfies the interruptable current standard indicated by the dotted line. The standard of breakable current is often about 3 to 5 times the rated current value. As the distance X is further increased, the on-voltage (Vce (sat)) gradually increases. However, when the distance X is 4 μm or more, the on-voltage value increases rapidly and at the same time, the increase in the breakable current is saturated. Therefore, considering the on-state voltage as described above, the upper limit of the distance X is preferably about 4.0 μm, and therefore the preferable range of the distance X according to Example 1 can be set to 0.5 μm or more and 4 μm or less. However, even when the distance X is 4 μm or less, the length of the contact hole 10 should not exceed the length of the p-type base region 2 and reach the surface exposed region of the n-type base region 1. The reason is that the forward breakdown voltage between the collector and the emitter of the cell-divided trench IGBT is not obtained.

図３に実施例２にかかるセル分割型トレンチＩＧＢＴの一セル分の平面図を示す。前述の実施例１にかかる図１−１とは、コンタクトホール１３だけでなく、ｐ＋型コンタクト領域１４もトレンチ長手方向に大きく伸びている点が異なる。図４として、ｎ＋型ソース領域のトレンチ長手方向に関する長さとコンタクトホール及びｐ＋型コンタクト領域の長さの関係をパラメーターとした場合の、オン電圧と遮断可能電流との関係図中の破線に示すように、ｐ＋型コンタクト領域１４とコンタクトホール１３の双方を伸ばすと、それぞれの効果を合わせた効果が得られる結果、効果としての遮断可能電流は実施例１の場合よりさらに大きくすることができる。ｐ＋型コンタクト領域１４の突き出し距離「Ｙ」は、必ずしもコンタクトホール１３の突き出し距離「Ｘ」と一致させる必要はなく、遮断可能電流規格との兼ね合いで最適値を選ぶことができる。前述した従来のセル部の平面図である図７中に示すように、ｐ＋型コンタクト領域１１７のみがｐ型ベース領域に突き出した構造の場合でも遮断可能電流の増大がえられるものの、ごくわずかである。図４からは、ｐ＋型コンタクト領域の突き出し効果は、コンタクトホールのみを突き出させた場合よりも遮断可能電流向上効果は小さく、遮断可能電流を増大させる効果はコンタクトホールを長くする場合の方が大きい効果が得られることもわかる。 FIG. 3 is a plan view of one cell of the cell division type trench IGBT according to the second embodiment. This embodiment differs from FIG. 1-1 according to the first embodiment in that not only the contact hole 13 but also the p + -type contact region 14 extends greatly in the longitudinal direction of the trench. As shown in FIG. 4, the broken line in the relationship diagram between the on-state voltage and the cut-off current when the relationship between the length of the n + type source region in the longitudinal direction of the trench and the length of the contact hole and the p + type contact region is used as a parameter. As shown, when both the p + -type contact region 14 and the contact hole 13 are extended, an effect obtained by combining the effects can be obtained. As a result, the current that can be cut off can be made larger than that in the first embodiment. it can. The protrusion distance “Y” of the p + -type contact region 14 does not necessarily need to coincide with the protrusion distance “X” of the contact hole 13, and an optimum value can be selected in consideration of the cutoff current standard. As shown in FIG. 7 which is a plan view of the conventional cell portion described above, an increase in the cut-off current can be obtained even in the case where only the p + -type contact region 117 protrudes into the p-type base region. It is. FIG. 4 shows that the p + -type contact region has a protruding effect smaller than the case where only the contact hole is protruded, and the effect of increasing the breakable current is greater when the contact hole is made longer. It can also be seen that a great effect can be obtained.

本発明にかかるセル分割型トレンチＩＧＢＴのセルユニット部の平面図である。It is a top view of the cell unit part of the cell division type trench IGBT concerning this invention. 図１−１のＡ−Ａ線で切断したセル分割型トレンチＩＧＢＴの断面図である。It is sectional drawing of the cell division | segmentation type | mold trench IGBT cut | disconnected by the AA line of FIGS. 1-1. 本発明にかかるセル分割型トレンチＩＧＢＴの距離Ｘをパラメーターとした場合の遮断可能電流とオン電圧との関係図である。FIG. 6 is a relationship diagram between a cutoff possible current and an on-voltage when the distance X of the cell division type trench IGBT according to the present invention is used as a parameter. 本発明にかかる、異なるセル分割型トレンチＩＧＢＴのセルユニット部の平面図である。It is a top view of the cell unit part of different cell division type trench IGBT concerning this invention. 本発明にかかる、ｎ＋型ソース領域のトレンチ長手方向に関する長さとコンタクトホール及びｐ＋型コンタクト領域の長さの関係をパラメーターとした場合の、遮断可能電流とオン電圧との関係図である。FIG. 6 is a relationship diagram between a breakable current and an on-voltage when the relationship between the length of the n + -type source region in the trench longitudinal direction and the length of the contact hole and the p + -type contact region is used as a parameter according to the present invention. 従来のセル分割型トレンチゲートバイポーラトランジスタの平面図である。It is a top view of the conventional cell division type trench gate bipolar transistor. 図５のＢ−Ｂ線で切断したセル分割型トレンチＩＧＢＴの断面図である。It is sectional drawing of the cell division type trench IGBT cut | disconnected by the BB line of FIG. 従来のセル分割型トレンチＩＧＢＴのセルユニット部の平面図である。It is a top view of the cell unit part of the conventional cell division type trench IGBT.

符号の説明Explanation of symbols

１、… 第一導電型半導体基板、シリコン基板、ｎ型ベース層、
２、… 第二導電型のベース領域、ｐ型ベース領域、
３、… トレンチ、
４、… ゲート絶縁膜、ゲート酸化膜、
５、… ポリシリコンゲート電極、
６、… 第一導電型ソース領域、ｎ＋型ソース領域、
７、… 第二導電型コンタクト領域、ｐ＋型コンタクト領域、
８、… 層間絶縁膜、
９、… エミッタ電極、
１０、… コンタクトホール、
１１、… 第二導電型コレクタ層
１２、… コレクタ電極
１３、… コンタクトホール
１４、… 第二導電型コンタクト領域、ｐ＋型コンタクト領域。 1,... First conductivity type semiconductor substrate, silicon substrate, n-type base layer,
2, ... second conductivity type base region, p-type base region,
3, ... trench,
4, ... Gate insulating film, gate oxide film,
5, ... polysilicon gate electrode,
6,... First conductivity type source region, n + type source region,
7, second conductivity type contact region, p + type contact region,
8, ... interlayer insulation film,
9, Emitter electrode,
10. Contact hole,
DESCRIPTION OF SYMBOLS 11, ... 2nd conductivity type collector layer 12, ... Collector electrode 13, ... Contact hole 14, ... 2nd conductivity type contact region, p + type contact region.

Claims (4)

第一導電型半導体基板と、該半導体基板の一方の主表面層に選択的に形成される第二導電型のベース領域と、この第二導電型ベース領域の表面層に選択的に形成される第一導電型ソース領域と、前記半導体基板表面から第二導電型のベース領域を超える深さを有し、並列ストライプ状表面パターンに形成されるトレンチと、該トレンチの側壁に形成されるゲート絶縁膜を介してトレンチ内に埋設されるポリシリコンゲート電極と、このポリシリコンゲート電極上に層間絶縁膜を介して形成されるエミッタ電極と、このエミッタ電極が前記第一導電型ソース領域と前記第二導電型ベース領域の双方の表面に接触するように前記層間絶縁膜に設けられるコンタクトホールと、前記第一導電型半導体基板の他方の主表面層に形成される第二導電型コレクタ層と、該第二導電型コレクタ層表面に接触するコレクタ電極とを備え、前記第一導電型半導体基板の一方の主表面では、前記並列トレンチ間の長手方向に第二導電型ベース領域と第一導電型半導体基板の各表面が交互に現われるように配設されるトレンチ型絶縁ゲートバイポーラトランジスタにおいて、前記コンタクトホールが、このコンタクトホールの前記トレンチの長手方向に相当する長さについて、前記第一導電型ソース領域よりも長くされていることを特徴とするトレンチ型絶縁ゲートバイポーラトランジスタ。 A first conductivity type semiconductor substrate, a second conductivity type base region selectively formed on one main surface layer of the semiconductor substrate, and a surface layer of the second conductivity type base region selectively formed A first conductivity type source region; a trench having a depth exceeding a base region of the second conductivity type from the surface of the semiconductor substrate; and a gate insulation formed on a sidewall of the trench; A polysilicon gate electrode embedded in the trench through the film; an emitter electrode formed on the polysilicon gate electrode through an interlayer insulating film; and the emitter electrode comprising the first conductivity type source region and the first electrode A contact hole provided in the interlayer insulating film so as to be in contact with both surfaces of the two-conductivity type base region, and a second conductivity-type core formed in the other main surface layer of the first conductivity-type semiconductor substrate. And a collector electrode in contact with the surface of the second conductivity type collector layer, and on one main surface of the first conductivity type semiconductor substrate, a second conductivity type base region is provided in the longitudinal direction between the parallel trenches. In the trench type insulated gate bipolar transistor arranged so that the surfaces of the first conductivity type semiconductor substrate appear alternately, the contact hole has a length corresponding to the longitudinal direction of the trench. A trench type insulated gate bipolar transistor characterized by being longer than one conductivity type source region. 前記コンタクトホールが前記トレンチの長手方向に相当する一方向側の長さについて、前記第一導電型ソース領域よりも０．５μｍ乃至４．０μｍの範囲で、長くされていることを特徴とする請求項１に記載のトレンチ型絶縁ゲートバイポーラトランジスタ。 The contact hole has a length in one direction corresponding to a longitudinal direction of the trench, which is longer than the first conductivity type source region in a range of 0.5 μm to 4.0 μm. Item 2. The trench type insulated gate bipolar transistor according to Item 1. 前記第二導電型ベース領域内の前記第一導電型ソース領域に挟まれた表面層に、該ベース領域よりも高濃度の第二導電型コンタクト領域が形成されていることを特徴とする請求項１または２記載のトレンチ型絶縁ゲートバイポーラトランジスタ。 The second conductivity type contact region having a concentration higher than that of the base region is formed in a surface layer sandwiched between the first conductivity type source regions in the second conductivity type base region. 3. A trench type insulated gate bipolar transistor according to 1 or 2. 前記第二導電型コンタクト領域が前記トレンチの長手方向に相当する一方向側の長さについて、前記第一導電型ソース領域よりも０．５μｍ乃至４．０μｍの範囲で、長くされていることを特徴とする請求項３に記載のトレンチ型絶縁ゲートバイポーラトランジスタ。 The second conductivity type contact region has a length in one direction corresponding to the longitudinal direction of the trench that is longer than the first conductivity type source region by 0.5 μm to 4.0 μm. 4. The trench type insulated gate bipolar transistor according to claim 3, wherein:
JP2006195194A 2006-07-18 2006-07-18 Trench type insulated gate bipolar transistor Active JP5261893B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006195194A JP5261893B2 (en) 2006-07-18 2006-07-18 Trench type insulated gate bipolar transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006195194A JP5261893B2 (en) 2006-07-18 2006-07-18 Trench type insulated gate bipolar transistor

Publications (2)

Publication Number Publication Date
JP2008027945A true JP2008027945A (en) 2008-02-07
JP5261893B2 JP5261893B2 (en) 2013-08-14

Family

ID=39118309

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006195194A Active JP5261893B2 (en) 2006-07-18 2006-07-18 Trench type insulated gate bipolar transistor

Country Status (1)

Country Link
JP (1) JP5261893B2 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009036390A1 (en) 2008-08-08 2010-04-15 Sumitomo Chemical Company, Limited Hydrogenation catalyst and process for producing an olefin polymer
DE102009036391A1 (en) 2008-08-08 2010-04-22 Sumitomo Chemical Company, Limited Process for producing an olefin polymer (1)
DE102009036410A1 (en) 2008-08-08 2010-11-18 Sumitomo Chemical Company, Limited Process for producing an olefin polymer (2)
DE112011100533T5 (en) 2010-11-30 2012-12-20 Fuji Electric Co., Ltd. Semiconductor device
US9318590B2 (en) 2013-04-02 2016-04-19 Toyota Jidosha Kabushiki Kaisha IGBT using trench gate electrode
WO2021086871A1 (en) * 2019-10-28 2021-05-06 Psiquantum, Corp. Electronic components employing field ionization

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000228519A (en) * 1999-02-05 2000-08-15 Fuji Electric Co Ltd Trench insulated gate bipolar transistor
JP2001085689A (en) * 1999-09-17 2001-03-30 Toyota Motor Corp Power semiconductor device
JP2001274400A (en) * 2000-03-28 2001-10-05 Toshiba Corp Semiconductor device
JP2002190595A (en) * 2000-12-21 2002-07-05 Denso Corp Semiconductor device and method of manufacturing the same
JP2004153112A (en) * 2002-10-31 2004-05-27 Toshiba Corp Power semiconductor device
JP2004158507A (en) * 2002-11-01 2004-06-03 Toyota Motor Corp Field-effect semiconductor device
JP2007221012A (en) * 2006-02-20 2007-08-30 Fuji Electric Device Technology Co Ltd Mos device and manufacturing method thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000228519A (en) * 1999-02-05 2000-08-15 Fuji Electric Co Ltd Trench insulated gate bipolar transistor
JP2001085689A (en) * 1999-09-17 2001-03-30 Toyota Motor Corp Power semiconductor device
JP2001274400A (en) * 2000-03-28 2001-10-05 Toshiba Corp Semiconductor device
JP2002190595A (en) * 2000-12-21 2002-07-05 Denso Corp Semiconductor device and method of manufacturing the same
JP2004153112A (en) * 2002-10-31 2004-05-27 Toshiba Corp Power semiconductor device
JP2004158507A (en) * 2002-11-01 2004-06-03 Toyota Motor Corp Field-effect semiconductor device
JP2007221012A (en) * 2006-02-20 2007-08-30 Fuji Electric Device Technology Co Ltd Mos device and manufacturing method thereof

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009036390A1 (en) 2008-08-08 2010-04-15 Sumitomo Chemical Company, Limited Hydrogenation catalyst and process for producing an olefin polymer
DE102009036391A1 (en) 2008-08-08 2010-04-22 Sumitomo Chemical Company, Limited Process for producing an olefin polymer (1)
DE102009036410A1 (en) 2008-08-08 2010-11-18 Sumitomo Chemical Company, Limited Process for producing an olefin polymer (2)
DE102009036390B4 (en) 2008-08-08 2021-11-18 Sumitomo Chemical Company, Limited Process for producing an olefin polymer
DE112011100533T5 (en) 2010-11-30 2012-12-20 Fuji Electric Co., Ltd. Semiconductor device
US8809911B2 (en) 2010-11-30 2014-08-19 Fuji Electric Co., Ltd. Semiconductor device
US9318590B2 (en) 2013-04-02 2016-04-19 Toyota Jidosha Kabushiki Kaisha IGBT using trench gate electrode
WO2021086871A1 (en) * 2019-10-28 2021-05-06 Psiquantum, Corp. Electronic components employing field ionization

Also Published As

Publication number Publication date
JP5261893B2 (en) 2013-08-14

Similar Documents

Publication Publication Date Title
CN109964317B (en) Semiconductor device with a plurality of semiconductor chips
JP5107460B2 (en) Integrated low leakage Schottky diode
US11217580B2 (en) Semiconductor device including insulated gate bipolar transistor element and freewheeling diode element
JP5098303B2 (en) Insulated gate bipolar transistor
JP5865618B2 (en) Semiconductor device
JP5480084B2 (en) Semiconductor device
US10608104B2 (en) Trench transistor device
JP6652515B2 (en) Semiconductor device
JPH11345969A (en) Power semiconductor device
JP5537359B2 (en) Semiconductor device
JP6183550B2 (en) Semiconductor device
JP2008186921A (en) Semiconductor device
US20150187877A1 (en) Power semiconductor device
JP2012507842A (en) Reverse conductive semiconductor device
JP2008021918A (en) Semiconductor device
US10490655B2 (en) Insulated gate bipolar transistor (IGBT) with high avalanche withstand
JP2008047772A (en) Insulated gate bipolar transistor
JP5261893B2 (en) Trench type insulated gate bipolar transistor
JP2009188290A (en) Power semiconductor device
JP2021052078A (en) Semiconductor device and manufacturing method thereof
JP2014154739A (en) Semiconductor device
CN111326510B (en) Semiconductor device with a semiconductor device having a plurality of semiconductor chips
KR20150069117A (en) Power semiconductor device
KR101994728B1 (en) Power semiconductor device
JP2013069871A (en) Semiconductor device

Legal Events

Date Code Title Description
RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20081216

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20090219

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090515

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20091112

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20110422

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20120719

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20120724

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121016

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121214

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130116

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130314

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130402

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130415

R150 Certificate of patent or registration of utility model

Ref document number: 5261893

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250