JPH0560667B2 - - Google Patents
Info
- Publication number
- JPH0560667B2 JPH0560667B2 JP4152487A JP4152487A JPH0560667B2 JP H0560667 B2 JPH0560667 B2 JP H0560667B2 JP 4152487 A JP4152487 A JP 4152487A JP 4152487 A JP4152487 A JP 4152487A JP H0560667 B2 JPH0560667 B2 JP H0560667B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- emitter layer
- emitter
- concentration impurity
- high concentration
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000012535 impurity Substances 0.000 claims description 33
- 239000004065 semiconductor Substances 0.000 claims description 21
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 239000000758 substrate Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 9
- 238000009792 diffusion process Methods 0.000 description 16
- 239000008188 pellet Substances 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、ゲートターンオフサイリスタ（以下
GTOサイリスタという）の製造方法に係り、特
に、製造工程数を少なくしたGTOサイリスタの
製造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a gate turn-off thyristor (hereinafter referred to as
The present invention relates to a method of manufacturing a GTO thyristor (referred to as a GTO thyristor), and particularly relates to a method of manufacturing a GTO thyristor with a reduced number of manufacturing steps.
GTOサイリスタの構造に関する従来技術とし
て例えば、特開昭55−39619号公報、特開昭57−
201078号公報等に記載された技術が知られてい
る。これらの従来技術によるGTOサイリスタは、
ゲート端子が低抵抗接触されていないベース層内
の同じ導電型の半導体による高濃度不純物層を隣
接するエミツタ層より厚く形成することにより、
このベース層をアノード端子に低抵抗接触させる
ようにしたものであり、また、ゲート端子を一方
のベース層に低抵抗接触させるために、このベー
ス層に同じ導電型の半導体による高濃度不純物層
を形成したものである。
Examples of prior art related to the structure of GTO thyristors include Japanese Patent Laid-Open No. 55-39619 and Japanese Patent Laid-open No. 57-39619.
A technique described in 201078 publication etc. is known. These conventional GTO thyristors are
By forming a highly concentrated impurity layer made of a semiconductor of the same conductivity type in the base layer, which is not connected to the gate terminal with low resistance, to be thicker than the adjacent emitter layer,
This base layer is brought into low resistance contact with the anode terminal, and in order to bring the gate terminal into low resistance contact with one of the base layers, this base layer is coated with a highly concentrated impurity layer made of a semiconductor of the same conductivity type. It was formed.
以下、このような従来技術によるGTOサイリ
スタの構造と製造方法を図面により説明する。 The structure and manufacturing method of such a GTO thyristor according to the prior art will be explained below with reference to the drawings.
第２図ａ〜ｄは従来技術による製造方法を説明
する単位GTOサイリスタの断面図、第３図、第
４図は従来技術及び本発明によるGTOサイリス
タの平面図及び単位GTOサイリスタの断面図で
ある。第２図〜第４図において、１はペレツト、
２は単位GTOサイリスタ、３はｎ型高濃度不純
物層、３１はｎ型半導体基板、４はｐベース層、
５はｐエミツタ層、６はｎエミツタ層、７はｐ型
高濃度不純物層、８はカソード電極、９はアノー
ド電極、１０はゲート電極である。 Figures 2 a to d are cross-sectional views of unit GTO thyristors for explaining the manufacturing method according to the prior art, and Figures 3 and 4 are plan views and cross-sectional views of unit GTO thyristors according to the prior art and the present invention. . In Figures 2 to 4, 1 is a pellet;
2 is a unit GTO thyristor, 3 is an n-type high concentration impurity layer, 31 is an n-type semiconductor substrate, 4 is a p base layer,
5 is a p emitter layer, 6 is an n emitter layer, 7 is a p-type high concentration impurity layer, 8 is a cathode electrode, 9 is an anode electrode, and 10 is a gate electrode.
短絡エミツタ構造のGTOサイリスタは、第３
図に示すように、ペレツト１内に多数の単位
GTOサイリスタ２が配列されて構成されている。
各GTOサイリスタ２は、第４図に示すような断
面構造を有している。この断面は、第３図におけ
る−断面である。単位GTOサイリスタ２は、
ｎエミツタ層６、ｐベース層４、ｎベース層とな
るｎ型半導体基板３１及びｐエミツタ層５が順次
積み重ねられて構成されており、ｎエミツタ層６
にカソード電極８が、ｐベース層４にｐ型高濃度
不純物層７を介してゲート電極１０が低抵抗に接
続されている。また、ｐエミツタ層５とｎベース
層であるｎ型半導体基板３１は、アノード電極９
に接続される。その際、アノード電極９とｎ型半
導体基板３１とを低抵抗接触させるため、ｐエミ
ツタ層５に隣接する位置に、ｎ型半導体基板３１
と同一の導電型の高濃度ｎ型不純物層が、ｐエミ
ツタ層５より厚く形成される。 The GTO thyristor with short-circuited emitter structure is
As shown in the figure, there are many units in pellet 1.
The GTO thyristor 2 is arranged and configured.
Each GTO thyristor 2 has a cross-sectional structure as shown in FIG. This cross section is the - cross section in FIG. The unit GTO thyristor 2 is
The n-emitter layer 6, the p-base layer 4, the n-type semiconductor substrate 31 serving as the n-base layer, and the p-emitter layer 5 are stacked in sequence, and the n-emitter layer 6
A cathode electrode 8 is connected to the p base layer 4 through a p-type high concentration impurity layer 7, and a gate electrode 10 is connected to the p base layer 4 with low resistance. Further, the p-emitter layer 5 and the n-type semiconductor substrate 31, which is the n-base layer, are connected to the anode electrode 9.
connected to. At this time, in order to bring the anode electrode 9 and the n-type semiconductor substrate 31 into low-resistance contact, the n-type semiconductor substrate 31 is placed adjacent to the p emitter layer 5.
A heavily doped n-type impurity layer of the same conductivity type is formed thicker than the p emitter layer 5.
このような構成のGTOサイリスタの従来技術
による製造方法を単位GTOサイリスタ２の部分
のみの断面図によりその製造工程を示す第２図ａ
〜ｄにより説明する。 FIG. 2 a shows a manufacturing method of a GTO thyristor having such a configuration according to the prior art using a sectional view of only the unit GTO thyristor 2.
This will be explained by d.
(1) ｎ型半導体基板３１を用意し、公知の選択拡
散法によつて、このｎ型半導体基板３１内にｎ
型高濃度不純物層３を形成する〔第２図ａ〕。(1) Prepare an n-type semiconductor substrate 31, and apply n to the inside of this n-type semiconductor substrate 31 by a known selective diffusion method.
A high concentration impurity layer 3 is formed (FIG. 2a).
(2) 次に、この半導体基板３１の両主面からｐ型
不純物、例えば、Gaを全面拡散し、ｐベース
層４及びｐエミツタ層５を形成する〔第２図
ａ〕。(2) Next, a p-type impurity, for example, Ga , is diffused over the entire surface of both main surfaces of the semiconductor substrate 31 to form a p base layer 4 and a p emitter layer 5 [FIG. 2a].
(3) 更に、公知の選択拡散法によつて、ｐベース
層４の表面にｎエミツタ層６を形成する〔第２
図ｃ〕。(3) Furthermore, an n emitter layer 6 is formed on the surface of the p base layer 4 by a known selective diffusion method [second
Figure c].
(4) 最後に、ｎエミツタ層６の両側をエツチング
により段差形成し、特開昭57−201078号公報等
に示された公知の方法でｐ型高濃度不純物層７
を形成する〔第２図ｄ〕。(4) Finally, steps are formed on both sides of the n-emitter layer 6 by etching, and the p-type high-concentration impurity layer 7 is etched using a known method disclosed in Japanese Patent Laid-Open No. 57-201078.
[Fig. 2 d].
これらの工程は、ペレツト１上に構成される全
ての単位GTOサイリスタ２が同時形成されるよ
うに行われ、その際、ｎ型高濃度不純物層３の深
さがｐエミツタ層５の深さより大きくなるように
その拡散が制御される。また、これらの工程の終
了後、カソード電極８、アノード電極９及びゲー
ト電極１０の取付けが行われる。 These steps are performed so that all the unit GTO thyristors 2 configured on the pellet 1 are formed at the same time, and at this time, the depth of the n-type high concentration impurity layer 3 is greater than the depth of the p emitter layer 5. Its diffusion is controlled so that Furthermore, after these steps are completed, the cathode electrode 8, anode electrode 9, and gate electrode 10 are attached.
前記従来技術は、ベース電極が低抵抗接触され
ていないｎベース層となる基板３１とアノード電
極９とを低抵抗接触させるため、隣接するｐエミ
ツタ層５より深いｎ型高濃度不純物層３の形成の
ために１工程を要しており、素子製造原価低減の
障害となつている。すなわち、前記従来技術は、
単位GTOサイリスタ２をペレツト１内に製造す
るために、４回の拡散工程を必要とし、製品コス
トの高いGTOサイリスタしか製造できないとい
う問題点を有している。
In the prior art, in order to bring the anode electrode 9 into low-resistance contact with the substrate 31, which is an n-base layer with which the base electrode is not in low-resistance contact, the n-type high-concentration impurity layer 3 is formed deeper than the adjacent p-emitter layer 5. This requires one process, which is an obstacle to reducing device manufacturing costs. That is, the conventional technology is
In order to manufacture the unit GTO thyristor 2 in the pellet 1, four diffusion steps are required, and there is a problem in that only GTO thyristors with high product costs can be manufactured.
本発明の目的は、前記従来技術の問題点を解決
し、単位GTOサイリスタ２をペレツト１内に作
り込むために必要な拡散工程数を削減し、従来技
術の場合と同一の接合構造を持つGTOサイリス
タを安価に製造することのできるこの種半導体装
置の製造方法を提供することにある。 The purpose of the present invention is to solve the problems of the prior art, reduce the number of diffusion steps required to form the unit GTO thyristor 2 in the pellet 1, and create a GTO thyristor having the same bonding structure as the prior art. It is an object of the present invention to provide a method for manufacturing a semiconductor device of this type, which allows thyristors to be manufactured at low cost.
本発明によれば、前記目的は、従来技術におけ
るｎ型高濃度不純物層３とｎエミツタ層６の形成
を１回の拡散工程で行い、さらに、ｐ型高濃度不
純物層７とｐエミツタ層５の形成を１回の拡散工
程で行うことにより達成される。
According to the present invention, the above object is to perform the formation of the n-type high concentration impurity layer 3 and the n emitter layer 6 in a single diffusion process in the prior art, and further to form the p-type high concentration impurity layer 7 and the p emitter layer 5 in one diffusion process. This is achieved by performing the formation in one diffusion step.
ｎ型高濃度不純物層３とｎエミツタ層６を形成
する拡散と、ｐ型高濃度不純物層７とｐエミツタ
層５を形成する拡散とを夫々１回の工程で行うこ
とにより、本発明は、３回の拡散工程で、ペレツ
ト内１にGTOサイリスタを作り込むことができ
る。
By performing the diffusion to form the n-type high-concentration impurity layer 3 and the n-emitter layer 6 and the diffusion to form the p-type high-concentration impurity layer 7 and the p-emitter layer 5 in one process, the present invention can achieve the following steps: A GTO thyristor can be built into the pellet in three diffusion steps.
以下、本発明による半導体装置の製造方法の一
実施例を図面により詳細に説明する。
Hereinafter, one embodiment of the method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings.
第１図ａ，ｂ，ｃは本発明の一実施例の製造方
法を説明する単位GTOサイリスタ２の断面図で
ある。第１図ａ〜ｃにおいて、図面の符号は第２
図〜第４図の場合と同一である。 FIGS. 1a, b, and c are cross-sectional views of a unit GTO thyristor 2 for explaining a manufacturing method according to an embodiment of the present invention. In Figures 1a to 1c, the reference numbers in the drawings indicate the second
This is the same as in the case of FIGS.
(1) ｎ型半導体基板３１を用意し、このｎ型半導
体基板に対してその両主面からｐ型不純物、例
えばGaを全面拡散し、形成された片側のｐ型
不純物層をラツプ等によつて除去し、ｐベース
層４を形成する〔第１図ａ〕。(1) Prepare an n-type semiconductor substrate 31, diffuse a p-type impurity, for example, Ga , over the entire surface of the n-type semiconductor substrate from both main surfaces, and wrap the formed p-type impurity layer on one side. The p base layer 4 is then removed (FIG. 1a).
(2) 次に、公知の選択拡散法によつて、両主面に
ｎ型不純物、例えばｐを拡散し、ｎ型高濃度不
純物層３及びｎエミツタ層６を形成する。この
工程で形成されるｎ型高濃度不純物層３及びｎ
エミツタ層６は、同一条件で拡散処理が行われ
るのでほぼ同一の深さとなる〔第１図ｂ〕。(2) Next, an n-type impurity, for example p, is diffused into both main surfaces by a known selective diffusion method to form an n-type high concentration impurity layer 3 and an n emitter layer 6. The n-type high concentration impurity layer 3 and n
Since the emitter layer 6 is diffused under the same conditions, it has approximately the same depth (FIG. 1b).
(3) 次に、ｎエミツタ層６の両側をエツチングに
より段差形成し、その後、ｎエミツタ層６側の
主面から公知のセルフアライメント方式によつ
て、また反対側主面から全面拡散法によつて、
同時にｐ型不純物を拡散し、ｐ型高濃度不純物
層７及びｐエミツタ層５を形成する。この工程
によつて形成されるｐ型高濃度不純物層７及び
ｐエミツタ層５は、同一条件で拡散処理が行わ
れるので、ほぼ同一の深さになる。また、この
工程は、ｎ型高濃度不純物層３の深さより、ｐ
エミツタ層５の深さが小さくなるようにその拡
散が制御される〔第１図ｃ〕。(3) Next, steps are formed on both sides of the n-emitter layer 6 by etching, and then from the main surface on the n-emitter layer 6 side by a known self-alignment method and from the opposite main surface by a full-surface diffusion method. Then,
At the same time, p-type impurities are diffused to form a p-type high concentration impurity layer 7 and a p emitter layer 5. Since the p-type high concentration impurity layer 7 and the p emitter layer 5 formed by this step are diffused under the same conditions, they have approximately the same depth. In addition, in this step, p
The diffusion is controlled so that the depth of the emitter layer 5 is reduced (FIG. 1c).
これらの工程が、ペレツト１上に構成される全
ての単位GTOサイリスタ２を同時に形成するよ
うに行われる点及び、これらの工程の終了後、カ
ソード電極８、アノード電極９、ゲート電極１０
を取付ける点は、従来技術の場合と同様である。 These steps are carried out so as to simultaneously form all the unit GTO thyristors 2 formed on the pellet 1, and after these steps are completed, the cathode electrode 8, anode electrode 9, gate electrode 10
The point of attachment is the same as in the case of the prior art.
前述した本発明の一実施例の製造方法により得
られたGTOサイリスタは、ｐベース層４にゲー
ト電極１０を低抵抗接触させるためのｐ型高濃度
不純物層７を有し、ゲート電極１０が低抵抗接触
されていないｎベース層に、アノード電極９を低
抵抗接触させるための、隣接するｐエミツタ層５
の深さより深いｎ型高濃度不純物層３を有する。
第３，４図に示した従来技術によると同様な構造
を有するものとなる。従つて、本発明の実施例に
よれば、単位GTOサイリスタ２をペレツト１内
に製造するために、従来技術より少ない３回の拡
散工程を必要とするのみで、従来技術と同様な構
造を有するGTOサイリスタを安価に製造し、提
供することができる。 The GTO thyristor obtained by the manufacturing method of the embodiment of the present invention described above has a p-type high concentration impurity layer 7 for bringing the gate electrode 10 into low resistance contact with the p base layer 4, and the gate electrode 10 has a low resistance. An adjacent p emitter layer 5 for bringing the anode electrode 9 into low resistance contact with the n base layer which is not in resistance contact.
The n-type high concentration impurity layer 3 is deeper than the depth of the n-type high concentration impurity layer 3.
The prior art shown in FIGS. 3 and 4 has a similar structure. Therefore, according to the embodiment of the present invention, in order to manufacture the unit GTO thyristor 2 in the pellet 1, only three diffusion steps are required, which is less than in the prior art, and the structure is similar to that in the prior art. GTO thyristors can be manufactured and provided at low cost.
以上説明したように、本発明によれば、単位
GTOサイリスタを３回の不純物拡散工程でペレ
ツト内に作り込むことができ、従来技術の場合と
同一の性能を有するGTOサイリスタを安価に製
造、提供することができる。
As explained above, according to the present invention, the unit
The GTO thyristor can be built into the pellet through three impurity diffusion steps, and the GTO thyristor having the same performance as the conventional technology can be manufactured and provided at low cost.
第１図ａ，ｂ，ｃは本発明の一実施例の製造方
法を説明する単位GTOサイリスタの断面図、第
２図ａ，ｂ，ｃ，ｄは従来技術による製造方法を
説明する単位GTOサイリスタの断面図、第３図、
第４図は従来技術及び本発明によるGTOサイリ
スタの平面図及び単位GTOサイリスタの断面図
である。
１……ペレツト、２……単位GTOサイリスタ、
３……ｎ型高濃度不純物層、３１……ｎ型半導体
基板、４……ｐベース層、５……ｐエミツタ層、
６……ｎエミツタ層、７……ｐ型高濃度不純物
層、８……カソード電極、９……アノード電極、
１０……ゲート電極。
Figures 1a, b, and c are cross-sectional views of a unit GTO thyristor illustrating a manufacturing method according to an embodiment of the present invention, and Figures 2a, b, c, and d are unit GTO thyristors illustrating a manufacturing method according to the prior art. Cross-sectional view, Figure 3,
FIG. 4 is a plan view of a GTO thyristor according to the prior art and the present invention, and a sectional view of a unit GTO thyristor. 1...Pellet, 2...Unit GTO thyristor,
3...n-type high concentration impurity layer, 31...n-type semiconductor substrate, 4...p base layer, 5...p emitter layer,
6...n emitter layer, 7...p type high concentration impurity layer, 8... cathode electrode, 9... anode electrode,
10...Gate electrode.
Claims (1)
る相互間でその導電型が異なる中央の２つのベー
ス層とその両側のエミツタ層とによるpnpnの４
層が形成され、半導体基板の一方の主表面に一方
のエミツタ層と該一方のエミツタ層に隣接する一
方のベース層の高濃度不純物層が露出し、半導体
基板の他方の主表面に他方のエミツタ層と該他方
のエミツタ層に隣接する他方のベース層の高濃度
不純物層が露出し、一方のエミツタ層にカソー
ド、一方のベース層にゲート、他方のエミツタ層
と他方のベース層にアノードをそれぞれ低抵抗接
触させて構成される半導体装置の製造方法におい
て、前記一方のエミツタ層と前記他方のエミツタ
層に隣接する前記他方のベーす層の高濃度不純物
層とを同時に形成することを特徴とする半導体装
置の製造方法。 ２ 特許請求の範囲第１項において、前記他方の
エミツタ層と前記一方のエミツタ層に隣接する前
記一方のベース層の高濃度不純物層とを同時に形
成することを特徴とする半導体装置の製造方法。[Claims] 1. A semiconductor substrate having a pair of main surfaces, two central base layers whose conductivity types differ between adjacent ones, and emitter layers on both sides of the four base layers.
One emitter layer and the high concentration impurity layer of one base layer adjacent to the one emitter layer are exposed on one main surface of the semiconductor substrate, and the other emitter layer is exposed on the other main surface of the semiconductor substrate. The high concentration impurity layer of the other base layer adjacent to the other emitter layer is exposed, a cathode is provided to one emitter layer, a gate is provided to one base layer, and an anode is provided to the other emitter layer and the other base layer. A method for manufacturing a semiconductor device configured with low resistance contact, characterized in that the one emitter layer and the high concentration impurity layer of the other base layer adjacent to the other emitter layer are formed at the same time. A method for manufacturing a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the other emitter layer and the high concentration impurity layer of the one base layer adjacent to the one emitter layer are formed at the same time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4152487A JPS63209167A (en) | 1987-02-26 | 1987-02-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4152487A JPS63209167A (en) | 1987-02-26 | 1987-02-26 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63209167A JPS63209167A (en) | 1988-08-30 |
| JPH0560667B2 true JPH0560667B2 (en) | 1993-09-02 |
Family
ID=12610777
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4152487A Granted JPS63209167A (en) | 1987-02-26 | 1987-02-26 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63209167A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5248622A (en) * | 1988-10-04 | 1993-09-28 | Kabushiki Kashiba Toshiba | Finely controlled semiconductor device and method of manufacturing the same |
| EP0366916B1 (en) * | 1988-10-04 | 1995-06-14 | Kabushiki Kaisha Toshiba | Shorted-anode semiconductor device and methods of making the same |
| JPH0282052U (en) * | 1988-12-13 | 1990-06-25 |
-
1987
- 1987-02-26 JP JP4152487A patent/JPS63209167A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63209167A (en) | 1988-08-30 |
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