JPS60198776A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60198776A JPS60198776A JP5393184A JP5393184A JPS60198776A JP S60198776 A JPS60198776 A JP S60198776A JP 5393184 A JP5393184 A JP 5393184A JP 5393184 A JP5393184 A JP 5393184A JP S60198776 A JPS60198776 A JP S60198776A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- mask
- semiconductor substrate
- gate
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000005530 etching Methods 0.000 claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 50
- 239000002344 surface layer Substances 0.000 claims description 2
- 230000007423 decrease Effects 0.000 abstract description 2
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 6
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 229910017604 nitric acid Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000866 electrolytic etching Methods 0.000 description 1
- 230000005764 inhibitory process Effects 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1012—Base regions of thyristors
- H01L29/102—Cathode base regions of thyristors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は交互に異なる導電形の層が積層された半導体基
板の最上層の電極が接触板に接触し、その層に隣接する
層に線表面より堀り下けられた一段低い面に電極が設け
られる、例えばゲートターンオフ(GTO)サイリスタ
、パワートランジスタのような半導体装置の製造方法に
関する。Detailed description of the invention [Technical field to which the invention pertains] The present invention relates to a semiconductor substrate in which layers of different conductivity types are stacked alternately, and an electrode on the top layer contacts a contact plate, and a layer adjacent to the layer is connected to a wire. The present invention relates to a method of manufacturing a semiconductor device, such as a gate turn-off (GTO) thyristor or a power transistor, in which an electrode is provided on a surface that is one step lower than the surface.
そのような半導体装置では、半導体基板の主表面上に主
電極膜と制御電極膜を有し、主電極膜に通電のための電
極板を接触させ九とき、この電極板が制御電極膜とは接
触することのなhように主表面に凹凸を設け、主電極膜
を凸面上に、制御電極膜を凹面上に形成している。第1
図は電力用GTOサイリスタの主表面を示し、半導体基
板の主表面上にカソード電極膜1とゲート電極膜2とを
有する。第2図はこの素子の断面を模式的に示したもの
で、p型エミッタ(pl)、nfiベース(nII)、
p!i11ベース(pIB>、n型エミッタ(n、)の
4層からなるシリコン板3がろう材4によシ、例えばモ
リプデ/からなる支持板5に固着されている。n1層の
表面には、例えばホトエツチングによ多形成したマスク
を用いての選択エツチングによシ凹凸が形成され、pB
層まで、*b下げられた凹面6にはゲート電極膜2、連
層上の凸面7にはカソード電極膜lが設けられている。Such a semiconductor device has a main electrode film and a control electrode film on the main surface of the semiconductor substrate, and when an electrode plate for energization is brought into contact with the main electrode film, this electrode plate is different from the control electrode film. The main surface is provided with irregularities so that they do not come into contact with each other, and the main electrode film is formed on the convex surface and the control electrode film is formed on the concave surface. 1st
The figure shows the main surface of a power GTO thyristor, which has a cathode electrode film 1 and a gate electrode film 2 on the main surface of a semiconductor substrate. Figure 2 schematically shows the cross section of this device, with a p-type emitter (pl), an nfi base (nII),
p! A silicon plate 3 consisting of four layers of an i11 base (pIB>) and an n-type emitter (n, ) is fixed to a support plate 5 made of a brazing material 4, for example, molybdenum.On the surface of the n1 layer, For example, unevenness is formed by selective etching using a mask formed by photoetching, and pB
A gate electrode film 2 is provided on the concave surface 6 lowered to *b layer, and a cathode electrode film 1 is provided on the convex surface 7 above the continuous layer.
カソード電極膜1は第1図に示すように細いので、電流
がこの膜1をその面方向に流れて電圧降下が生ずるのを
防ぐためと、半導体基板内で生じた熱を外部へ放散させ
るため、その全面にカソード電極板8を接触させる。ゲ
ート電極膜2は凹面6に存在するのでカソード電極板8
によシゲート電極膜2がカソード電極膜lと短絡される
ことはない。このような構造のGTOにおいて、最も重
要な性能である電流遮断性能に影響を及ばず因子として
は、カソードの幅、pB層の層抵抗、n1層中の電流キ
ャリアの寿命、ゲートインピーダンスなどがある。いま
他の条件を同一としたとき、ゲートインピーダンスの影
響は第3図に示す通りで、GTOの性能向上にはこのゲ
ートインピーダンスを低減することが有効であシ、その
ために付加的な拡散工程を施こすことは、例えば特開昭
53−37388船報によシ公知である。特にpB層を
拡散法で形成した場合、ゲート部をエツチング等によシ
堀シ下げると次第に拡散層の低濃度部分が現われるため
、急速にゲートインピーダンスの増大が起こるので、そ
のような付加的な拡散工程が不可欠である。この付加拡
散層は、表面濃度が高い程、例えばlXlocm 以上
あるのが有効であるが、しかしこのような高い表面濃度
の拡散層がゲート、カソード間接合9に迄及ぶと、その
接合の降伏電圧を6v程度まで低下させるという別の特
性劣化を招く。従って、この拡散層はゲート。As the cathode electrode film 1 is thin as shown in Fig. 1, this is used to prevent current from flowing through the film 1 in the direction of its surface and cause a voltage drop, and to dissipate heat generated within the semiconductor substrate to the outside. , the cathode electrode plate 8 is brought into contact with the entire surface thereof. Since the gate electrode film 2 is present on the concave surface 6, the cathode electrode plate 8
The silicate gate electrode film 2 is never short-circuited with the cathode electrode film l. In a GTO with such a structure, factors that do not affect the most important performance, current interruption performance, include the width of the cathode, the layer resistance of the pB layer, the lifetime of current carriers in the n1 layer, and the gate impedance. . Now, assuming other conditions are the same, the influence of gate impedance is as shown in Figure 3. It is effective to reduce this gate impedance to improve the performance of GTO, and for that purpose an additional diffusion process is required. This method is known, for example, from Japanese Unexamined Patent Application Publication No. 53-37388. In particular, when the pB layer is formed by the diffusion method, when the gate part is etched or etched down, a low concentration part of the diffusion layer gradually appears, resulting in a rapid increase in gate impedance. A diffusion process is essential. The higher the surface concentration of this additional diffusion layer is, the more effective it is, for example, 1Xlocm or more.However, if such a high surface concentration diffusion layer extends to the gate-cathode junction 9, the breakdown voltage of that junction will increase. Another characteristic deterioration occurs in that the voltage drops to about 6V. Therefore, this diffusion layer is a gate.
カソード間接合には達しないような選択拡散でなければ
ならない。そのため、ゲート部堀下げ工程のあと、マス
ク材で表面を覆って、ホトエツチングによシバターンを
形成する必要があった。しかもこのホトエツチング工程
によシ形成されるマスクのパターンが、以前の凹凸形成
のだめのマスクのパターンとずれる可能性が常に存在し
、ゲート。The selective diffusion must be such that it does not reach the cathode-to-cathode junction. Therefore, after the gate trenching step, it was necessary to cover the surface with a mask material and form a shiver turn by photo-etching. Moreover, there is always a possibility that the mask pattern formed by this photoetching process will deviate from the pattern of the mask used for forming the unevenness.
カソード間接合9と拡散層との間の距離が不均一。The distance between the inter-cathode junction 9 and the diffusion layer is uneven.
不平衡となシ、半導体装置の特性低下につながる虞があ
った。There is a possibility that the imbalance may lead to deterioration of the characteristics of the semiconductor device.
本発明は、とのGTOサイリスタのような半導体基板の
主表面から堀シ下げられた一段低い面に、最上層に隣接
した層の電極が設けられる半導体装置に対して、一段低
い面から所定の領域のみに容易にしか本確実に高不純物
濃度表面層を形成することのできる製造方法を提供する
ことを目的とする。The present invention provides a semiconductor device, such as a GTO thyristor, in which an electrode of a layer adjacent to the top layer is provided on a lower surface dug down from the main surface of a semiconductor substrate. It is an object of the present invention to provide a manufacturing method that can easily and reliably form a high impurity concentration surface layer only in a region.
本発明によれば、半導体基板主表面上の所定の領域にマ
スクを被着し、マスクで覆われない領域を堀シ下けて一
段低い藺を形成した後、マスクを残留させたままで半導
体基板主表面の露出領域全面から不純物を拡散し、次い
で導電形によシエッチング速度の異なるエツチング手段
を用いて最上層の露出領域面からの不純物拡散層を優先
的に除去することによシ上記の目的が達成される。According to the present invention, a mask is applied to a predetermined area on the main surface of a semiconductor substrate, and the area not covered by the mask is dug down to form a lower layer, and then the semiconductor substrate is exposed with the mask remaining. By diffusing the impurity from the entire exposed region of the main surface, and then using etching means having different etching rates depending on the conductivity type, the impurity diffusion layer from the exposed region of the top layer is preferentially removed. The purpose is achieved.
第4図(a)〜(d)は本発明の一実施例の工程を順次
示すもので、第1.第2図と共通の部分には同一の符号
が付されている。半導体基板3の表面にゲート部堀下け
のための、例えば酸化膜、窒化膜等を成膜し、ホトエツ
チングによシカソードパターンのマスク10を形成する
(図a)。次いでこのマスク10を用いて、例えばエツ
チングによりpB層に達するゲート部堀下げを行う(図
b)。エツチング液としては硝酸、弗酸、酢酸の混酸等
が用いられる。次に図Cに示すようにpB’ipと同じ
導電形、すなわちp形の不純物の、例えば3〜5μmの
深さの付加拡散層11を形成する。拡散は基板3の上面
の露出部に非選択的に行なわれるので、ゲート。FIGS. 4(a) to 4(d) sequentially show the steps of an embodiment of the present invention. Components common to those in FIG. 2 are given the same reference numerals. For example, an oxide film, a nitride film, or the like is formed on the surface of the semiconductor substrate 3 for trenching the gate portion, and a diagonal cathode pattern mask 10 is formed by photo-etching (FIG. 1A). Next, using this mask 10, the gate portion is dug down to reach the pB layer by, for example, etching (FIG. b). As the etching solution, a mixed acid of nitric acid, hydrofluoric acid, acetic acid, etc. is used. Next, as shown in FIG. C, an additional diffusion layer 11 of impurity of the same conductivity type as pB'ip, that is, p-type, is formed to a depth of, for example, 3 to 5 μm. Since the diffusion is performed non-selectively on the exposed portion of the upper surface of the substrate 3, the gate.
カソード間接合9の露出部付近にも高濃度に拡散される
。この状態では前述のようにカソード、ゲート間接合9
の降伏電圧が低下するので、n11層の側面t−図dに
示すように付加拡散層11の深さだけ除去することによ
シ、接合9の降伏電圧は回復する。nit層の除去は、
電解エツチングによpn1層のみを選択的にi去する方
法、あるいはnu層に対してpB層よシ大きいエツチン
グ速度を有するエツチング液を用いる方法によって行の
、ことができホトエツチング技術を用いる必要がない。It is also diffused at a high concentration near the exposed portion of the inter-cathode junction 9. In this state, as mentioned above, the junction 9 between the cathode and the gate
Since the breakdown voltage of the junction 9 decreases, the breakdown voltage of the junction 9 is restored by removing only the depth of the additional diffusion layer 11 from the side surface t of the n11 layer as shown in FIG. d. Removal of the nit layer is
This can be done by selectively removing only the PN1 layer by electrolytic etching, or by using an etching solution that has a higher etching rate for the NU layer than for the pB layer, and there is no need to use photoetching techniques. .
nm層に対してp層層よシ大きいエツチング速度を有す
るエツチング液の例としては、硝酸、弗酸、酢酸の3対
1対Bの比の混酸がある。なお最上層がp層、隣接層が
n層の場合には硝酸、弗酸、水の混合比が、8対1対ユ
のエツチング液を用いてp層を優先的にエツチングする
。An example of an etching solution having a higher etching rate for the nm layer than for the p layer is a mixed acid of nitric acid, hydrofluoric acid, and acetic acid in a ratio of 3:1:B. When the uppermost layer is a p-layer and the adjacent layer is an n-layer, the p-layer is preferentially etched using an etching solution with a mixing ratio of nitric acid, hydrofluoric acid, and water of 8:1:y.
本発明は、交互に異なる導電形の層を有する半導体基板
の最上層に隣接する層に接触する電極が主表面から堀シ
下げられた一段低い面に形成される半導体装置の前記の
電極へのインピーダンスを低下させる目的で電極に接す
る一段低い面に低抵抗層を形成する場合に、堀シ下げの
ためのマスクを残して露出面全面に不純物を付加拡散し
、その後導電形によシエッチング速度に差のあ、るエツ
チング手段を用いて最上!露出面からの付加拡散によっ
て生じた異なる導電形の高不純物濃度層を除去するもの
である。この方法では、全面拡散後、マスクを用いて選
択的に拡散層を除去する場合に比してホトエツチング工
程が不要となシ、経済的に有利である。さらに選択エツ
チングのためのマスクパターンと堀シ゛下げのためのマ
スクパターンの不整合という問題はなく、導電形による
エツチング速度差を利用したエツチング手段にょシ自己
整合的に付加拡散層が所定の領域のみに形成されるので
、半導体装置の特性の均一化が達せられ。The present invention provides a semiconductor device in which an electrode contacting a layer adjacent to an uppermost layer of a semiconductor substrate having layers of alternately different conductivity types is formed on a lower surface lowered from the main surface. When forming a low-resistance layer on a lower surface in contact with an electrode for the purpose of lowering impedance, impurities are added and diffused over the entire exposed surface leaving a mask for lowering the trench, and then etching speed is increased depending on the conductivity type. The best using a unique etching method! This removes a high impurity concentration layer of a different conductivity type caused by additional diffusion from the exposed surface. This method is economically advantageous because it does not require a photoetching step compared to the case where the diffusion layer is selectively removed using a mask after the entire surface is diffused. Furthermore, there is no problem of mismatch between the mask pattern for selective etching and the mask pattern for trenching, and the etching method that takes advantage of the difference in etching speed depending on the conductivity type allows the additional diffusion layer to be added only to a predetermined region in a self-aligned manner. Therefore, the characteristics of the semiconductor device can be made uniform.
得られる効果は極めて大きい。The effects obtained are extremely large.
@1図はGTOサイリスタの平面図、第2図はGTOサ
イリスタの部分的縦断面図、第3図はGTOサイリスタ
のゲートインピーダンスと遮断電流との関係線図、第4
図は本発明の〜実施例の工程を順次示す部分的縦断面図
である。
1・・・カソード電極膜、2・・・ゲート電極膜、3・
・・シリコン板、6・・・凹面、 10・・・マスク、
11・・・p影付tlll 72図
ゲートインヒ一ダンス
才3[2]
74図@Figure 1 is a plan view of the GTO thyristor, Figure 2 is a partial vertical cross-sectional view of the GTO thyristor, Figure 3 is a relationship diagram between the gate impedance and cut-off current of the GTO thyristor, and Figure 4
The figures are partial vertical cross-sectional views sequentially showing the steps of embodiments of the present invention. 1... Cathode electrode film, 2... Gate electrode film, 3...
... silicon plate, 6 ... concave surface, 10 ... mask,
11...p Shaded tllll Figure 72 Gate inhibition 3 [2] Figure 74
Claims (1)
体基板の最上層には主表面において、そして最上層に隣
接し九層には、主表面から堀シ下げられ九一段低い面に
おいて接触する電極がそれぞれ設けられ、該一段低り面
から高不純物濃度表面層が形成される半導体装置の製造
方法において、半導体基板主表面上の所定の領域にマス
クを被着し、マスクで覆われない領域を堀シ下げて一段
低い面を形成した後、マスクを一留させたitで前記半
導体基板主表面の露出領域全面から不純物を拡散し、次
いで導電形によりエツチング速度の異なるエツチング手
段を用いて最上′層の露出領域面からの不純物拡散層を
除去することを特徴とする半導体装置の製造方法。l) Contact the top layer of a semiconductor substrate having a stack of alternating layers of different conductivity types at its main surface, and contact the nine layers adjacent to the top layer at a surface that is 91 steps lower than the main surface. In a method for manufacturing a semiconductor device in which a high impurity concentration surface layer is formed from the lower surface of the semiconductor substrate, a mask is applied to a predetermined region on the main surface of the semiconductor substrate and the region is not covered with the mask. After trenching the region to form a lower surface, impurities are diffused from the entire exposed region of the main surface of the semiconductor substrate by keeping the mask in place, and then etching using etching means having different etching speeds depending on the conductivity type. 1. A method of manufacturing a semiconductor device, comprising removing an impurity diffusion layer from an exposed region surface of the uppermost layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5393184A JPS60198776A (en) | 1984-03-21 | 1984-03-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5393184A JPS60198776A (en) | 1984-03-21 | 1984-03-21 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60198776A true JPS60198776A (en) | 1985-10-08 |
Family
ID=12956479
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5393184A Pending JPS60198776A (en) | 1984-03-21 | 1984-03-21 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60198776A (en) |
-
1984
- 1984-03-21 JP JP5393184A patent/JPS60198776A/en active Pending
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