JPS60198776A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the uniformity of characteristics of the titled device by a method wherein an impurity-diffused layer from the surface of an exposed region at the uppermost layer is removed with priority by using etching means having speeds different to each other with regards to conductivity types. CONSTITUTION:The gate section reaching a PB layer is dug down by using a mask 10 to the surface of a semiconductor substrate 3. An additional diffused layer 11 with an impurity of the same conductivity type as that of the PB layer is formed. Since diffusion is carried out non-selectively to the exposed part in the upper surface of the substrate 3, the impurity is diffused also to the neighborhood of the exposed part of a gate-cathode junction 9 at high concentration. The yielding voltage of the junction 9 decreases under this condition; therefore, said voltage of the junction 9 recovers by removing the side surface of an nE layer by the depth of the layer 11. Since the layer 11 is formed only at a required region in such a manner, the uniformity of characteristics of the titled device can be attained.

Description

Detailed description of the invention [Technical field to which the invention pertains] The present invention relates to a semiconductor substrate in which layers of different conductivity types are stacked alternately, and an electrode on the top layer contacts a contact plate, and a layer adjacent to the layer is connected to a wire. The present invention relates to a method of manufacturing a semiconductor device, such as a gate turn-off (GTO) thyristor or a power transistor, in which an electrode is provided on a surface that is one step lower than the surface.

[Prior art and its problems]

Such a semiconductor device has a main electrode film and a control electrode film on the main surface of the semiconductor substrate, and when an electrode plate for energization is brought into contact with the main electrode film, this electrode plate is different from the control electrode film. The main surface is provided with irregularities so that they do not come into contact with each other, and the main electrode film is formed on the convex surface and the control electrode film is formed on the concave surface. 1st
The figure shows the main surface of a power GTO thyristor, which has a cathode electrode film 1 and a gate electrode film 2 on the main surface of a semiconductor substrate. Figure 2 schematically shows the cross section of this device, with a p-type emitter (pl), an nfi base (nII),
p! A silicon plate 3 consisting of four layers of an i11 base (pIB>) and an n-type emitter (n, ) is fixed to a support plate 5 made of a brazing material 4, for example, molybdenum.On the surface of the n1 layer, For example, unevenness is formed by selective etching using a mask formed by photoetching, and pB
A gate electrode film 2 is provided on the concave surface 6 lowered to *b layer, and a cathode electrode film 1 is provided on the convex surface 7 above the continuous layer.

As the cathode electrode film 1 is thin as shown in Fig. 1, this is used to prevent current from flowing through the film 1 in the direction of its surface and cause a voltage drop, and to dissipate heat generated within the semiconductor substrate to the outside. , the cathode electrode plate 8 is brought into contact with the entire surface thereof. Since the gate electrode film 2 is present on the concave surface 6, the cathode electrode plate 8
The silicate gate electrode film 2 is never short-circuited with the cathode electrode film l. In a GTO with such a structure, factors that do not affect the most important performance, current interruption performance, include the width of the cathode, the layer resistance of the pB layer, the lifetime of current carriers in the n1 layer, and the gate impedance. . Now, assuming other conditions are the same, the influence of gate impedance is as shown in Figure 3. It is effective to reduce this gate impedance to improve the performance of GTO, and for that purpose an additional diffusion process is required. This method is known, for example, from Japanese Unexamined Patent Application Publication No. 53-37388. In particular, when the pB layer is formed by the diffusion method, when the gate part is etched or etched down, a low concentration part of the diffusion layer gradually appears, resulting in a rapid increase in gate impedance. A diffusion process is essential. The higher the surface concentration of this additional diffusion layer is, the more effective it is, for example, 1Xlocm or more.However, if such a high surface concentration diffusion layer extends to the gate-cathode junction 9, the breakdown voltage of that junction will increase. Another characteristic deterioration occurs in that the voltage drops to about 6V. Therefore, this diffusion layer is a gate.

The selective diffusion must be such that it does not reach the cathode-to-cathode junction. Therefore, after the gate trenching step, it was necessary to cover the surface with a mask material and form a shiver turn by photo-etching. Moreover, there is always a possibility that the mask pattern formed by this photoetching process will deviate from the pattern of the mask used for forming the unevenness.

The distance between the inter-cathode junction 9 and the diffusion layer is uneven.

There is a possibility that the imbalance may lead to deterioration of the characteristics of the semiconductor device.

[Purpose of the invention]

The present invention provides a semiconductor device, such as a GTO thyristor, in which an electrode of a layer adjacent to the top layer is provided on a lower surface dug down from the main surface of a semiconductor substrate. It is an object of the present invention to provide a manufacturing method that can easily and reliably form a high impurity concentration surface layer only in a region.

[Key points of the invention]

According to the present invention, a mask is applied to a predetermined area on the main surface of a semiconductor substrate, and the area not covered by the mask is dug down to form a lower layer, and then the semiconductor substrate is exposed with the mask remaining. By diffusing the impurity from the entire exposed region of the main surface, and then using etching means having different etching rates depending on the conductivity type, the impurity diffusion layer from the exposed region of the top layer is preferentially removed. The purpose is achieved.

[Embodiments of the invention]

FIGS. 4(a) to 4(d) sequentially show the steps of an embodiment of the present invention. Components common to those in FIG. 2 are given the same reference numerals. For example, an oxide film, a nitride film, or the like is formed on the surface of the semiconductor substrate 3 for trenching the gate portion, and a diagonal cathode pattern mask 10 is formed by photo-etching (FIG. 1A). Next, using this mask 10, the gate portion is dug down to reach the pB layer by, for example, etching (FIG. b). As the etching solution, a mixed acid of nitric acid, hydrofluoric acid, acetic acid, etc. is used. Next, as shown in FIG. C, an additional diffusion layer 11 of impurity of the same conductivity type as pB'ip, that is, p-type, is formed to a depth of, for example, 3 to 5 μm. Since the diffusion is performed non-selectively on the exposed portion of the upper surface of the substrate 3, the gate.

It is also diffused at a high concentration near the exposed portion of the inter-cathode junction 9. In this state, as mentioned above, the junction 9 between the cathode and the gate
Since the breakdown voltage of the junction 9 decreases, the breakdown voltage of the junction 9 is restored by removing only the depth of the additional diffusion layer 11 from the side surface t of the n11 layer as shown in FIG. d. Removal of the nit layer is
This can be done by selectively removing only the PN1 layer by electrolytic etching, or by using an etching solution that has a higher etching rate for the NU layer than for the pB layer, and there is no need to use photoetching techniques. .

An example of an etching solution having a higher etching rate for the nm layer than for the p layer is a mixed acid of nitric acid, hydrofluoric acid, and acetic acid in a ratio of 3:1:B. When the uppermost layer is a p-layer and the adjacent layer is an n-layer, the p-layer is preferentially etched using an etching solution with a mixing ratio of nitric acid, hydrofluoric acid, and water of 8:1:y.

〔Effect of the invention〕

The present invention provides a semiconductor device in which an electrode contacting a layer adjacent to an uppermost layer of a semiconductor substrate having layers of alternately different conductivity types is formed on a lower surface lowered from the main surface. When forming a low-resistance layer on a lower surface in contact with an electrode for the purpose of lowering impedance, impurities are added and diffused over the entire exposed surface leaving a mask for lowering the trench, and then etching speed is increased depending on the conductivity type. The best using a unique etching method! This removes a high impurity concentration layer of a different conductivity type caused by additional diffusion from the exposed surface. This method is economically advantageous because it does not require a photoetching step compared to the case where the diffusion layer is selectively removed using a mask after the entire surface is diffused. Furthermore, there is no problem of mismatch between the mask pattern for selective etching and the mask pattern for trenching, and the etching method that takes advantage of the difference in etching speed depending on the conductivity type allows the additional diffusion layer to be added only to a predetermined region in a self-aligned manner. Therefore, the characteristics of the semiconductor device can be made uniform.

The effects obtained are extremely large.

[Brief explanation of drawings]

@Figure 1 is a plan view of the GTO thyristor, Figure 2 is a partial vertical cross-sectional view of the GTO thyristor, Figure 3 is a relationship diagram between the gate impedance and cut-off current of the GTO thyristor, and Figure 4
The figures are partial vertical cross-sectional views sequentially showing the steps of embodiments of the present invention. 1... Cathode electrode film, 2... Gate electrode film, 3...
... silicon plate, 6 ... concave surface, 10 ... mask,
11...p Shaded tllll Figure 72 Gate inhibition 3 [2] Figure 74

Claims (1)

[Claims] l) Contact the top layer of a semiconductor substrate having a stack of alternating layers of different conductivity types at its main surface, and contact the nine layers adjacent to the top layer at a surface that is 91 steps lower than the main surface. In a method for manufacturing a semiconductor device in which a high impurity concentration surface layer is formed from the lower surface of the semiconductor substrate, a mask is applied to a predetermined region on the main surface of the semiconductor substrate and the region is not covered with the mask. After trenching the region to form a lower surface, impurities are diffused from the entire exposed region of the main surface of the semiconductor substrate by keeping the mask in place, and then etching using etching means having different etching speeds depending on the conductivity type. 1. A method of manufacturing a semiconductor device, comprising removing an impurity diffusion layer from an exposed region surface of the uppermost layer.