JPS6145395B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a field effect semiconductor device.

A field effect semiconductor device forms a predetermined depletion region inside the semiconductor device by applying a predetermined voltage to the gate, and controls the main current of the semiconductor device by controlling this depletion region. . Field effect transistors and field effect thyristors are known as representative examples of this type of semiconductor device. An important point in field-effect semiconductor devices is how high voltage and large current can be controlled with a low gate voltage. This is particularly important when devices of this type are used as switching devices in the power sector. The inventors of the present invention previously proposed a field effect switching element having a structure suitable for these uses (Japanese Patent Application No. 66648/1984, etc.).

However, recently, expectations for field-effect thyristors have been increasing day by day, and there is a demand for something that can independently control high voltages in the KV class and large currents in the 100A class, similar to conventional thyristors with a pnpn stacked structure. ing. There are several problems unique to controlling such large amounts of power. Firstly,
The purpose is to improve the breakdown voltage between the gate and cathode. If the channel to be cut off by the depletion layer is narrowed, a relatively low gate voltage (several tens of V or less) is sufficient in theoretical calculations, but when this type of semiconductor device is actually used, the control circuit at turn-off is required. It is necessary to withstand the reverse induced voltage generated by the induced component. Since the reverse induced voltage increases as the switching time becomes shorter, this becomes a problem, especially when taking advantage of the short switching time, which is the characteristic of field-effect thyristors.

Second, there is a problem with the manufacturing method. As shown in FIG. 1, conventionally, a gate region 13 embedded in a base region 12 of a semiconductor substrate 1 is connected to one main surface 100 of a semiconductor substrate 1 and connected to a gate electrode (not shown). It was necessary to form a diffusion region 131 with a high concentration. This area 131
is formed by selective diffusion using a mask 15 made of, for example, a SiO ₂ film. However, mask 1
When forming 5 by, for example, a known photo-etching method, unexpected pinholes may occur due to dust or the like. If a pinhole like this 151
If there is, an abnormal diffusion region 132 is generated from here at the same depth as the diffusion region 131. When this abnormal diffusion region contacts the cathode region 14, a diffusion region 131, a gate region 13, and an abnormal diffusion region 13 are formed between the gate electrode and the cathode electrode (not shown).
2. A p ⁺ n ⁺ junction diode consisting of the cathode region 14 is formed, and there is a problem in that the breakdown voltage between the gate and the cathode is lowered in this part.

Thirdly, uniformity of semiconductor devices is important. In order to increase the current, a method of arranging a large number of unit elements in parallel within the same semiconductor substrate and using a common electrode for each unit element is known. In this case, it is desirable that the structures of each unit element be the same. Particularly in a field effect semiconductor device having a fine gate structure as shown in FIG. 1, it is required that the channel width d be made uniform. The width d is usually several μm to several
Since it is as small as 10 μm, it has been difficult to precisely adjust the width d using conventional manufacturing methods.

SUMMARY OF THE INVENTION An object of the present invention is to provide an improved field effect semiconductor device that solves the above problems and a method for manufacturing the same.

In order to achieve such an object, the present invention is characterized in that, firstly, in a field effect semiconductor device having a gate region embedded in a base region in a semiconductor substrate, from one main surface of the semiconductor substrate; A trench reaching the gate region is formed, and a gate electrode is formed at the bottom of the trench.

Second, in addition to the first point, it is formed by a gate region and a surrounding semiconductor region of the opposite conductivity type.
It is at the point where the p-n junction terminates in a positive bevel on the side surface of the groove.

Third, a semiconductor structure has a cathode region of one conductivity type exposed on one main surface, a gate region of the other conductivity type, a base region of one conductivity type, and an anode region of the other conductivity type exposed on the other main surface. In order to form a semiconductor substrate, a semiconductor substrate of one conductivity type is prepared, an anode region of the other conductivity type is first formed on this semiconductor substrate, and a gate region is formed at the same time or subsequently.

The first feature makes it possible to prevent abnormal diffusion due to pinholes in the diffusion mask, and the second feature makes it possible to achieve a high breakdown voltage between the gate and the cathode. Furthermore, according to the third feature, since the anode region, which takes a long time to heat and tends to affect the concentration profile of the semiconductor substrate, is formed first, the concentration profile of the semiconductor substrate is subsequently formed. Heat treatment is not performed. Therefore, a field effect semiconductor device can be manufactured without changing the shape of the gate region, which requires a fine structure.

Next, examples of the present invention will be described. FIG. 2 shows a cross-sectional structure of one embodiment of the present invention. The silicon semiconductor substrate 100 includes a p ⁺ anode region 111, an n ^- type base region 112, a p type buried gate region 113,
p ⁺ type gate region 114, n ⁺ type cathode region 11
5, consisting of an n-type cathode region 116. 200 is an anode electrode, 300 is a gate electrode, 400 is a cathode electrode, and 500 is a surface protection SiO ₂ film. Further, 401 is a tungsten plate adjacent to the cathode electrode 400. Next, the operation of the semiconductor device of this embodiment will be explained. When the _SW between the cathode and the gate is opened with the main voltage V _A that makes the J ₁ junction forward biased between the anode electrode 200 and the tungsten plate 401, 111,1
Consisting of areas indicated by 12, 116, and 115
Current flows through the p ⁺ n ^- nn ⁺ diode. Next, 1
The p ⁺ n ^- pnn ⁺ thyristors consisting of regions 11, 112, 113, 116, and 115 become conductive. In this case, the cathode current i _K flows through the cathode electrode 400 and the tungsten plate 401, but since the cathode electrode 400 is very thin, the voltage drop there is small, and the temperature rise due to the voltage drop is small. Furthermore, since the large-volume tungsten plates are in contact with each other, the structure has good heat dissipation and is suitable for passing large currents. Further, in order to cut off this current, _SW is closed and a gate voltage V _G is applied between the gate electrode 300 and the tungsten plate 401 so that the J ₃ junction becomes reverse biased. This voltage causes the channel portion 117 to be pinched off by the depletion layer, and at the same time, carriers remaining in the n ^- base layer 112 flow through the buried gate region 113 to the gate electrode 300, and the main current is turned off. In order to turn off at high speed, it is desirable to apply a gate voltage higher than the voltage required to pinch off the channel portion 117.

In order to make the characteristics of this embodiment more clear, the second
An enlarged view of the main part of the embodiment shown in the figure is shown in FIG. In FIG. 3, the same parts as in FIG. 2 are indicated by the same symbols as in FIG. In FIG. 3, a pn formed by a buried gate region 113 and a cathode region 116
The end of junction J ₃ is exposed at the shoulder of mesa 101, and the impurity concentration of p-type buried gate region 113 is higher than that of n-type cathode region 116. Therefore, the exposed end of the pn junction _J3 has a positive bevel. As a result, the breakdown voltage between the gate and the cathode was improved, as will be described later.

The cathode region 115 with high impurity concentration has a planar structure and is not exposed at the shoulder of the mesa 101. With this structure, when the gate and cathode are reverse biased, the cathode region 11
Since the depletion layer formed in the mesa 101 tends to spread along the shoulder portion of the mesa 101, the surface electric field in this portion is relaxed, and the breakdown voltage between the gate and the cathode is improved. An example of how the deprived layer spreads is shown by dotted lines in Figures 3 and 4.

High impurity concentration gate region 114 is formed by selective diffusion to form ohmic contact between gate region 113 and gate electrode 300. Unlike the conventional example, the diffusion depth is extremely shallow.
Therefore, even if there is an unexpected pinhole in the diffusion mask and a p ⁺ diffusion region is generated at an unexpected location, there is no fear that the withstand voltage between the gate and the cathode will decrease.

FIG. 4 is an enlarged view of main parts of another embodiment of the present invention. The structure of the cathode region 115 is different from that of FIG. That is, in FIG. 4, the cathode region 115 is formed on the entire top surface of the mesa 101. With such a structure, the main current conduction area becomes large and the forward voltage drop can be reduced. Further, since the photoetching process for selectively diffusing the n ⁺ -type cathode region 115 as shown in FIG. 3 is not necessary, there is an advantage that the manufacturing process is simplified. Depending on the application, it is appropriate to decide whether to adopt the structure shown in Figure 3 and prioritize improving the breakdown voltage between the gate and cathode, or adopt the structure shown in Figure 4 and prioritize reducing the forward voltage drop. This is a matter that should be selected.

Next, a method suitable for manufacturing the semiconductor device of the above embodiment will be explained with reference to FIG. first,
n ^- type silicon substrate 11 with resistivity of 50 to 300 Ω・cm
The surface concentration is approximately 10 ¹⁹ to 10 ²⁰ cm from one main surface of 2.
^-3 , p ⁺ type anode region 111 with a thickness of about 70 μm is diffused with an impurity that gives p type such as poron.
was formed (b). Next, an impurity imparting p-type, such as boron, was selectively diffused from the other main surface to a surface concentration of approximately 10 ¹⁷ to ^{10 18} cm ^-3 to form a p-type buried gate region 113 (c). In order to completely bury this p-type buried gate region 113, an n-type cathode region 116 containing phosphorus as an impurity and having a thickness of 20 μm and having a concentration of 10 ¹⁵ to ^{10 16} cm ^-3 was formed by epitaxial vapor deposition (d ). Next, this n-type cathode region 1
An n ⁺ -type cathode region 115 containing phosphorus as an impurity and having a surface concentration of about 10 ²⁰ cm ^-3 and a thickness of about 8 μm was formed from the exposed surface of No. 16 by selective diffusion (e). this
The n ⁺ -type cathode region 115 is configured to include a portion (thyristor region) where the p-type buried gate region 113 is present therebelow and a portion (diode region) where the p-type buried gate region 113 is not present. Thereafter, the n-type cathode region 116 was removed by etching to expose a portion of the p-type buried gate region, thereby forming a recess 118 (f). In order to make good ohmic contact of the gate electrode to a part of this exposed p-type buried gate region, a p ⁺ -type gate region 11 with a thickness of approximately 3 μm is provided.
4 was formed by selective diffusion method (g). Note that in the explanation so far, for the sake of simplicity, the oxide film formed as a semiconductor during the diffusion process has been omitted.

Finally, an anode electrode 200 made of tungsten or the like is bonded to the p ⁺ type anode region 111 using a brazing material such as aluminum-antimony, and the exposed portions of the n ⁺ type cathode region 115 and the p ⁺ type gate region 114 are etched using a photoetching method. Therefore, a metal such as aluminum was deposited to form a gate electrode 300 and a cathode electrode 400. The portions of the main surface of the semiconductor substrate that are not covered with the above-mentioned electrodes are covered with a SiO ₂ film 500 (h). When measured after completion, the thickness of the gate region 113 was approximately 40 μm.
The mutual spacing d was approximately 6 μm.

An important point in the above manufacturing method is that prior to the diffusion of the p-type gate region 113, the p-type anode region 1 is
The point is that 11 diffusions are being carried out. The distance d between the p-type gate regions 113 is an important value in determining the switching characteristics of this type of semiconductor device, and must be precisely controlled in order to obtain the desired characteristics. However, if these steps were reversed, the above-mentioned distance d would be likely to vary because a long heat treatment would be required to form the p ⁺ -type anode region 111 after the formation of the p-type gate region 113. Note that the p ⁺ type anode region 114 and
The heat treatment time when forming the n ⁺ type cathode region 115 is relatively short because these regions are thin, at most several μm.
The effect on the spacing d mentioned above can be ignored.

According to experiments by the present inventors, when the manufacturing method of this embodiment described above is followed, the variation in the distance d is d = 6 μm.
It was about 10% of the design value, but it was 30% when the p ⁺ type anode region 111 was formed later.

Effects similar to those obtained by the manufacturing method of the embodiment of the present invention described above can also be obtained by the following manufacturing method. That is, for example, an n-type silicon substrate is prepared, and a p-type gate region 113 and an n-type cathode region 11 are formed on one main surface side of the silicon substrate as shown in FIG.
6. n ⁺ type cathode region 115 and recess 118
form. Next, a p ⁺ -type semiconductor layer of the same thickness (several μm) is formed selectively on the exposed portion of the p-type gate region 113 at the bottom of the recess 118 and simultaneously over the entire other main surface of the silicon substrate by a diffusion method. do. The p ⁺ -type semiconductor layer at the bottom of the recess 118 is the p ⁺ -type gate region 114 , and the p ⁺ -type semiconductor layer at the other main surface is the p ⁺ -type anode region 111 .

If this manufacturing method is followed, the following effects will be obtained in addition to the above-mentioned effects. Since the first p ⁺ type anode region is formed simultaneously with the p ⁺ type gate region, the manufacturing process of the semiconductor device is simplified. Since the thickness of the second p ⁺ type anode region is as thin as that of the p ⁺ type gate region, it has the effect of reducing the forward voltage drop of the semiconductor device. That is, the p ⁺ type anode region 11
1 is thin, the majority carrier concentration at the portion of the p ⁺ type anode region 111 in contact with the anode electrode 200 maintains approximately a thermal equilibrium value, so that the majority carrier concentration gradient within the p ⁺ type anode region 111 becomes large. Therefore, the diffusion current becomes large at a low junction potential, and the forward voltage drop becomes small without impairing other electrical characteristics.

Furthermore, as will be described later, when replacing part of the p ⁺ type anode region with an n ⁺ type semiconductor region to increase speed, the n ⁺ type semiconductor region is replaced with the formation of the n ⁺ type cathode region shown in FIG. 5e. It is possible to do both at the same time. In this way, the manufacturing process can be further simplified and increased in speed.

Next, the effects of the semiconductor device of this embodiment will be specifically explained. When the semiconductor device shown in Fig. 2 is manufactured by the manufacturing method shown in Fig. 5, the breakdown voltage between the gate and cathode is approximately 150V. There was no decrease at all. On the other hand, in the semiconductor device illustrated in FIG. 1, the impurity concentration of each semiconductor region,
When the dimensions were made approximately the same, the withstand voltage between the gate and cathode was approximately 70V.

It should be noted that in each of the above-described embodiments, the conductivity type of each semiconductor region is not to be fixed, and it is clear that p and n may be appropriately exchanged as necessary. In particular, speeding up can be achieved by making at least the portion of the anode region included in the projection part formed by projecting the gate electrode onto the anode region the same conductivity type as the base region (Japanese Patent Application No.
(See No. 86021). Further, although the present invention is particularly effective in field effect thyristors, it can also be applied to field effect transistors that require a similar gate structure.

Furthermore, in the manufacturing method of the embodiment described above, the p ⁺ type anode region 111 and the p type gate region 113 may be formed at the same time, and in this case there is an advantage that the manufacturing process is simplified.

As explained in detail above, the present invention
This is effective in improving the cathode-to-cathode breakdown voltage and obtaining a field-effect semiconductor device with excellent uniformity.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing one process of manufacturing an example of a conventional field effect thyristor, Fig. 2 is a sectional view showing a field effect thyristor according to an embodiment of the present invention, and Fig. 3 is an embodiment of the present invention. FIG. 4 is a cross-sectional view of a main part of a field-effect thyristor according to another embodiment of the present invention, and FIG. 5 is a manufacturing process of a field-effect thyristor according to an embodiment of the present invention. FIG. 100... Semiconductor substrate, 111... P ⁺ type anode region, 112... N ^- type base region, 113
... p type gate region, 114 ... p ⁺ type gate region, 115 ... n ⁺ type gate region, 116 ... n
type cathode region, 200... anode electrode, 30
0...gate electrode, 400...cathode electrode.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate of one conductivity type having a pair of main surfaces and a plurality of grooves formed on one main surface, and a semiconductor substrate formed at the top of a mesa formed between adjacent grooves of the semiconductor substrate. a first semiconductor region of one conductivity type which has an impurity concentration higher than that of the semiconductor substrate; The other conductive portion extends until it is included in a projected portion formed by projecting the first semiconductor region onto the other main surface of the semiconductor, and forms a p-n junction with the semiconductor substrate such that the exposed end has a positive bevel. a third semiconductor region exposed on the other main surface of the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate;
between a pair of main electrodes formed on the exposed surface of the semiconductor region and one of the pair of main electrodes formed on the surface of the second semiconductor region exposed at the bottom of the groove, the semiconductor substrate and the second semiconductor and a control electrode that controls the main current flowing between the pair of main electrodes by applying a voltage that reverse biases a pn junction formed between the semiconductor substrate and the semiconductor substrate to form a depletion layer within the semiconductor substrate. A semiconductor device characterized by: 2. In claim 1, at least a portion of the third semiconductor region included in a projection portion formed by projecting the first semiconductor region onto the other main surface of the semiconductor substrate is of the other conductivity type. A semiconductor device characterized by being a semiconductor. 3 A step of diffusing an impurity imparting the other conductivity type from one main surface of a semiconductor substrate of one conductivity type having a pair of main surfaces to form a high impurity concentration region of the other conductivity type, and simultaneously with or subsequent to said step. selectively diffusing impurities imparting the other conductivity type from the other main surface of the semiconductor substrate to form a gate region of the other conductivity type; a step of depositing an epitaxial semiconductor layer of a type, from an exposed main surface of the epitaxial semiconductor layer of one conductivity type to a gate region of the other conductivity type, and forming an epitaxial semiconductor layer between the epitaxial semiconductor layer and the gate region; pn
1. A method of manufacturing a semiconductor device, comprising at least the step of forming a plurality of grooves such that a junction is exposed with a regular bevel on the side surface thereof.