JPS634680A - Electrostatic induction type semiconductor device - Google Patents
Electrostatic induction type semiconductor deviceInfo
- Publication number
- JPS634680A JPS634680A JP14882786A JP14882786A JPS634680A JP S634680 A JPS634680 A JP S634680A JP 14882786 A JP14882786 A JP 14882786A JP 14882786 A JP14882786 A JP 14882786A JP S634680 A JPS634680 A JP S634680A
- Authority
- JP
- Japan
- Prior art keywords
- region
- gate
- cathode
- gate regions
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 37
- 230000006698 induction Effects 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000003068 static effect Effects 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000000034 method Methods 0.000 abstract description 5
- 230000003321 amplification Effects 0.000 abstract description 3
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 238000004904 shortening Methods 0.000 abstract 1
- 230000003313 weakening effect Effects 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
- H01L29/7392—Gated diode structures with PN junction gate, e.g. field controlled thyristors (FCTh), static induction thyristors (SITh)
Abstract
Description
【発明の詳細な説明】 〔技術分野〕 この発明は静電誘導形半導体装置に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to an electrostatic induction type semiconductor device.
静電誘導形半導体装置のひとつに静電誘導形サイリスク
がある。第３図は、通常、表面ゲート形と称される従来
の静電誘導形サイリスクの断面構造をあられしたもので
ある。この静電誘導形サイリスクは半導体基板１′の一
側にカソード領域（Ｎ゛領域４′とゲート領域（Ｐ″領
域５′を備えていて、他側にアノード領域（Ｐ”領域）
３′を備え、そして、カソード領域４′・アノード領域
３′間にＮ−半界体領域の高比抵抗領域（ベース領域）
２′を備えている。アノード領域３′にはアノード電極
１０′が設けられている。カソード領域４′とゲート領
域５′には、ＳｉＯ□膜（二酸化ケイ素膜）１３′に開
けられた窓を介して、カソード電極１１′とゲート電極
１２′が設けられている。One of the electrostatic induction type semiconductor devices is the electrostatic induction type SIRISK. FIG. 3 shows a cross-sectional structure of a conventional electrostatic induction type cell, which is usually referred to as a surface gate type. This electrostatic induction type silice has a cathode region (N' region 4' and a gate region (P" region 5') on one side of the semiconductor substrate 1', and an anode region (P" region) on the other side.
3', and a high resistivity region (base region) of an N-semifield region between the cathode region 4' and the anode region 3'.
2'. An anode electrode 10' is provided in the anode region 3'. A cathode electrode 11' and a gate electrode 12' are provided in the cathode region 4' and the gate region 5' through a window formed in the SiO□ film (silicon dioxide film) 13'.
第３図の静電誘導形サイリスクの動作機構を、サイリス
クがゲート領域５′に電圧が印加されていない状態でア
ノード・カソード間が導通ずるいわゆるノーマリイオン
・タイプのものである場合、を例にとって説明する。The operating mechanism of the electrostatic induction type SIRISK shown in Fig. 3 is shown as an example in the case where the SIRISK is of the so-called normally ion type in which conduction occurs between the anode and cathode when no voltage is applied to the gate region 5'. I will explain it to you.
まず、通電状態から阻止状態にするいわゆるターンオフ
機構について述べる。First, a so-called turn-off mechanism that changes the current from the energized state to the blocked state will be described.
通電状態では、高比抵抗領域２′内にカソード領域４′
から注入された電子、および、アノード領域３′から注
入された正孔が充満している。ゲ−ト電極１２′に電圧
が加えられて、ゲート領域５′とカソード領域４′が逆
バイアスとなると、正札はゲート領域５′に吸い出され
、電子はカソード領域４′に吸い出されると同時に、ゲ
ートＨ域５′とカソード領域４′の間に空乏層が急速に
拡がる。この空乏層によって、主電流通路がふさがれる
こととなる。その後、空乏層とアノード領域３′の間に
残留する正孔が消滅していくに従って、主電流も減少し
てゆき阻止状態となる。In the energized state, a cathode region 4' is formed within the high resistivity region 2'.
It is filled with electrons injected from the anode region 3' and holes injected from the anode region 3'. When a voltage is applied to the gate electrode 12' and the gate region 5' and cathode region 4' are reverse biased, the genuine tag is sucked out to the gate region 5' and the electrons are sucked out to the cathode region 4'. At the same time, a depletion layer rapidly expands between the gate H region 5' and the cathode region 4'. This depletion layer blocks the main current path. Thereafter, as the holes remaining between the depletion layer and the anode region 3' disappear, the main current also decreases and a blocking state is reached.
つぎに、阻止状態から通電状態にするいわゆるターンオ
ン機構について述べる。Next, a so-called turn-on mechanism for changing the state from the blocked state to the energized state will be described.
ゲート領域５′とカソード領域４′を逆バイアスとして
いた電圧を除去する。そうすると、ゲート領域５′がら
空乏層内へ電子が注入され、空乏層内のイオン化したド
ナーが電子によって中和される。ドナーの中和によって
空乏層は縮小されて、アノード領域３′から注入される
正孔とともに伝導度変調が起こり高比抵抗領域領域２′
内に低抵抗領域が形成されるので、この低抵抗領域を通
して主電流通電が開始する。The voltage that reverse biased the gate region 5' and cathode region 4' is removed. Then, electrons are injected into the depletion layer from the gate region 5', and the ionized donors in the depletion layer are neutralized by the electrons. The depletion layer is reduced by the neutralization of the donors, and conductivity modulation occurs together with the holes injected from the anode region 3', forming the high resistivity region 2'.
Since a low-resistance region is formed within, the main current begins to flow through this low-resistance region.
しかしながら、上記のサイリスクではいくつかの問題が
ある。However, the above-mentioned Cyrisk has several problems.
ゲート・カソード間耐電圧は、高比抵抗領域２′、カソ
ード領域４′、および、ゲート領域５′における不純物
濃度がほぼ一定であると、第２図に示したゲート・カソ
ード間距離ＩＧＫに依存する。耐電圧をあげるため、ｌ
ＧＫを長くすると、ゲート領域４′による静電誘導作用
が弱まり、主電流の断続制御が困難となるという問題が
ある。When the impurity concentration in the high resistivity region 2', cathode region 4', and gate region 5' is approximately constant, the gate-cathode withstand voltage depends on the gate-cathode distance IGK shown in Fig. 2. do. To increase the withstand voltage, l
When GK is made long, the electrostatic induction effect by the gate region 4' is weakened, and there is a problem in that it becomes difficult to control the main current on and off.
ひとつのチャンネルを形成するのに最低限必要な基板の
長さは、第２図にみるように、ゲート電極幅ＩＧ （５
μｍ）＋ゲート電極・カン−１１４Ｍ幅Ｉｔｓ （３
μｍ）十カソード電極幅ｆｆｉｇ（９，ｕｍ）＋ゲート
電極・カソード電極幅７！ｓ （３μｍ）＝２０１１ｍ
である。なお、ゲート領域５′とカソード領域４′形成
のために５ｉ０２膜に開ける窓の最低限必要な大きさは
、それぞれ２μｍ（１９）と３μｍ （Ａｋ ）である
。第３図の従来の構造では製造プロセスなどからくる制
約上、上記の必要寸法を縮小する（必要なチップ面積を
縮める）ことが困難である。As shown in Figure 2, the minimum length of the substrate required to form one channel is the gate electrode width IG (5
μm) + gate electrode/can - 114M width Its (3
μm) 10 cathode electrode width ffig (9, um) + gate electrode/cathode electrode width 7! s (3μm)=2011m
It is. Note that the minimum required sizes of windows to be opened in the 5i02 film for forming the gate region 5' and cathode region 4' are 2 μm (19) and 3 μm (Ak), respectively. In the conventional structure shown in FIG. 3, it is difficult to reduce the above-mentioned required dimensions (reduce the required chip area) due to constraints caused by manufacturing processes and the like.
さらに、ゲート領域５′の抵抗値が低減すると、正孔の
吸い出し時間を短縮することができるが、第３図の構造
では、ゲーＨＪＴ域５′の拡散深さを９μｍ程度と深く
する必要があり、拡散で不純物濃度が低下するため、ゲ
ート領域５′の抵抗値を小さくすることができない。Furthermore, if the resistance value of the gate region 5' is reduced, the hole extraction time can be shortened, but in the structure shown in FIG. 3, it is necessary to increase the diffusion depth of the gate HJT region 5' to about 9 μm. However, since the impurity concentration decreases due to diffusion, the resistance value of the gate region 5' cannot be reduced.
この発明は、上記の事情に鑑み、ゲート・カソード間の
耐電圧が高く、ゲート領域の抵抗値も小さく、しかも、
必要なチップ面積も少なくすることもできる構造の静電
誘導形半導体装置を提供することを目的とする。In view of the above circumstances, this invention has a high withstand voltage between the gate and cathode, a low resistance value in the gate region, and
It is an object of the present invention to provide an electrostatic induction type semiconductor device having a structure that can also reduce the required chip area.
前記目的を達成するため、この発明は、基板の一側にカ
ソード領域とゲート領域を備えている静電誘導形半導体
装置において、半導体層表面に前記ゲート領域が形成さ
れているとともに、前記半導体層表面に積層された半導
体基板と同じ導電型の半導体層表面に前記カソード領域
が形成されていることを特徴とする静電誘導形半導体装
置を要旨とする。To achieve the above object, the present invention provides a static induction type semiconductor device including a cathode region and a gate region on one side of a substrate, in which the gate region is formed on the surface of the semiconductor layer, and the gate region is formed on the surface of the semiconductor layer. The gist of the present invention is an electrostatic induction type semiconductor device characterized in that the cathode region is formed on the surface of a semiconductor layer of the same conductivity type as a semiconductor substrate laminated on the surface.
以下、この発明にかかる静電誘導形半導体装置（以下、
「サイリスク」と言う）を、一実施例である静電誘厚形
サイリスクの製造途中と完成状態における構造をあられ
す図面を参照しながら詳しく説明する。Hereinafter, the electrostatic induction type semiconductor device (hereinafter referred to as
The structure of an electrostatically dielectric thick type SIRISK, which is an example of the electrostatic dielectric SIRISK, during manufacturing and in a completed state will be explained in detail with reference to the accompanying drawings.
第１図は、この発明にかかるサイリスクの一実施例の断
面構造をあられしたものである。FIG. 1 shows a cross-sectional structure of an embodiment of the Cyrisk according to the present invention.
第２図（ａｌ〜（υは、それぞれ、サイリスクの主な製
造工程における断面構造を工程順にあられしたものであ
る。Figure 2 (al~(υ) shows the cross-sectional structure of the main manufacturing process of Cyrisk in order of process.
サイリスクは次のようにして製造する。まず、高比抵抗
領域２で必要とされる抵抗率を有するＮ型シリコン半導
体基板１を用意し、熱酸化法によって、両面に酸化膜を
形成する。Cyrisk is manufactured as follows. First, an N-type silicon semiconductor substrate 1 having a resistivity required for the high resistivity region 2 is prepared, and oxide films are formed on both surfaces by thermal oxidation.
下側（他側）の酸化膜を写真食刻処理法で除去しておい
て、不純物を拡散し、アノード領域（Ｐ゛層）３を形成
する。The lower (other side) oxide film is removed by photolithography, and impurities are diffused to form an anode region (P' layer) 3.
写真食刻処理法で、上側（−側）の酸化膜２０に窓２工
を開けて、不純物を拡散し、第２図（ａｌにみるように
、ゲーＨＩ域（Ｐ″領域５を形成する。Two windows are opened in the upper (-side) oxide film 20 using a photolithography process, and impurities are diffused to form a HI region (P'' region 5) as shown in FIG. 2 (al). .
つぎに、−旦、酸化膜２０を除去し、第２図（ｂ）にみ
るように、ＳｉＯ□膜２２膜上２体基板ｌの上側に形成
し、第２図（Ｃ）にみるように、やはり写真食刻処理法
でカソード領域形成のための窓２３を開ける。そして、
窓２３の個所に、第２図（ｄ）にみるように、所望の抵
抗率を有するＮ−層（半導体基板と同じ導電型の半導体
層）ｌａをエピタキシャル成長させる。このエピタキシ
ャル成長の際、ＳｉＯ□膜２２膜上２層はポリシリコン
層２４′となる。Ｎ−層１ａの厚みは所望のゲート・カ
ソード間耐電圧が得られる厚みとする。次にエピタキシ
ャル成長させたＮ−層ｌａ表面に不純−物を拡散して、
第２図ｆ１３１にみるように、不純物濃度が高いＮ・層
、すなわちカソード領域４を形成し、さらにＳｉｎ、膜
２５を形成する。Next, the oxide film 20 is removed, and as shown in FIG. 2(b), a SiO□ film 22 is formed on the upper side of the two-layer substrate l, as shown in FIG. 2(c). , the window 23 for forming the cathode region is also opened using a photolithography process. and,
At the location of the window 23, as shown in FIG. 2(d), an N- layer (semiconductor layer of the same conductivity type as the semiconductor substrate) la having a desired resistivity is epitaxially grown. During this epitaxial growth, the two layers above the SiO□ film 22 become a polysilicon layer 24'. The thickness of the N- layer 1a is set to a thickness that allows a desired gate-cathode withstand voltage to be obtained. Next, impurities are diffused onto the surface of the epitaxially grown N-layer la.
As shown in FIG. 2 f131, an N layer with a high impurity concentration, that is, a cathode region 4, is formed, and then a Sin film 25 is formed.
この後、第２図（ｆ）にみるように、写真食刻処理法に
て、ポリシリコンＮ２４′上のＳ ｉ Ｏｔ ［９２５
を除去しておいてから、そのまま、ＣＦ４ガスを用いた
ドライエツチングでポリシリコン層２４′を選択的にエ
ツチングする。After that, as shown in FIG. 2(f), S i Ot [925
After removing the polysilicon layer 24', the polysilicon layer 24' is selectively etched by dry etching using CF4 gas.
つづいて、第２図（幻にみるように、エピタキシャル成
長させたＮ−層１ａの側面も覆うようにして絶縁膜２６
を形成する。絶縁膜２６としては５ｉ０２膜や窒化膜（
例えば、ＳｔＮ膜）等を使う。そして、写真食刻処理法
でＳｉｎ、膜２２．２５と絶縁膜２６を除去して、第２
図（ｈｌにみるように、電極形成用の窓２７．２８を開
ける。この窓２７．２８のところへアルミニウム等の金
属材料を用いて、第２図（ｉ）にみるように、カソード
電極１１とゲート電極１２を形成する。なお、アノード
ＨＭ３には、第１図にみるように、通常の方法で、アノ
ード電極１０が形成されている。Continuing, as shown in FIG.
form. As the insulating film 26, a 5i02 film or a nitride film (
For example, a StN film) or the like is used. Then, the Sin film 22, 25 and the insulating film 26 are removed by photolithography, and the second
As shown in FIG. A gate electrode 12 is formed on the anode HM3.As shown in FIG. 1, an anode electrode 10 is formed on the anode HM3 by a conventional method.
このように上記のサイリスクでは、半導体基板表面に積
み上げられた基板と同じ導電型半専体層があって、ゲー
ト領域は半導体基板表面に形成されていて、カソード領
域は半ｍ体層表面に形成されている。つまり、ゲート領
域とカソード領域は段差がある構造となっているのであ
る。この構造を備えているサイリスクは以下のような利
点を有する。In this way, in the above-mentioned SIRISK, there is a semi-dedicated layer of the same conductivity type as the substrate stacked on the surface of the semiconductor substrate, the gate region is formed on the surface of the semiconductor substrate, and the cathode region is formed on the surface of the semi-conductive layer. has been done. In other words, the structure has a step difference between the gate region and the cathode region. Cyrisk with this structure has the following advantages.
ゲート・カソード間の耐電圧を決める寸法ｌＧＫ′は、
Ｎ−層１ａの厚みを増すことによって容易に大きくでき
る。その際、高比抵抗領域２とゲート領域５の関係は何
ら変わらないので、ゲート領域５の静電ＢＡ ４作用が
弱まるようなこともほとんどない。The dimension lGK' that determines the withstand voltage between the gate and cathode is
It can be easily increased by increasing the thickness of the N- layer 1a. At this time, since the relationship between the high resistivity region 2 and the gate region 5 does not change at all, the electrostatic BA 4 effect of the gate region 5 is hardly weakened.
ゲート領域５の拡散深さが浅（でも、ゲート領域５を高
比抵抗領域２内に充分位置させることができるので、ゲ
ート作用を損なうことなくゲート領域５の抵抗を低くす
ることができる。そのため、ターンオフ時間を短くでき
る。Although the diffusion depth of the gate region 5 is shallow (although the gate region 5 can be located sufficiently within the high resistivity region 2, the resistance of the gate region 5 can be lowered without impairing the gate function. , the turn-off time can be shortened.
ゲート領域５の拡散深さが浅いと、電圧増幅率も増大す
る。なぜなら、電圧増幅率μはチャンネル幅Ｗ ｃ ／
拡散深さＸｊに比例することが経験的に知られているか
らである。When the diffusion depth of gate region 5 is shallow, the voltage amplification factor also increases. This is because the voltage amplification factor μ is the channel width W c /
This is because it is empirically known that it is proportional to the diffusion depth Xj.
カソード領域４とゲート領域５の横方向間隙が不要とな
るので、チップ面、積が同じであれば、写真食刻処理法
の窓開は寸法を広くとることができるので、製作しやす
い。また、従来の最小限の窓開は寸法で製造すれば、チ
ップ面積を縮小できることとなる。Since there is no need for a lateral gap between the cathode region 4 and the gate region 5, if the chip surface and area are the same, the window opening in the photolithography process can be made wider, making it easier to manufacture. Furthermore, if the conventional minimum window opening size is manufactured, the chip area can be reduced.
カソード電極１１とゲート電極１２が同じ面上にないの
で電極層を積み上げて厚みを増しやすい。そのため、電
極抵抗値を低くできるので、アノード・カソード間電流
（主電流）容量が増加するこの発明は、上記の実施例に
限定されない。各工程で用いられる加工方法や材料を同
様の５働きをする他のものであっても良い。静電誘導形
半導体装置も、サイリスクに限らず、静電誘導形トラン
ジスタであってもよい。この場合には、カソード領域は
ソース領域と称される。Since the cathode electrode 11 and the gate electrode 12 are not on the same plane, it is easy to stack the electrode layers to increase the thickness. Therefore, the present invention, in which the electrode resistance value can be lowered and the anode-cathode current (main current) capacity increases, is not limited to the above embodiments. The processing methods and materials used in each step may be other materials that perform the same five functions. The electrostatic induction type semiconductor device is not limited to SIRISK, but may also be an electrostatic induction type transistor. In this case, the cathode region is referred to as the source region.
以上に詳述したように、この発明にかかる静電誘導形半
導体装置は、半導体基板表面にゲート領域が形成されて
いるとともに、半導体基板表面に積層された半導体基板
と同じ導電型の半導体装置面にカソード領域が形成され
ている構造となっている。そのため、静電誘導半導体装
置が、ゲート・カソード間の耐電圧特性、スイッチング
速度特性、電流容量特性や必要なチップ面積の点で優れ
たものとなる。As detailed above, the electrostatic induction type semiconductor device according to the present invention has a gate region formed on the surface of the semiconductor substrate, and a semiconductor device surface of the same conductivity type as the semiconductor substrate laminated on the surface of the semiconductor substrate. It has a structure in which a cathode region is formed at the top. Therefore, the electrostatic induction semiconductor device has excellent gate-cathode withstand voltage characteristics, switching speed characteristics, current capacity characteristics, and required chip area.
第１図は、この発明の一例であるサイリスクの断面図、
第２図（ａｌ〜（１）は、このサイリスクを製造する際
の各工程における断面図、第３図は、従来のサイリスク
の断面図、第４図は、この従来のサイリスクの部分断面
図である。
■・・・半導体基板 １ａ・・・Ｎ−層（半導体基板
と同じ導電型の半導体層） ４・・・カソード領域５
・・・ゲート領域
代理人 弁理士 松 本 武 彦
第２図
５ ｌ
第３図
第４図
５” ４゛FIG. 1 is a cross-sectional view of Cyrisk, which is an example of the present invention.
Figure 2 (al~(1)) is a cross-sectional view of each step in manufacturing this Cyrisk, Figure 3 is a cross-sectional view of a conventional Cyrisk, and Figure 4 is a partial sectional view of this conventional Cyrisk. ■... Semiconductor substrate 1a... N- layer (semiconductor layer of the same conductivity type as the semiconductor substrate) 4... Cathode region 5
...Gate area agent Patent attorney Takehiko Matsumoto Figure 2 5 l Figure 3 Figure 4 5” 4゛
Claims (1)
いる静電誘導形半導体装置において、半導体基板表面に
前記ゲート領域が形成されているとともに、前記半導体
基板表面に積層された半導体基板と同じ導電型の半導体
層表面に前記カソード領域が形成されていることを特徴
とする静電誘導形半導体装置。(1) In a static induction type semiconductor device having a cathode region and a gate region on one side of a substrate, the gate region is formed on the surface of the semiconductor substrate, and a semiconductor substrate laminated on the surface of the semiconductor substrate An electrostatic induction semiconductor device characterized in that the cathode region is formed on the surface of a semiconductor layer of the same conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14882786A JPS634680A (en) | 1986-06-24 | 1986-06-24 | Electrostatic induction type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14882786A JPS634680A (en) | 1986-06-24 | 1986-06-24 | Electrostatic induction type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS634680A true JPS634680A (en) | 1988-01-09 |
Family
ID=15461615
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14882786A Pending JPS634680A (en) | 1986-06-24 | 1986-06-24 | Electrostatic induction type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS634680A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2645348A1 (en) * | 1989-03-28 | 1990-10-05 | Matsushita Electric Works Ltd | PROCESS FOR THE MANUFACTURE OF A STATICALLY INDUCED TYPE SEMICONDUCTOR DEVICE AND DEVICE OBTAINED IN THIS WAY |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS562667A (en) * | 1979-06-20 | 1981-01-12 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS57173974A (en) * | 1981-04-20 | 1982-10-26 | Hitachi Ltd | Semiconductor device |
| JPS60955A (en) * | 1983-06-18 | 1985-01-07 | 泉株式会社 | Anti-contamination processing method of protective sheet-shaped article for construction work |
-
1986
- 1986-06-24 JP JP14882786A patent/JPS634680A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS562667A (en) * | 1979-06-20 | 1981-01-12 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS57173974A (en) * | 1981-04-20 | 1982-10-26 | Hitachi Ltd | Semiconductor device |
| JPS60955A (en) * | 1983-06-18 | 1985-01-07 | 泉株式会社 | Anti-contamination processing method of protective sheet-shaped article for construction work |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2645348A1 (en) * | 1989-03-28 | 1990-10-05 | Matsushita Electric Works Ltd | PROCESS FOR THE MANUFACTURE OF A STATICALLY INDUCED TYPE SEMICONDUCTOR DEVICE AND DEVICE OBTAINED IN THIS WAY |
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