JPS599926B2 - Nrz/2相マイクロコンピユ−タ直列通信論理装置 - Google Patents
Nrz/2相マイクロコンピユ−タ直列通信論理装置Info
- Publication number
- JPS599926B2 JPS599926B2 JP54114049A JP11404979A JPS599926B2 JP S599926 B2 JPS599926 B2 JP S599926B2 JP 54114049 A JP54114049 A JP 54114049A JP 11404979 A JP11404979 A JP 11404979A JP S599926 B2 JPS599926 B2 JP S599926B2
- Authority
- JP
- Japan
- Prior art keywords
- bit
- data
- serial
- register
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Signal Processing (AREA)
- Mathematical Physics (AREA)
- Computer Networks & Wireless Communication (AREA)
- General Physics & Mathematics (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Computer And Data Communications (AREA)
- Information Transfer Systems (AREA)
- Dc Digital Transmission (AREA)
- Microcomputers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US000000939743 | 1978-09-05 | ||
| US000000939744 | 1978-09-05 | ||
| US000000939742 | 1978-09-05 | ||
| US05/939,742 US4361876A (en) | 1978-09-05 | 1978-09-05 | Microcomputer with logic for selectively disabling serial communications |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5569833A JPS5569833A (en) | 1980-05-26 |
| JPS599926B2 true JPS599926B2 (ja) | 1984-03-06 |
Family
ID=25473633
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP54114049A Expired JPS599926B2 (ja) | 1978-09-05 | 1979-09-04 | Nrz/2相マイクロコンピユ−タ直列通信論理装置 |
| JP58138644A Pending JPS5962253A (ja) | 1978-09-05 | 1983-07-28 | デジタル回路 |
| JP58138643A Granted JPS5962938A (ja) | 1978-09-05 | 1983-07-28 | マイクロコンピユ−タ |
Family Applications After (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58138644A Pending JPS5962253A (ja) | 1978-09-05 | 1983-07-28 | デジタル回路 |
| JP58138643A Granted JPS5962938A (ja) | 1978-09-05 | 1983-07-28 | マイクロコンピユ−タ |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US4361876A (enExample) |
| JP (3) | JPS599926B2 (enExample) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4369516A (en) * | 1980-09-15 | 1983-01-18 | Motorola, Inc. | Self-clocking data transmission system |
| DE3119117C2 (de) * | 1981-05-14 | 1993-10-21 | Bosch Gmbh Robert | Vorrichtung zum Rücksetzen von Recheneinrichtungen |
| JPS58115547A (ja) * | 1981-12-29 | 1983-07-09 | Fujitsu Ltd | マイクロプロセツサの動作モ−ド設定方式 |
| US4626985A (en) * | 1982-12-30 | 1986-12-02 | Thomson Components - Mostek Corporation | Single-chip microcomputer with internal time-multiplexed address/data/interrupt bus |
| US4686528A (en) * | 1984-01-31 | 1987-08-11 | Motorola, Inc. | Method of encoding and decoding data signals |
| JPS60216653A (ja) * | 1984-03-28 | 1985-10-30 | Sumitomo Electric Ind Ltd | 半導体集積回路 |
| JP2633852B2 (ja) * | 1987-06-10 | 1997-07-23 | 株式会社日立製作所 | データ処理装置 |
| JPH0225955A (ja) * | 1988-07-14 | 1990-01-29 | Nec Corp | シングルチップマイクロコンピュータ |
| JPH0275091A (ja) * | 1988-09-09 | 1990-03-14 | Takayuki Murata | 情報表示体 |
| US5218683A (en) * | 1989-10-30 | 1993-06-08 | Hayes Microcomputer Products, Inc. | Method and apparatus for concealing the enablement of a device by modifying a status word |
| US5898890A (en) * | 1992-03-27 | 1999-04-27 | Ast Research, Inc. | Method for transferring data between devices by generating a strobe pulse and clamping a clock line |
| CA2192426C (en) * | 1996-01-03 | 2000-08-01 | Richard Ng | Bidirectional voltage translator |
| US6324592B1 (en) | 1997-02-25 | 2001-11-27 | Keystone Aerospace | Apparatus and method for a mobile computer architecture and input/output management system |
| DE19848211B4 (de) * | 1998-10-20 | 2004-02-05 | Honeywell Ag | Datenübertragungsverfahren |
| US6522944B2 (en) | 2000-04-27 | 2003-02-18 | Rockwell Automation Technologies, Inc. | Driver board control system for modular conveyor with address-based network for inter-conveyor communication |
| US6701214B1 (en) | 2000-04-27 | 2004-03-02 | Rockwell Automation Technologies, Inc. | Driver board control system for modular conveyer with address-based network for inter-conveyor communication |
| US6745232B1 (en) | 2000-08-23 | 2004-06-01 | Rockwell Automation Technologies, Inc. | Strobed synchronization providing diagnostics in a distributed system |
| US6701462B1 (en) | 2000-05-19 | 2004-03-02 | Rockwell Automation Technologies, Inc. | Situational aware output configuration and execution |
| US6591311B1 (en) | 2000-04-27 | 2003-07-08 | Rockwell Automation Technologies, Inc. | Method and system for selecting controller output value source |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3242467A (en) * | 1960-06-07 | 1966-03-22 | Ibm | Temporary storage register |
| US3286240A (en) * | 1962-12-31 | 1966-11-15 | Ibm | Channel status checking and switching system |
| US3480914A (en) * | 1967-01-03 | 1969-11-25 | Ibm | Control mechanism for a multi-processor computing system |
| US3470542A (en) * | 1967-03-17 | 1969-09-30 | Wang Laboratories | Modular system design |
| US3706974A (en) * | 1971-10-27 | 1972-12-19 | Ibm | Interface multiplexer |
| US3813651A (en) * | 1971-12-29 | 1974-05-28 | Tokyo Shibaura Electric Co | Data processing system |
| US3742148A (en) * | 1972-03-01 | 1973-06-26 | K Ledeen | Multiplexing system |
| JPS5330446B2 (enExample) * | 1973-05-12 | 1978-08-26 | ||
| JPS5444161B2 (enExample) * | 1973-09-08 | 1979-12-24 | ||
| US3978455A (en) * | 1974-09-09 | 1976-08-31 | Gte Automatic Electric Laboratories Incorporated | I/o structure for microprocessor implemented systems |
| JPS5193139A (enExample) * | 1975-02-12 | 1976-08-16 | ||
| US3982195A (en) * | 1975-05-29 | 1976-09-21 | Teletype Corporation | Method and apparatus for decoding diphase signals |
| JPS5837585B2 (ja) * | 1975-09-30 | 1983-08-17 | 株式会社東芝 | ケイサンキソウチ |
| US4038644A (en) * | 1975-11-19 | 1977-07-26 | Ncr Corporation | Destination selection apparatus for a bus oriented computer system |
| JPS5296836A (en) * | 1976-02-10 | 1977-08-15 | Toshiba Corp | Multiplex data processing system |
| US4065809A (en) * | 1976-05-27 | 1977-12-27 | Tokyo Shibaura Electric Co., Ltd. | Multi-processing system for controlling microcomputers and memories |
| US4096569A (en) * | 1976-12-27 | 1978-06-20 | Honeywell Information Systems Inc. | Data processing system having distributed priority network with logic for deactivating information transfer requests |
| US4168532A (en) * | 1977-02-24 | 1979-09-18 | The United States Of America As Represented By The Secretary Of The Air Force | Multimode data distribution and control apparatus |
| US4149242A (en) * | 1977-05-06 | 1979-04-10 | Bell Telephone Laboratories, Incorporated | Data interface apparatus for multiple sequential processors |
-
1978
- 1978-09-05 US US05/939,742 patent/US4361876A/en not_active Expired - Lifetime
-
1979
- 1979-09-04 JP JP54114049A patent/JPS599926B2/ja not_active Expired
-
1983
- 1983-07-28 JP JP58138644A patent/JPS5962253A/ja active Pending
- 1983-07-28 JP JP58138643A patent/JPS5962938A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5962938A (ja) | 1984-04-10 |
| JPS5569833A (en) | 1980-05-26 |
| US4361876A (en) | 1982-11-30 |
| JPS6410862B2 (enExample) | 1989-02-22 |
| JPS5962253A (ja) | 1984-04-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS599926B2 (ja) | Nrz/2相マイクロコンピユ−タ直列通信論理装置 | |
| EP1629392B1 (en) | Memory module architecture daisy chain topology detects and reports presence of outer memory module to inner module | |
| JP2821552B2 (ja) | 2経路データ転送装置 | |
| US7328399B2 (en) | Synchronous serial data communication bus | |
| US5276807A (en) | Bus interface synchronization circuitry for reducing time between successive data transmission in a system using an asynchronous handshaking | |
| US4841440A (en) | Control processor for controlling a peripheral unit | |
| US5140680A (en) | Method and apparatus for self-timed digital data transfer and bus arbitration | |
| EP0258872B1 (en) | Serial data transfer system | |
| US7702832B2 (en) | Low power and low pin count bi-directional dual data rate device interconnect interface | |
| EP0380856A2 (en) | Method and apparatus for interfacing a system control unit for a multi-processor | |
| EP1629389A2 (en) | Memory channel with bit lane fail-over | |
| US20080046619A1 (en) | Simultaneous Transmissions Between Multiple Master Buses and Multiple Slave Buses | |
| EP1629394A2 (en) | Memory channel with unidrectional links | |
| EP1629393A2 (en) | Memory interface protocol for distinguishing status information from read data | |
| US4346452A (en) | NRZ/Biphase microcomputer serial communication logic | |
| US5687388A (en) | Scalable tree structured high speed input/output subsystem architecture | |
| US3921137A (en) | Semi static time division multiplex slot assignment | |
| US4222116A (en) | Digital logic for separating data and clock in Manchester-encoded data | |
| US5889959A (en) | Fast write initialization method and system for loading channel adapter microcode | |
| US4468737A (en) | Circuit for extending a multiplexed address and data bus to distant peripheral devices | |
| WO2005091544A1 (en) | Bit clock with embedded word clock boundary | |
| US4296477A (en) | Register device for transmission of data having two data ranks one of which receives data only when the other is full | |
| WO1996033464A1 (en) | Processing unit to clock interface | |
| WO2005091543A1 (en) | Architecture for bidirectional serializers and deserializer | |
| GB2029172A (en) | NRZ/biphase microcomputer serial communication logic |