JPS5998549A - Single in-line type semiconductor device - Google Patents

Single in-line type semiconductor device

Info

Publication number
JPS5998549A
JPS5998549A JP57207001A JP20700182A JPS5998549A JP S5998549 A JPS5998549 A JP S5998549A JP 57207001 A JP57207001 A JP 57207001A JP 20700182 A JP20700182 A JP 20700182A JP S5998549 A JPS5998549 A JP S5998549A
Authority
JP
Japan
Prior art keywords
semiconductor device
type semiconductor
leads
outer leads
dummy lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57207001A
Other languages
Japanese (ja)
Inventor
Yoshihiro Ishizuka
石塚　良博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP57207001A priority Critical patent/JPS5998549A/en
Publication of JPS5998549A publication Critical patent/JPS5998549A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To improve the reliability of a semiconductor device by forming a dummy lead in a direction opposite to the surface, from which outer leads are led, on inner leads which are disposed at the farthest position from the outer leads, thereby reducing variations in the characteristics of the device or in the electric characteristics. CONSTITUTION:A dummy lead which extend in a direction opposite to outer leads 12 is formed at inner leads 11 so that a contraction strain which occurs in a direction parallel to Y-Y' axis is balanced with that which occurs at outer leads side. In an SIL type semiconductor device which employs such a leadframe, the dummy lead becomes a buffer at the resin molding time and the subsequent stress receiving time to be balanced with the contraction strain, thereby reducing the variations in the characteristics of the device with reproducibility, i.e., enabling to control the stress applied to a chip under the manufacturing conditions.

Description

【発明の詳細な説明】 本発明はシングルインライン（以下、Ｓ工りと記す）形
半導体装置の組立に用いられるリードフレームの改良に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a lead frame used in the assembly of a single-in-line (hereinafter referred to as S-type) type semiconductor device.

一般にプラスチックパッケージにおける半導体装置では
樹脂の成形によるチップへの収縮歪がめシ、デバイスは
種々の影響を受けている。このチップに発生する応力は
アフターキーアー後にうける半田ディッピング等の熱サ
イクルにおいて変化しデバイスの特性を変動させる。特
にＳＩＬ形半導体装置においてはデエアルインライン（
以下、ＤＩＬと記す）形半導体装置と比較し熱サイクル
によるデバイスの特性あるいは集積回路としての電気的
特性の変動が大きいと言った問題があった。In general, semiconductor devices in plastic packages are subject to various influences such as shrinkage strain on the chip due to resin molding. The stress generated in this chip changes during thermal cycles such as solder dipping after after-keying, and changes the characteristics of the device. Especially in SIL type semiconductor devices, dair in-line (
Compared to semiconductor devices of the DIL type (hereinafter referred to as DIL), there is a problem in that the characteristics of the device or the electrical characteristics of the integrated circuit vary greatly due to thermal cycles.

上記のようなパッケージの相異による応力変動の差は収
縮歪の対称性によ如理解できる。一般にＤＩＬ形牛形体
導体装置チップに対してインナーリードが対称に配置さ
れ、収縮歪はチップのＸ軸、ｙ軸の両方に対し対称に生
ずるが、ＳＩＬ形半導体装置ではインナーリードの配置
は第１図に示す様に非対称になっておｊ９、ｘ−ｘ’軸
に平行な方向に生じる収縮歪はバランスをくずしている
。、　ＳＩＬ形半導体装置では熱サイクルによる収縮歪
のアンバランスによｊｊｌｌＤＩＬ形半導体装置と比較
して特性の変動を大きくしている。The difference in stress fluctuation due to the difference in packages as described above can be clearly understood from the symmetry of shrinkage strain. In general, the inner leads are arranged symmetrically with respect to the DIL-type bull-shaped conductor device chip, and shrinkage strain occurs symmetrically with respect to both the X-axis and the y-axis of the chip, but in the SIL-type semiconductor device, the inner leads are arranged symmetrically with respect to the chip. As shown in the figure, it is asymmetrical and the shrinkage strain occurring in the direction parallel to the j9, x-x' axis disrupts the balance. , SIL type semiconductor devices have larger fluctuations in characteristics compared to DIL type semiconductor devices due to unbalance of shrinkage strain caused by thermal cycles.

本発明は上記のようなＳＩＬ形半導体装置の問題を解決
するためになされたものであシ、その要点はアウターリ
ードに対し、最も離れた位置に配置されたインナーリー
ドに、アウターリードを取シ出している面に相対する方
向にダミーリードを設けることによυ、樹脂の成形によ
るチップへの収縮歪をチップに対し対称となるようにし
、熱サイクルによるデバイス特性の変動あるいは半導体
装置の電気的特性の変動の小さい信頼性の高い半導体装
置を得ることができる。The present invention was made in order to solve the problems of SIL type semiconductor devices as described above. By providing dummy leads in the direction opposite to the exposed surface, υ makes the shrinkage strain on the chip due to resin molding symmetrical with respect to the chip, and prevents fluctuations in device characteristics due to thermal cycles or electrical resistance of semiconductor devices. A highly reliable semiconductor device with small variations in characteristics can be obtained.

以下実施例に基づいてこの発明を説明する。第２図は本
発明によるリードフレームの一実施例を示すＳＩＬ形半
導体装置の平面断面図である。本実施例のリードフレー
ムにおいて、１１はダミーリードを有したインナーリー
ドであり、１２はアウターリード、３はチップ、４は金
線、５はレジンモールド樹脂である。Ｙ　−Ｙ’軸に平
行な方向に生じる収縮歪がアウターリード側で生じる収
縮歪とバランスするよう、インナーリード１１にアウタ
ーリードとは反対方向に延びたダミーリードが設けられ
ている。The present invention will be explained below based on Examples. FIG. 2 is a plan sectional view of an SIL type semiconductor device showing one embodiment of a lead frame according to the present invention. In the lead frame of this embodiment, 11 is an inner lead having a dummy lead, 12 is an outer lead, 3 is a chip, 4 is a gold wire, and 5 is a resin molding resin. The inner lead 11 is provided with a dummy lead extending in the opposite direction to the outer lead so that the shrinkage strain occurring in the direction parallel to the Y-Y' axis is balanced with the shrinkage strain occurring on the outer lead side.

このような構造のリードフレームを用いたＳＩＬ形半導
体装置ではダミーリードが樹脂成形時及びその後の熱ス
トレスを受けた時に緩衝剤となり収縮歪のバランスがと
れ、デバイス特性の変動を小さくかつ再現性のある従っ
て製造条件によシテップの受ける応力のコントロールを
可能にすることができる。In an SIL type semiconductor device using a lead frame with this structure, the dummy leads act as a buffer during resin molding and when subjected to subsequent thermal stress, and balance the shrinkage strain, minimizing fluctuations in device characteristics and improving reproducibility. Therefore, it is possible to control the stress to which the sheet is subjected depending on the manufacturing conditions.

なお、上記実施例ではダミーリードの数がアウターリー
ドの数と同一数になっているが、収縮歪のバランスが得
られればリードの数は異ってもよい。またダミーリード
の巾についても同様に、収縮歪のバランスが得られれば
異った巾でもよい。In the above embodiment, the number of dummy leads is the same as the number of outer leads, but the number of leads may be different as long as the balance of shrinkage strain is achieved. Similarly, the width of the dummy lead may be different as long as the shrinkage strain is balanced.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は現行の、第２図はこの発明のリードフレームを
用いたＳＩＬ形半導体装置の夫々の平面断面図である。 １．１１・・・・・・インナーリード、２．１２・・・
・・・アウターリード、３・・・・・・チップ、４・・
・・・・金線、５・・・・・・レジンモールド樹脂。FIG. 1 is a plan sectional view of an SIL type semiconductor device using the current lead frame, and FIG. 2 is a plan sectional view of an SIL type semiconductor device using the lead frame of the present invention. 1.11... Inner lead, 2.12...
...Outer lead, 3...Tip, 4...
...Gold wire, 5...Resin mold resin.

Claims (1)

【特許請求の範囲】[Claims] シングルインライン形半導体装置において、アウターリ
ードに対して最も離れた位置に配置されたインナーリー
ドに、アウターリードを取シ出している面に相対する方
向にダミーリードが設けられていることを特徴とする半
導体装置。In a single in-line type semiconductor device, a dummy lead is provided on the inner lead located farthest from the outer lead in a direction opposite to the surface from which the outer lead is taken out. Semiconductor equipment.
JP57207001A 1982-11-26 1982-11-26 Single in-line type semiconductor device Pending JPS5998549A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57207001A JPS5998549A (en) 1982-11-26 1982-11-26 Single in-line type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57207001A JPS5998549A (en) 1982-11-26 1982-11-26 Single in-line type semiconductor device

Publications (1)

Publication Number Publication Date
JPS5998549A true JPS5998549A (en) 1984-06-06

Family

ID=16532543

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57207001A Pending JPS5998549A (en) 1982-11-26 1982-11-26 Single in-line type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5998549A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4949161A (en) * 1988-12-23 1990-08-14 Micron Technology, Inc. Interdigitized leadframe strip
US5432127A (en) * 1989-06-30 1995-07-11 Texas Instruments Incorporated Method for making a balanced capacitance lead frame for integrated circuits having a power bus and dummy leads

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4949161A (en) * 1988-12-23 1990-08-14 Micron Technology, Inc. Interdigitized leadframe strip
US5432127A (en) * 1989-06-30 1995-07-11 Texas Instruments Incorporated Method for making a balanced capacitance lead frame for integrated circuits having a power bus and dummy leads

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