GB2278956A - Integrated circuit with multiple relative offset bond pad array - Google Patents

Integrated circuit with multiple relative offset bond pad array Download PDF

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Publication number
GB2278956A
GB2278956A GB9411399A GB9411399A GB2278956A GB 2278956 A GB2278956 A GB 2278956A GB 9411399 A GB9411399 A GB 9411399A GB 9411399 A GB9411399 A GB 9411399A GB 2278956 A GB2278956 A GB 2278956A
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Prior art keywords
bond pads
integrated circuit
array
chip
bond
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Granted
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GB9411399A
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GB9411399D0 (en
GB2278956B (en
Inventor
Junior Donald Earl Hawk
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AT&T Corp
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AT&T Corp
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Publication of GB2278956B publication Critical patent/GB2278956B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/494—Connecting portions
    • H01L2224/4943—Connecting portions the connecting portions being staggered
    • H01L2224/49431—Connecting portions the connecting portions being staggered on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The size of an integrated circuit chip, 1, may be decreased by offsetting the bond pads 3 with respect to the edge of the chip. Offsetting the bond pads permits the average bond pad spacing to be reduced and thereby reduces the length of the bond pad array. <IMAGE>

Description

INTEGRATED CIRCUIT WITH MULTIPLE RELATIVE OFFSET BOND PAD ARRAY Technical Field This invention relates to the field of integrated circuit packages and to the integrated circuit chips within the packages.
Background of the Invention An integrated circuit, such as one formed with silicon die, package has an integrated circuit chip which is mounted on a die attach area. The circuit must be electrically contacted to the external pins of the package. The components of the integrated circuit, in what is termed the core area, are connected to a series of what are termed bond pads on the periphery of the chip. These bond pads are conductive areas above which the protective layer covering the chip has been removed. Wires are connected from these bond pads to the conductive paths of the package which lead to the external pins.
An exemplary method of forming the wire connection uses what is commonly termed the ball wedge. According to this method, a ball is formed on one end of the wire. The end of the wire with the ball is subsequently bonded to the bond pad and the other end of the wire is bonded to a specified wedge bond area of the conductive path in the package. The distance from the ball bond to the wedge bond is termed the wire span.
As the components of integrated circuits decrease in size and as the number of components on the integrated circuits increases, the number of electrical contacts to the integrated circuit of a given size also typically increases. The final size of the silicon is constrained by either the size of the core area or by the requirements imposed on the bond pad spacings around the periphery of the chip. It is, of course, desirable to minimize the amount of silicon needed for the integrated circuit.
Decreasing the bond pad spacing in order to minimize the silicon area makes the wire bonding process more difficult as is evident from consideration of the following. There must be a minimum center to center spacing between the bond pads so that the ball applied to one pad does not also contact an adjacent pad and create an electrical short circuit The size of the bond pad itself may decrease as spacings decrease in order to satisfy silicon design rules. The wire bond ball size must be sufficiently small to be placed on the bond pad. However, decreasing the wire bond ball size beyond a certain limit adversely affects the integrity of the connection. Additionally, the electrical circuitry attaching the bond pads with the electrical components of the core area may require the pads to be spaced apart a certain minimum distance. The equipment used in the wire bonding process requires sufficient clearances so that adjacent wires are not disturbed during the ball placement and bonding operations. Furthermore, the wires are very small in diameter and move easily during the subsequent assembly processes. The possibility of such movement and the resulting electrical shorts between adjacent wires requires that a minimum separation rule between the wires be established for the wire bonding process. Of course, the wire separation requirements maybe a function of wire span.
Exemplary technology presently has bond pads arranged in a straight or fixed relative offset array on at least two, and frequently four, sides of the integrated circuit chip. The conductive paths of the package are relatively large in comparison to the bond pads. Accordingly, the wires in the middle of the chip are approximately perpendicular to the side of the chip, but the wires near the corners of the chip are not perpendicular to the side of the chip. In the center of the chip, bond pad spacing is dictated by the minimum center-to-center spacing which is greater than what would be required based solely upon minimum wire separation criteria alone.
Adjacent bond pads may have a relative offset and be spaced closer together than the minimum straight bond pad pitch would permit. However, toward the corners of the chip, the deviation of the wire from perpendicularity may require, based on minimum wire separation, that the bond pads be spaced at distances greater than the minimum straight bond pad pitch or the pitch used for the offset bond pads. Thus, the bond pad locations are constrained by two factors: 1) the bond pads must have a minimum center to center spacing; and 2) the wires must have a minimum separation.
An arrangement of bond pads which minimizes the silicon area while still satisfying all silicon packaging considerations is desirable.
Summary of the Invention According to an exemplary embodiment of this invention, an integrated circuit chip has at least one bond pad array on a side of the chip with at least two pairs of adjacent bond pads having at least two values of relative offsets. That is, the array of bond pads has at least two different values of relative offsets. The spacings between the bond pads are varied, and adjacent bond pads are closer together when there is a relative offset than they are for at least two bond pads without a relative offset. The spacing between bond pads is measured from center-to-center. In another exemplary embodiment, an integrated circuit package is formed by mounting the chip in the die attach area and using a plurality of wires to connect the bond pads to wedge bond areas located on conductive paths of the package. For both embodiments, the choice of the relative offsets and the spacing of the bond pads within the arrays is such that the average bond pad spacing is minimized while satisfying other constraints.
Brief Descn'ption of the Drawing FIG. 1 is a top view of an exemplary embodiment of this invention showing an integrated circuit chip and a portion of the conductive paths leading to the external pins of the package; and FIG. 2 shows a portion of the embodiment depicted in FIG. 1.
For reasons of clarity, the elements depicted are not drawn to scale.
Identical numerals in different FIGURES represent identical elements.
Detailed Description The invention will be described by reference to an exemplary embodiment. Depicted in FIG. 1 are an integrated circuit chip 1 having a plurality of bond pads 3. Chip 1 is mounted in the die attach area 5. The center of the chip, that is, the core area, contains the integrated circuit which is not depicted for reasons of clarity. Such circuits are well known. There is a plurality of conductive paths 7, and a plurality of wires 9 with each wire having one end connected to a bond pad 3 and one end connected to a conductive path 7. Both the bond pads and the conductive paths are arranged in arrays. The bond pad arrays are located on the periphery of the chip. Within an array, the bond pads have multiple relative offsets with respect to the sides of the chip, and the spacings between adjacent bond pads may vary, that is, the inter-bond pad spacings are not constant. There is one array of each per chip side. In the region between the bond pads 3 and the conductive paths 7, the wires 9 are spaced apart at least a minimum distance s. As can be seen, the arrays of conductive paths 7 are longer than are the arrays of bond pads 3.
The elements depicted will be readily fabricated, using present techniques, by those skilled in the art except for the arrangement of the bond pads which will be explained in detail later. The components of the integrated circuit in the core area are well known, as are techniques for their manufacture, and are not shown for reasons of clarity. Techniques for fabricating the conductive paths and mounting the chip on the die attach area are also well known and need not be described. Techniques for bonding the wires to both the bond pads and the die attach area are well known. The elements depicted are protected from the external environment by the body of the package(not shown) and an integrated circuit package with external electrical connections is thus formed.
In contrast to prior art packages and chips, there are multiple relative offsets for adjacent bond pads. The spacing between adjacent bond pads may also vary. The offset is frequently the distance between the edge of the chip and the bond pad. The relative offset is frequently the difference in the offsets of two adjacent bond pads. Of course, the offsets may be measured from other reference points such as the center line of the chip. Regardless of the reference point used, the relative offset will be the same. If there is no difference in offsets, there is no relative offset.
There may be more than two values for the offsets, and there is more than one value for the relative offset. Having multiple relative offsets means that it will be possible to select, on a given side of the chip, at least two pairs of consecutive bond pads whose relative offsets are a different amount The choice of relative offsets between two adjacent bond pads is that which minimizes the spacing between bond pads and meets all other silicon and packaging constraints; that is minimum center to center spacing and minimum wire separation. When adjacent bond pads have a relative offset, the lateral center to center separation of the bond pads may be less, and generally is less, than it is when there is no relative offset. The relative offset within an array varies. Of course, variations in distances used to measure offsets which are due to alignment errors or processing steps are not considered; the differences are the result of design. All other silicon and packaging technology being equal, this arrangement of bond pads results in chips that are smaller than those fabricated with fixed relative offsets.
This is better understood by reference to FIG. 2 which shows a portion of the embodiment depicted in FIG. 1. In particular, a portion of a bond pad array is depicted in detail. As is evident, the bond pads are not a constant distance from the edge of the chip. That is, they do not have a constant offset, and adjacent bond pads may have a relative offsets Within an array, the relative offset is a variable. The bond pads in the middle of the array have a relative offset Near the ends of the array, except for the end members, there is no or zero relative offset between adjacent bond pads. The spacing between adjacent bond pads also varies. That is, there are at least two values of lateral spacing within the array. The lateral spacing is larger near the ends of the array where there is no relative offset between adjacent bond pads than it is in the center of the array where there are relative offsets between adjacent bond pads. The size of the relative offset and bond pad spacing will be readily determined by those skilled in the art Variations of the embodiment described will be readily thought of by those skilled in the arl For example, the embodiment described bond pads having two offset values in the middle of the array. However, the invention is more generally applicable to arrays of bond pads having three, four, etc. offset values in the array. The conductive paths may be on a lead frame or in a ceramic package.
Additionally, all arrays need not be the same distance from the reference point.

Claims (6)

Claims:
1. An integrated circuit chip (e.g., 1) having a plurality of sides comprising: at least one array of bond pads (e.g., 3), said array comprising a plurality of bond pads (e.g., 3), at least two pairs of adjacent bond pads of said plurality of bond pads (e.g., 3) having at least two values of relative offset
2. An integrated circuit chip as recited in claim 1 in which at least one array of bond pads (e.g., 3) has at least two values of lateral spacing between adjacent bond pads.
3. An integrated circuit as recited in claim 2 in which said bond pads (e.g., 3) of said array have at least three offset values.
4. An integrated circuit package comprising: a plurality of conductive paths (e.g., 7); a die attach area (e.g., 5); an integrated circuit chip (e.g., 1), said chip (e.g., 1) being mounted in said die attach area (e.g., 5) and having a plurality of sides, comprising at least one array of bond pads (e.g., 3) having a plurality of bond pads (e.g., 3), at least two pairs of adjacent bond pads (e.g., 3) of said plurality of bond pads (e.g., 3) having at least two values relative offset; and a plurality of wires (e.g., 9), each of said wires (e.g., 9) being connected to one bond pad (e.g., 3) and one conductive path (e.g., 7).
5. An integrated circuit package as recited in claim 4 in which said at least one array of bond pads (e.g., 3) has at least two values lateral spacing between adjacent bond pads.
6. An integrated circuit chip as recited in claim 5 in which said bond pads (e.g., 3) have at least three offset values.
GB9411399A 1993-06-09 1994-06-07 Integrated circuit with multiple relative offset bond pad array Expired - Fee Related GB2278956B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19652395A1 (en) * 1996-06-13 1997-12-18 Samsung Electronics Co Ltd Integrated circuit module

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0382445A2 (en) * 1989-02-10 1990-08-16 Honeywell Inc. High density bond pad design
EP0459493A2 (en) * 1990-06-01 1991-12-04 Kabushiki Kaisha Toshiba A semiconductor device using a lead frame and its manufacturing method

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63252434A (en) * 1987-04-09 1988-10-19 Nec Corp Semiconductor integrated circuit device
JP2932785B2 (en) * 1991-09-20 1999-08-09 富士通株式会社 Semiconductor device
KR100306988B1 (en) * 1992-10-26 2001-12-15 윌리엄 비. 켐플러 Device Package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0382445A2 (en) * 1989-02-10 1990-08-16 Honeywell Inc. High density bond pad design
EP0459493A2 (en) * 1990-06-01 1991-12-04 Kabushiki Kaisha Toshiba A semiconductor device using a lead frame and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19652395A1 (en) * 1996-06-13 1997-12-18 Samsung Electronics Co Ltd Integrated circuit module
FR2749975A1 (en) * 1996-06-13 1997-12-19 Samsung Electronics Co Ltd SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A HIGH NUMBER OF INPUT / OUTPUT CONNECTIONS

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JPH0799213A (en) 1995-04-11
KR950001996A (en) 1995-01-04
GB9411399D0 (en) 1994-07-27
GB2278956B (en) 1997-10-08

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Effective date: 20080607