JPS5976442A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPS5976442A
JPS5976442A JP18784382A JP18784382A JPS5976442A JP S5976442 A JPS5976442 A JP S5976442A JP 18784382 A JP18784382 A JP 18784382A JP 18784382 A JP18784382 A JP 18784382A JP S5976442 A JPS5976442 A JP S5976442A
Authority
JP
Japan
Prior art keywords
film
etching
substrate
insulating film
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18784382A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0478013B2 (enrdf_load_stackoverflow
Inventor
Ryozo Nakayama
中山　良三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP18784382A priority Critical patent/JPS5976442A/ja
Publication of JPS5976442A publication Critical patent/JPS5976442A/ja
Publication of JPH0478013B2 publication Critical patent/JPH0478013B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)
JP18784382A 1982-10-26 1982-10-26 半導体装置の製造方法 Granted JPS5976442A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18784382A JPS5976442A (ja) 1982-10-26 1982-10-26 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18784382A JPS5976442A (ja) 1982-10-26 1982-10-26 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS5976442A true JPS5976442A (ja) 1984-05-01
JPH0478013B2 JPH0478013B2 (enrdf_load_stackoverflow) 1992-12-10

Family

ID=16213194

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18784382A Granted JPS5976442A (ja) 1982-10-26 1982-10-26 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JPS5976442A (enrdf_load_stackoverflow)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59114823A (ja) * 1982-12-21 1984-07-03 Agency Of Ind Science & Technol 半導体装置の平坦化方法
JPH01290236A (ja) * 1988-05-03 1989-11-22 Internatl Business Mach Corp <Ibm> 幅の広いトレンチを平坦化する方法
JPH03148155A (ja) * 1989-10-25 1991-06-24 Internatl Business Mach Corp <Ibm> 誘電体充填分離トレンチ形成方法
US5077234A (en) * 1990-06-29 1991-12-31 Digital Equipment Corporation Planarization process utilizing three resist layers

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5363871A (en) * 1976-11-18 1978-06-07 Matsushita Electric Ind Co Ltd Production of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5363871A (en) * 1976-11-18 1978-06-07 Matsushita Electric Ind Co Ltd Production of semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59114823A (ja) * 1982-12-21 1984-07-03 Agency Of Ind Science & Technol 半導体装置の平坦化方法
JPH01290236A (ja) * 1988-05-03 1989-11-22 Internatl Business Mach Corp <Ibm> 幅の広いトレンチを平坦化する方法
JPH03148155A (ja) * 1989-10-25 1991-06-24 Internatl Business Mach Corp <Ibm> 誘電体充填分離トレンチ形成方法
US5077234A (en) * 1990-06-29 1991-12-31 Digital Equipment Corporation Planarization process utilizing three resist layers

Also Published As

Publication number Publication date
JPH0478013B2 (enrdf_load_stackoverflow) 1992-12-10

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