JPS5972035U - polarized signal receiver - Google Patents
polarized signal receiverInfo
- Publication number
- JPS5972035U JPS5972035U JP19343082U JP19343082U JPS5972035U JP S5972035 U JPS5972035 U JP S5972035U JP 19343082 U JP19343082 U JP 19343082U JP 19343082 U JP19343082 U JP 19343082U JP S5972035 U JPS5972035 U JP S5972035U
- Authority
- JP
- Japan
- Prior art keywords
- output
- polarized signal
- gates
- pair
- terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案の一実施例を示す接続図、第２図はこ
の考案の動作を説明するための波形図である。
１１：有極信号受信装置、１２ａ、１２ｂニアオドカプ
ラ、１３：雑音除去回路、１３ａ、 １３ｂ：第１ゲ
ート、１３Ｃ，１３ｄ：第２ゲート、１３ｅ。
１３ｆ：カウンタ。
オ哩 イ「「口 ？
１□□□□−’ Ｄ−ｔ−１ｌ
ｌ゛ １日FIG. 1 is a connection diagram showing an embodiment of this invention, and FIG. 2 is a waveform diagram for explaining the operation of this invention. 11: polarized signal receiving device, 12a, 12b near-odd coupler, 13: noise removal circuit, 13a, 13b: first gate, 13C, 13d: second gate, 13e. 13f: Counter. Oh, I: “Mouth? 1□□□□-’ D-t-1l
l゛ 1 day
Claims (1)
１ゲートと、 Ｂ この一対の第１ゲートのそれぞれの出力がリセット
端子に与えられ、所定の計数出力端子の出力を反対側の
ゲートの一方の入力端子に与えてその反対側のゲートを
閉じるように制御する一対のカウンタと、 Ｃ上記第１ゲートの出力が一方の入力端子に与えられ、
上記カウンタの所定の計数出力端子の出力が遅延回路を
通じて与えられ、上記ゲートの一方に有極信号が与えら
れたとき出力を発生する一対の第２ゲートと、 Ｄ この一対の第２ゲートの出力によってセット、リセ
ットが繰返されるフリップフロップと、から成る有極信
号受信装置。[Claims for Utility Model Registration] A: A pair of first gates to which a signal of one polarity of the polarized signal is applied, and B: The output of each of the pair of first gates is applied to a reset terminal, and a predetermined counting output is obtained. a pair of counters that control the output of the terminal to be applied to one input terminal of the gate on the opposite side to close the gate on the opposite side;
a pair of second gates, to which the output of a predetermined counting output terminal of the counter is applied through a delay circuit, and which generates an output when a polarized signal is applied to one of the gates; A polarized signal receiving device consisting of a flip-flop that is repeatedly set and reset by
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19343082U JPS5972035U (en) | 1982-12-20 | 1982-12-20 | polarized signal receiver |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19343082U JPS5972035U (en) | 1982-12-20 | 1982-12-20 | polarized signal receiver |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5972035U true JPS5972035U (en) | 1984-05-16 |
Family
ID=30416029
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19343082U Pending JPS5972035U (en) | 1982-12-20 | 1982-12-20 | polarized signal receiver |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5972035U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02141017A (en) * | 1988-11-21 | 1990-05-30 | Meidensha Corp | Transmitter-receiver using pulse transformer |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5263054A (en) * | 1975-11-19 | 1977-05-25 | Hitachi Ltd | Pulse signal detecting circuit |
-
1982
- 1982-12-20 JP JP19343082U patent/JPS5972035U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5263054A (en) * | 1975-11-19 | 1977-05-25 | Hitachi Ltd | Pulse signal detecting circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02141017A (en) * | 1988-11-21 | 1990-05-30 | Meidensha Corp | Transmitter-receiver using pulse transformer |
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