JPS5928733U - Pulse input device - Google Patents

Pulse input device

Info

Publication number
JPS5928733U
JPS5928733U JP12445082U JP12445082U JPS5928733U JP S5928733 U JPS5928733 U JP S5928733U JP 12445082 U JP12445082 U JP 12445082U JP 12445082 U JP12445082 U JP 12445082U JP S5928733 U JPS5928733 U JP S5928733U
Authority
JP
Japan
Prior art keywords
input device
counter
pulse input
count
pulse train
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12445082U
Other languages
Japanese (ja)
Inventor
菅野 不二夫
Original Assignee
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河電機株式会社 filed Critical 横河電機株式会社
Priority to JP12445082U priority Critical patent/JPS5928733U/en
Publication of JPS5928733U publication Critical patent/JPS5928733U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のパルス入力装置を示す回路図、第2図は
アナログ信号を示す波形図、第3図はパルス列信号を示
す波形図、第4図は本考案の第1の実施例を示す回路図
、第5図は本考案の第2の実施例を示す回路図である。 図面中、2. 2’はカウンタ、5,6はナンド回路、
7はラッチ回路、bはパルス列信号である。
Fig. 1 is a circuit diagram showing a conventional pulse input device, Fig. 2 is a waveform diagram showing an analog signal, Fig. 3 is a waveform diagram showing a pulse train signal, and Fig. 4 shows a first embodiment of the present invention. Circuit Diagram FIG. 5 is a circuit diagram showing a second embodiment of the present invention. In the drawing, 2. 2' is a counter, 5 and 6 are NAND circuits,
7 is a latch circuit, and b is a pulse train signal.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] パルス列信号を計数するカウンタを具備し、このカウン
タにより計数されたカウント数は一定時間毎に出力され
てコンピュータに読み込まれるパルス入力装置において
、前記カウント数がカウンタの最大計数値であるフルカ
ウントになると前記パルス列信号を通過させないように
なっているゲート回路を備え、このゲート回路を介して
前記パルス列信号を前記カウンタに入力することを特徴
とするパルス入力装置。
In a pulse input device that is equipped with a counter that counts pulse train signals, and in which the count counted by the counter is outputted at regular intervals and read into a computer, when the count reaches a full count, which is the maximum count of the counter, A pulse input device comprising a gate circuit configured not to pass a pulse train signal, and inputting the pulse train signal to the counter via the gate circuit.
JP12445082U 1982-08-19 1982-08-19 Pulse input device Pending JPS5928733U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12445082U JPS5928733U (en) 1982-08-19 1982-08-19 Pulse input device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12445082U JPS5928733U (en) 1982-08-19 1982-08-19 Pulse input device

Publications (1)

Publication Number Publication Date
JPS5928733U true JPS5928733U (en) 1984-02-22

Family

ID=30283690

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12445082U Pending JPS5928733U (en) 1982-08-19 1982-08-19 Pulse input device

Country Status (1)

Country Link
JP (1) JPS5928733U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009049496A (en) * 2007-08-14 2009-03-05 Yokogawa Electric Corp Pulse detector

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009049496A (en) * 2007-08-14 2009-03-05 Yokogawa Electric Corp Pulse detector

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